diff --git a/insns/InsnLw.py b/insns/InsnLw.py
new file mode 100644
index 0000000..c4e9e6d
--- /dev/null
+++ b/insns/InsnLw.py
@@ -0,0 +1,9 @@
+from InsnRV32IITypeLoad import *
+
+"""
+LW instruction
+"""
+
+class InsnLw(InsnRV32IITypeLoad):
+    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM):
+        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM, 0b010, 4, True)
diff --git a/insns/InsnRV32IITypeLoad.py b/insns/InsnRV32IITypeLoad.py
index 9bc6e6b..8dba77c 100644
--- a/insns/InsnRV32IITypeLoad.py
+++ b/insns/InsnRV32IITypeLoad.py
@@ -30,7 +30,7 @@ class InsnRV32IITypeLoad(InsnRV32IIType):
             m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
             m.d.comb += self.spec_mem_addr.eq(self.addr & ~(int(self.RISCV_FORMAL_XLEN // 8) - 1))
             m.d.comb += self.spec_mem_rmask.eq(((1 << self.mask_shift) - 1) << (self.addr - self.spec_mem_addr))
-            m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(result) if self.is_signed else result, 0))
+            m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(self.result) if self.is_signed else self.result, 0))
             m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
             m.d.comb += self.spec_trap.eq(((self.addr & (self.mask_shift - 1)) != 0) | ~self.misa_ok)
         else: