Modularize codebase

cores/minerva/.gitignore

@@ -1,14 +0,0 @@
-# Python
-__pycache__/
-/*.egg-info
-/.eggs
-
-# tests
-**/test/spec_*/
-*.vcd
-*.gtkw
-
-# misc user-created
-*.il
-*.v
-/build

cores/minerva/cli.py

@@ -1,114 +0,0 @@
-import argparse
-import warnings
-from nmigen import cli
-
-from minerva.core import Minerva
-
-
-def main():
-    parser = argparse.ArgumentParser(formatter_class=argparse.ArgumentDefaultsHelpFormatter)
-
-    parser.add_argument("--reset-addr",
-            type=lambda s: int(s, 16), default="0x00000000",
-            help="reset vector address")
-
-    parser.add_argument("--with-icache",
-            default=False, action="store_true",
-            help="enable the instruction cache")
-    parser.add_argument("--with-dcache",
-            default=False, action="store_true",
-            help="enable the data cache")
-    parser.add_argument("--with-muldiv",
-            default=False, action="store_true",
-            help="enable RV32M support")
-    parser.add_argument("--with-debug",
-            default=False, action="store_true",
-            help="enable the Debug Module")
-    parser.add_argument("--with-trigger",
-            default=False, action="store_true",
-            help="enable the Trigger Module")
-    parser.add_argument("--with-rvfi",
-            default=False, action="store_true",
-            help="enable the riscv-formal interface")
-
-    icache_group = parser.add_argument_group("icache options")
-    icache_group.add_argument("--icache-nways",
-            type=int, choices=[1, 2], default=1,
-            help="number of ways")
-    icache_group.add_argument("--icache-nlines",
-            type=int, default=32,
-            help="number of lines")
-    icache_group.add_argument("--icache-nwords",
-            type=int, choices=[4, 8, 16], default=4,
-            help="number of words in a line")
-    icache_group.add_argument("--icache-base",
-            type=lambda s: int(s, 16), default="0x00000000",
-            help="base address")
-    icache_group.add_argument("--icache-limit",
-            type=lambda s: int(s, 16), default="0x80000000",
-            help="limit address")
-
-    dcache_group = parser.add_argument_group("dcache options")
-    dcache_group.add_argument("--dcache-nways",
-            type=int, choices=[1, 2], default=1,
-            help="number of ways")
-    dcache_group.add_argument("--dcache-nlines",
-            type=int, default=32,
-            help="number of lines")
-    dcache_group.add_argument("--dcache-nwords",
-            type=int, choices=[4, 8, 16], default=4,
-            help="number of words in a line")
-    dcache_group.add_argument("--dcache-base",
-            type=lambda s: int(s, 16), default="0x00000000",
-            help="base address")
-    dcache_group.add_argument("--dcache-limit",
-            type=lambda s: int(s, 16), default="0x80000000",
-            help="limit address")
-
-    trigger_group = parser.add_argument_group("trigger options")
-    trigger_group.add_argument("--nb-triggers",
-            type=int, default=8,
-            help="number of triggers")
-
-    cli.main_parser(parser)
-
-    args = parser.parse_args()
-
-    if args.with_debug and not args.with_trigger:
-        warnings.warn("Support for hardware breakpoints requires --with-trigger")
-
-    cpu = Minerva(args.reset_addr,
-            args.with_icache, args.icache_nways, args.icache_nlines, args.icache_nwords,
-            args.icache_base, args.icache_limit,
-            args.with_dcache, args.dcache_nways, args.dcache_nlines, args.dcache_nwords,
-            args.dcache_base, args.dcache_limit,
-            args.with_muldiv,
-            args.with_debug,
-            args.with_trigger, args.nb_triggers,
-            args.with_rvfi)
-
-    ports = [
-        cpu.external_interrupt, cpu.timer_interrupt, cpu.software_interrupt,
-        cpu.ibus.ack, cpu.ibus.adr, cpu.ibus.bte, cpu.ibus.cti, cpu.ibus.cyc, cpu.ibus.dat_r,
-        cpu.ibus.dat_w, cpu.ibus.sel, cpu.ibus.stb, cpu.ibus.we, cpu.ibus.err,
-        cpu.dbus.ack, cpu.dbus.adr, cpu.dbus.bte, cpu.dbus.cti, cpu.dbus.cyc, cpu.dbus.dat_r,
-        cpu.dbus.dat_w, cpu.dbus.sel, cpu.dbus.stb, cpu.dbus.we, cpu.dbus.err
-    ]
-
-    if args.with_debug:
-        ports += [cpu.jtag.tck, cpu.jtag.tdi, cpu.jtag.tdo, cpu.jtag.tms]
-
-    if args.with_rvfi:
-        ports += [
-            cpu.rvfi.valid, cpu.rvfi.order, cpu.rvfi.insn, cpu.rvfi.trap, cpu.rvfi.halt,
-            cpu.rvfi.intr, cpu.rvfi.mode, cpu.rvfi.ixl, cpu.rvfi.rs1_addr, cpu.rvfi.rs2_addr,
-            cpu.rvfi.rs1_rdata, cpu.rvfi.rs2_rdata, cpu.rvfi.rd_addr, cpu.rvfi.rd_wdata,
-            cpu.rvfi.pc_rdata, cpu.rvfi.pc_wdata, cpu.rvfi.mem_addr, cpu.rvfi.mem_rmask,
-            cpu.rvfi.mem_wmask, cpu.rvfi.mem_rdata, cpu.rvfi.mem_wdata
-        ]
-
-    cli.main_runner(parser, args, cpu, name="minerva_cpu", ports=ports)
-
-
-if __name__ == "__main__":
-    main()

cores/minerva/setup.py

@@ -1,19 +0,0 @@
-from setuptools import setup, find_packages
-
-
-setup(
-    name="minerva",
-    version="0.1",
-    description="A 32-bit RISC-V soft processor",
-    author="Jean-François Nguyen",
-    author_email="jf@lambdaconcept.com",
-    license="BSD",
-    python_requires="~=3.6",
-    install_requires=["nmigen>=0.1rc1"],
-    extras_require={ "debug": ["jtagtap"] },
-    packages=find_packages(),
-    project_urls={
-        "Source Code": "https://github.com/lambdaconcept/minerva",
-        "Bug Tracker": "https://github.com/lambdaconcept/minerva/issues"
-    }
-)

rvfi/insns/insn_add.py

@@ -1,4 +1,4 @@
-from insn_rv32i_r_type import *
+from .insn_rv32i_r_type import *
 
 """
 ADD instruction

rvfi/insns/insn_addi.py

@@ -1,4 +1,4 @@
-from insn_rv32i_i_type_arith import *
+from .insn_rv32i_i_type_arith import *
 
 """
 ADDI instruction

rvfi/insns/insn_and.py

@@ -1,4 +1,4 @@
-from insn_rv32i_r_type import *
+from .insn_rv32i_r_type import *
 
 """
 AND instruction

rvfi/insns/insn_andi.py

@@ -1,4 +1,4 @@
-from insn_rv32i_i_type_arith import *
+from .insn_rv32i_i_type_arith import *
 
 """
 ANDI instruction

rvfi/insns/insn_auipc.py

@@ -1,4 +1,4 @@
-from insn_rv32i_u_type import *
+from .insn_rv32i_u_type import *
 
 """
 AUIPC instruction

rvfi/insns/insn_beq.py

@@ -1,4 +1,4 @@
-from insn_rv32i_sb_type import *
+from .insn_rv32i_sb_type import *
 
 """
 BEQ instruction

rvfi/insns/insn_bge.py

@@ -1,4 +1,4 @@
-from insn_rv32i_sb_type import *
+from .insn_rv32i_sb_type import *
 
 """
 BGE instruction

rvfi/insns/insn_bgeu.py

@@ -1,4 +1,4 @@
-from insn_rv32i_sb_type import *
+from .insn_rv32i_sb_type import *
 
 """
 BGEU instruction

rvfi/insns/insn_blt.py

@@ -1,4 +1,4 @@
-from insn_rv32i_sb_type import *
+from .insn_rv32i_sb_type import *
 
 """
 BLT instruction

rvfi/insns/insn_bltu.py

@@ -1,4 +1,4 @@
-from insn_rv32i_sb_type import *
+from .insn_rv32i_sb_type import *
 
 """
 BLTU instruction

rvfi/insns/insn_bne.py

@@ -1,4 +1,4 @@
-from insn_rv32i_sb_type import *
+from .insn_rv32i_sb_type import *
 
 """
 BNE instruction

rvfi/insns/insn_jal.py

@@ -1,4 +1,4 @@
-from insn import *
+from .insn import *
 
 """
 JAL instruction

rvfi/insns/insn_jalr.py

@@ -1,4 +1,4 @@
-from insn_rv32i_i_type import *
+from .insn_rv32i_i_type import *
 
 """
 JALR instruction

rvfi/insns/insn_lb.py

@@ -1,4 +1,4 @@
-from insn_rv32i_i_type_load import *
+from .insn_rv32i_i_type_load import *
 
 """
 LB instruction

rvfi/insns/insn_lbu.py

@@ -1,4 +1,4 @@
-from insn_rv32i_i_type_load import *
+from .insn_rv32i_i_type_load import *
 
 """
 LBU instruction

rvfi/insns/insn_lh.py

@@ -1,4 +1,4 @@
-from insn_rv32i_i_type_load import *
+from .insn_rv32i_i_type_load import *
 
 """
 LH instruction

rvfi/insns/insn_lhu.py

@@ -1,4 +1,4 @@
-from insn_rv32i_i_type_load import *
+from .insn_rv32i_i_type_load import *
 
 """
 LHU instruction

rvfi/insns/insn_lui.py

@@ -1,4 +1,4 @@
-from insn_rv32i_u_type import *
+from .insn_rv32i_u_type import *
 
 """
 LUI instruction

rvfi/insns/insn_lw.py

@@ -1,4 +1,4 @@
-from insn_rv32i_i_type_load import *
+from .insn_rv32i_i_type_load import *
 
 """
 LW instruction

rvfi/insns/insn_or.py

@@ -1,4 +1,4 @@
-from insn_rv32i_r_type import *
+from .insn_rv32i_r_type import *
 
 """
 OR instruction

rvfi/insns/insn_ori.py

@@ -1,4 +1,4 @@
-from insn_rv32i_i_type_arith import *
+from .insn_rv32i_i_type_arith import *
 
 """
 ORI instruction

rvfi/insns/insn_rv32i_i_type.py

@@ -1,4 +1,4 @@
-from insn import *
+from .insn import *
 
 """
 RV32I I-Type Instruction

rvfi/insns/insn_rv32i_i_type_arith.py

@@ -1,4 +1,4 @@
-from insn_rv32i_i_type import *
+from .insn_rv32i_i_type import *
 
 """
 RV32I I-Type Instruction (Arithmetic Variation)

rvfi/insns/insn_rv32i_i_type_load.py

@@ -1,4 +1,4 @@
-from insn_rv32i_i_type import *
+from .insn_rv32i_i_type import *
 
 """
 RV32I I-Type Instruction (Load Variation)

rvfi/insns/insn_rv32i_i_type_shift.py

@@ -1,4 +1,4 @@
-from insn import *
+from .insn import *
 
 """
 RV32I I-Type Instruction (Shift Variation)

rvfi/insns/insn_rv32i_r_type.py

@@ -1,4 +1,4 @@
-from insn import *
+from .insn import *
 
 """
 RV32I R-Type Instruction

rvfi/insns/insn_rv32i_s_type.py

@@ -1,4 +1,4 @@
-from insn import *
+from .insn import *
 
 """
 RV32I S-Type Instruction

rvfi/insns/insn_rv32i_sb_type.py

@@ -1,4 +1,4 @@
-from insn import *
+from .insn import *
 
 """
 RV32I SB-Type Instruction

rvfi/insns/insn_rv32i_u_type.py

@@ -1,4 +1,4 @@
-from insn import *
+from .insn import *
 
 """
 RV32I U-Type Instruction

rvfi/insns/insn_sb.py

@@ -1,4 +1,4 @@
-from insn_rv32i_s_type import *
+from .insn_rv32i_s_type import *
 
 """
 SB instruction

rvfi/insns/insn_sh.py

@@ -1,4 +1,4 @@
-from insn_rv32i_s_type import *
+from .insn_rv32i_s_type import *
 
 """
 SH instruction

rvfi/insns/insn_sll.py

@@ -1,4 +1,4 @@
-from insn_rv32i_r_type import *
+from .insn_rv32i_r_type import *
 
 """
 SLL instruction

rvfi/insns/insn_slli.py

@@ -1,4 +1,4 @@
-from insn_rv32i_i_type_shift import *
+from .insn_rv32i_i_type_shift import *
 
 """
 SLLI instruction

rvfi/insns/insn_slt.py

@@ -1,4 +1,4 @@
-from insn_rv32i_r_type import *
+from .insn_rv32i_r_type import *
 
 """
 SLT instruction

rvfi/insns/insn_slti.py

@@ -1,4 +1,4 @@
-from insn_rv32i_i_type_arith import *
+from .insn_rv32i_i_type_arith import *
 
 """
 SLTI instruction

rvfi/insns/insn_sltiu.py

@@ -1,4 +1,4 @@
-from insn_rv32i_i_type_arith import *
+from .insn_rv32i_i_type_arith import *
 
 """
 SLTIU instruction

rvfi/insns/insn_sltu.py

@@ -1,4 +1,4 @@
-from insn_rv32i_r_type import *
+from .insn_rv32i_r_type import *
 
 """
 SLTU instruction

rvfi/insns/insn_sra.py

@@ -1,4 +1,4 @@
-from insn_rv32i_r_type import *
+from .insn_rv32i_r_type import *
 
 """
 SRA instruction

rvfi/insns/insn_srai.py

@@ -1,4 +1,4 @@
-from insn_rv32i_i_type_shift import *
+from .insn_rv32i_i_type_shift import *
 
 """
 SRAI instruction

rvfi/insns/insn_srl.py

@@ -1,4 +1,4 @@
-from insn_rv32i_r_type import *
+from .insn_rv32i_r_type import *
 
 """
 SRL instruction

rvfi/insns/insn_srli.py

@@ -1,4 +1,4 @@
-from insn_rv32i_i_type_shift import *
+from .insn_rv32i_i_type_shift import *
 
 """
 SRLI instruction

rvfi/insns/insn_sub.py

@@ -1,4 +1,4 @@
-from insn_rv32i_r_type import *
+from .insn_rv32i_r_type import *
 
 """
 SUB instruction

rvfi/insns/insn_sw.py

@@ -1,4 +1,4 @@
-from insn_rv32i_s_type import *
+from .insn_rv32i_s_type import *
 
 """
 SW instruction

rvfi/insns/insn_xor.py

@@ -1,4 +1,4 @@
-from insn_rv32i_r_type import *
+from .insn_rv32i_r_type import *
 
 """
 XOR instruction

rvfi/insns/insn_xori.py

@@ -1,4 +1,4 @@
-from insn_rv32i_i_type_arith import *
+from .insn_rv32i_i_type_arith import *
 
 """
 XORI instruction

rvfi/insns/isa_rv32i.py

@@ -1,40 +1,40 @@
-from insn_lui import *
+from .insn_lui import *
-from insn_auipc import *
+from .insn_auipc import *
-from insn_jal import *
+from .insn_jal import *
-from insn_jalr import *
+from .insn_jalr import *
-from insn_beq import *
+from .insn_beq import *
-from insn_bne import *
+from .insn_bne import *
-from insn_blt import *
+from .insn_blt import *
-from insn_bge import *
+from .insn_bge import *
-from insn_bltu import *
+from .insn_bltu import *
-from insn_bgeu import *
+from .insn_bgeu import *
-from insn_lb import *
+from .insn_lb import *
-from insn_lh import *
+from .insn_lh import *
-from insn_lw import *
+from .insn_lw import *
-from insn_lbu import *
+from .insn_lbu import *
-from insn_lhu import *
+from .insn_lhu import *
-from insn_sb import *
+from .insn_sb import *
-from insn_sh import *
+from .insn_sh import *
-from insn_sw import *
+from .insn_sw import *
-from insn_addi import *
+from .insn_addi import *
-from insn_slti import *
+from .insn_slti import *
-from insn_sltiu import *
+from .insn_sltiu import *
-from insn_xori import *
+from .insn_xori import *
-from insn_ori import *
+from .insn_ori import *
-from insn_andi import *
+from .insn_andi import *
-from insn_slli import *
+from .insn_slli import *
-from insn_srli import *
+from .insn_srli import *
-from insn_srai import *
+from .insn_srai import *
-from insn_add import *
+from .insn_add import *
-from insn_sub import *
+from .insn_sub import *
-from insn_sll import *
+from .insn_sll import *
-from insn_slt import *
+from .insn_slt import *
-from insn_sltu import *
+from .insn_sltu import *
-from insn_xor import *
+from .insn_xor import *
-from insn_srl import *
+from .insn_srl import *
-from insn_sra import *
+from .insn_sra import *
-from insn_or import *
+from .insn_or import *
-from insn_and import *
+from .insn_and import *
 
 """
 RV32I Base ISA