diff --git a/cores/minerva/.gitignore b/cores/minerva/.gitignore
deleted file mode 100644
index 1bbe5d0..0000000
--- a/cores/minerva/.gitignore
+++ /dev/null
@@ -1,14 +0,0 @@
-# Python
-__pycache__/
-/*.egg-info
-/.eggs
-
-# tests
-**/test/spec_*/
-*.vcd
-*.gtkw
-
-# misc user-created
-*.il
-*.v
-/build
diff --git a/cores/minerva/cli.py b/cores/minerva/cli.py
deleted file mode 100644
index 1d4ba49..0000000
--- a/cores/minerva/cli.py
+++ /dev/null
@@ -1,114 +0,0 @@
-import argparse
-import warnings
-from nmigen import cli
-
-from minerva.core import Minerva
-
-
-def main():
-    parser = argparse.ArgumentParser(formatter_class=argparse.ArgumentDefaultsHelpFormatter)
-
-    parser.add_argument("--reset-addr",
-            type=lambda s: int(s, 16), default="0x00000000",
-            help="reset vector address")
-
-    parser.add_argument("--with-icache",
-            default=False, action="store_true",
-            help="enable the instruction cache")
-    parser.add_argument("--with-dcache",
-            default=False, action="store_true",
-            help="enable the data cache")
-    parser.add_argument("--with-muldiv",
-            default=False, action="store_true",
-            help="enable RV32M support")
-    parser.add_argument("--with-debug",
-            default=False, action="store_true",
-            help="enable the Debug Module")
-    parser.add_argument("--with-trigger",
-            default=False, action="store_true",
-            help="enable the Trigger Module")
-    parser.add_argument("--with-rvfi",
-            default=False, action="store_true",
-            help="enable the riscv-formal interface")
-
-    icache_group = parser.add_argument_group("icache options")
-    icache_group.add_argument("--icache-nways",
-            type=int, choices=[1, 2], default=1,
-            help="number of ways")
-    icache_group.add_argument("--icache-nlines",
-            type=int, default=32,
-            help="number of lines")
-    icache_group.add_argument("--icache-nwords",
-            type=int, choices=[4, 8, 16], default=4,
-            help="number of words in a line")
-    icache_group.add_argument("--icache-base",
-            type=lambda s: int(s, 16), default="0x00000000",
-            help="base address")
-    icache_group.add_argument("--icache-limit",
-            type=lambda s: int(s, 16), default="0x80000000",
-            help="limit address")
-
-    dcache_group = parser.add_argument_group("dcache options")
-    dcache_group.add_argument("--dcache-nways",
-            type=int, choices=[1, 2], default=1,
-            help="number of ways")
-    dcache_group.add_argument("--dcache-nlines",
-            type=int, default=32,
-            help="number of lines")
-    dcache_group.add_argument("--dcache-nwords",
-            type=int, choices=[4, 8, 16], default=4,
-            help="number of words in a line")
-    dcache_group.add_argument("--dcache-base",
-            type=lambda s: int(s, 16), default="0x00000000",
-            help="base address")
-    dcache_group.add_argument("--dcache-limit",
-            type=lambda s: int(s, 16), default="0x80000000",
-            help="limit address")
-
-    trigger_group = parser.add_argument_group("trigger options")
-    trigger_group.add_argument("--nb-triggers",
-            type=int, default=8,
-            help="number of triggers")
-
-    cli.main_parser(parser)
-
-    args = parser.parse_args()
-
-    if args.with_debug and not args.with_trigger:
-        warnings.warn("Support for hardware breakpoints requires --with-trigger")
-
-    cpu = Minerva(args.reset_addr,
-            args.with_icache, args.icache_nways, args.icache_nlines, args.icache_nwords,
-            args.icache_base, args.icache_limit,
-            args.with_dcache, args.dcache_nways, args.dcache_nlines, args.dcache_nwords,
-            args.dcache_base, args.dcache_limit,
-            args.with_muldiv,
-            args.with_debug,
-            args.with_trigger, args.nb_triggers,
-            args.with_rvfi)
-
-    ports = [
-        cpu.external_interrupt, cpu.timer_interrupt, cpu.software_interrupt,
-        cpu.ibus.ack, cpu.ibus.adr, cpu.ibus.bte, cpu.ibus.cti, cpu.ibus.cyc, cpu.ibus.dat_r,
-        cpu.ibus.dat_w, cpu.ibus.sel, cpu.ibus.stb, cpu.ibus.we, cpu.ibus.err,
-        cpu.dbus.ack, cpu.dbus.adr, cpu.dbus.bte, cpu.dbus.cti, cpu.dbus.cyc, cpu.dbus.dat_r,
-        cpu.dbus.dat_w, cpu.dbus.sel, cpu.dbus.stb, cpu.dbus.we, cpu.dbus.err
-    ]
-
-    if args.with_debug:
-        ports += [cpu.jtag.tck, cpu.jtag.tdi, cpu.jtag.tdo, cpu.jtag.tms]
-
-    if args.with_rvfi:
-        ports += [
-            cpu.rvfi.valid, cpu.rvfi.order, cpu.rvfi.insn, cpu.rvfi.trap, cpu.rvfi.halt,
-            cpu.rvfi.intr, cpu.rvfi.mode, cpu.rvfi.ixl, cpu.rvfi.rs1_addr, cpu.rvfi.rs2_addr,
-            cpu.rvfi.rs1_rdata, cpu.rvfi.rs2_rdata, cpu.rvfi.rd_addr, cpu.rvfi.rd_wdata,
-            cpu.rvfi.pc_rdata, cpu.rvfi.pc_wdata, cpu.rvfi.mem_addr, cpu.rvfi.mem_rmask,
-            cpu.rvfi.mem_wmask, cpu.rvfi.mem_rdata, cpu.rvfi.mem_wdata
-        ]
-
-    cli.main_runner(parser, args, cpu, name="minerva_cpu", ports=ports)
-
-
-if __name__ == "__main__":
-    main()
diff --git a/cores/minerva/setup.py b/cores/minerva/setup.py
deleted file mode 100644
index 8162ead..0000000
--- a/cores/minerva/setup.py
+++ /dev/null
@@ -1,19 +0,0 @@
-from setuptools import setup, find_packages
-
-
-setup(
-    name="minerva",
-    version="0.1",
-    description="A 32-bit RISC-V soft processor",
-    author="Jean-François Nguyen",
-    author_email="jf@lambdaconcept.com",
-    license="BSD",
-    python_requires="~=3.6",
-    install_requires=["nmigen>=0.1rc1"],
-    extras_require={ "debug": ["jtagtap"] },
-    packages=find_packages(),
-    project_urls={
-        "Source Code": "https://github.com/lambdaconcept/minerva",
-        "Bug Tracker": "https://github.com/lambdaconcept/minerva/issues"
-    }
-)
diff --git a/cores/minerva/minerva/__init__.py b/rvfi/__init__.py
similarity index 100%
rename from cores/minerva/minerva/__init__.py
rename to rvfi/__init__.py
diff --git a/cores/minerva/minerva/test/__init__.py b/rvfi/cores/__init__.py
similarity index 100%
rename from cores/minerva/minerva/test/__init__.py
rename to rvfi/cores/__init__.py
diff --git a/cores/minerva/LICENSE.txt b/rvfi/cores/minerva/LICENSE.txt
similarity index 100%
rename from cores/minerva/LICENSE.txt
rename to rvfi/cores/minerva/LICENSE.txt
diff --git a/cores/minerva/README.md b/rvfi/cores/minerva/README.md
similarity index 100%
rename from cores/minerva/README.md
rename to rvfi/cores/minerva/README.md
diff --git a/cores/minerva/minerva/units/__init__.py b/rvfi/cores/minerva/__init__.py
similarity index 100%
rename from cores/minerva/minerva/units/__init__.py
rename to rvfi/cores/minerva/__init__.py
diff --git a/cores/minerva/minerva/cache.py b/rvfi/cores/minerva/cache.py
similarity index 100%
rename from cores/minerva/minerva/cache.py
rename to rvfi/cores/minerva/cache.py
diff --git a/cores/minerva/minerva/core.py b/rvfi/cores/minerva/core.py
similarity index 100%
rename from cores/minerva/minerva/core.py
rename to rvfi/cores/minerva/core.py
diff --git a/cores/minerva/minerva/csr.py b/rvfi/cores/minerva/csr.py
similarity index 100%
rename from cores/minerva/minerva/csr.py
rename to rvfi/cores/minerva/csr.py
diff --git a/cores/minerva/minerva/isa.py b/rvfi/cores/minerva/isa.py
similarity index 100%
rename from cores/minerva/minerva/isa.py
rename to rvfi/cores/minerva/isa.py
diff --git a/cores/minerva/minerva/stage.py b/rvfi/cores/minerva/stage.py
similarity index 100%
rename from cores/minerva/minerva/stage.py
rename to rvfi/cores/minerva/stage.py
diff --git a/rvfi/cores/minerva/test/__init__.py b/rvfi/cores/minerva/test/__init__.py
new file mode 100644
index 0000000..e69de29
diff --git a/cores/minerva/minerva/test/test_cache.py b/rvfi/cores/minerva/test/test_cache.py
similarity index 100%
rename from cores/minerva/minerva/test/test_cache.py
rename to rvfi/cores/minerva/test/test_cache.py
diff --git a/cores/minerva/minerva/test/test_units_divider.py b/rvfi/cores/minerva/test/test_units_divider.py
similarity index 100%
rename from cores/minerva/minerva/test/test_units_divider.py
rename to rvfi/cores/minerva/test/test_units_divider.py
diff --git a/cores/minerva/minerva/test/test_units_multiplier.py b/rvfi/cores/minerva/test/test_units_multiplier.py
similarity index 100%
rename from cores/minerva/minerva/test/test_units_multiplier.py
rename to rvfi/cores/minerva/test/test_units_multiplier.py
diff --git a/rvfi/cores/minerva/units/__init__.py b/rvfi/cores/minerva/units/__init__.py
new file mode 100644
index 0000000..e69de29
diff --git a/cores/minerva/minerva/units/adder.py b/rvfi/cores/minerva/units/adder.py
similarity index 100%
rename from cores/minerva/minerva/units/adder.py
rename to rvfi/cores/minerva/units/adder.py
diff --git a/cores/minerva/minerva/units/compare.py b/rvfi/cores/minerva/units/compare.py
similarity index 100%
rename from cores/minerva/minerva/units/compare.py
rename to rvfi/cores/minerva/units/compare.py
diff --git a/cores/minerva/minerva/units/debug/__init__.py b/rvfi/cores/minerva/units/debug/__init__.py
similarity index 100%
rename from cores/minerva/minerva/units/debug/__init__.py
rename to rvfi/cores/minerva/units/debug/__init__.py
diff --git a/cores/minerva/minerva/units/debug/controller.py b/rvfi/cores/minerva/units/debug/controller.py
similarity index 100%
rename from cores/minerva/minerva/units/debug/controller.py
rename to rvfi/cores/minerva/units/debug/controller.py
diff --git a/cores/minerva/minerva/units/debug/dmi.py b/rvfi/cores/minerva/units/debug/dmi.py
similarity index 100%
rename from cores/minerva/minerva/units/debug/dmi.py
rename to rvfi/cores/minerva/units/debug/dmi.py
diff --git a/cores/minerva/minerva/units/debug/jtag.py b/rvfi/cores/minerva/units/debug/jtag.py
similarity index 100%
rename from cores/minerva/minerva/units/debug/jtag.py
rename to rvfi/cores/minerva/units/debug/jtag.py
diff --git a/cores/minerva/minerva/units/debug/regfile.py b/rvfi/cores/minerva/units/debug/regfile.py
similarity index 100%
rename from cores/minerva/minerva/units/debug/regfile.py
rename to rvfi/cores/minerva/units/debug/regfile.py
diff --git a/cores/minerva/minerva/units/debug/top.py b/rvfi/cores/minerva/units/debug/top.py
similarity index 100%
rename from cores/minerva/minerva/units/debug/top.py
rename to rvfi/cores/minerva/units/debug/top.py
diff --git a/cores/minerva/minerva/units/debug/wbmaster.py b/rvfi/cores/minerva/units/debug/wbmaster.py
similarity index 100%
rename from cores/minerva/minerva/units/debug/wbmaster.py
rename to rvfi/cores/minerva/units/debug/wbmaster.py
diff --git a/cores/minerva/minerva/units/decoder.py b/rvfi/cores/minerva/units/decoder.py
similarity index 100%
rename from cores/minerva/minerva/units/decoder.py
rename to rvfi/cores/minerva/units/decoder.py
diff --git a/cores/minerva/minerva/units/divider.py b/rvfi/cores/minerva/units/divider.py
similarity index 100%
rename from cores/minerva/minerva/units/divider.py
rename to rvfi/cores/minerva/units/divider.py
diff --git a/cores/minerva/minerva/units/exception.py b/rvfi/cores/minerva/units/exception.py
similarity index 100%
rename from cores/minerva/minerva/units/exception.py
rename to rvfi/cores/minerva/units/exception.py
diff --git a/cores/minerva/minerva/units/fetch.py b/rvfi/cores/minerva/units/fetch.py
similarity index 100%
rename from cores/minerva/minerva/units/fetch.py
rename to rvfi/cores/minerva/units/fetch.py
diff --git a/cores/minerva/minerva/units/loadstore.py b/rvfi/cores/minerva/units/loadstore.py
similarity index 100%
rename from cores/minerva/minerva/units/loadstore.py
rename to rvfi/cores/minerva/units/loadstore.py
diff --git a/cores/minerva/minerva/units/logic.py b/rvfi/cores/minerva/units/logic.py
similarity index 100%
rename from cores/minerva/minerva/units/logic.py
rename to rvfi/cores/minerva/units/logic.py
diff --git a/cores/minerva/minerva/units/multiplier.py b/rvfi/cores/minerva/units/multiplier.py
similarity index 100%
rename from cores/minerva/minerva/units/multiplier.py
rename to rvfi/cores/minerva/units/multiplier.py
diff --git a/cores/minerva/minerva/units/predict.py b/rvfi/cores/minerva/units/predict.py
similarity index 100%
rename from cores/minerva/minerva/units/predict.py
rename to rvfi/cores/minerva/units/predict.py
diff --git a/cores/minerva/minerva/units/rvficon.py b/rvfi/cores/minerva/units/rvficon.py
similarity index 100%
rename from cores/minerva/minerva/units/rvficon.py
rename to rvfi/cores/minerva/units/rvficon.py
diff --git a/cores/minerva/minerva/units/shifter.py b/rvfi/cores/minerva/units/shifter.py
similarity index 100%
rename from cores/minerva/minerva/units/shifter.py
rename to rvfi/cores/minerva/units/shifter.py
diff --git a/cores/minerva/minerva/units/trigger.py b/rvfi/cores/minerva/units/trigger.py
similarity index 100%
rename from cores/minerva/minerva/units/trigger.py
rename to rvfi/cores/minerva/units/trigger.py
diff --git a/cores/minerva/minerva/wishbone.py b/rvfi/cores/minerva/wishbone.py
similarity index 100%
rename from cores/minerva/minerva/wishbone.py
rename to rvfi/cores/minerva/wishbone.py
diff --git a/insns/README.md b/rvfi/insns/README.md
similarity index 100%
rename from insns/README.md
rename to rvfi/insns/README.md
diff --git a/rvfi/insns/__init__.py b/rvfi/insns/__init__.py
new file mode 100644
index 0000000..e69de29
diff --git a/insns/insn.py b/rvfi/insns/insn.py
similarity index 100%
rename from insns/insn.py
rename to rvfi/insns/insn.py
diff --git a/insns/insn_add.py b/rvfi/insns/insn_add.py
similarity index 93%
rename from insns/insn_add.py
rename to rvfi/insns/insn_add.py
index 54128cb..2cd7f6d 100644
--- a/insns/insn_add.py
+++ b/rvfi/insns/insn_add.py
@@ -1,4 +1,4 @@
-from insn_rv32i_r_type import *
+from .insn_rv32i_r_type import *
 
 """
 ADD instruction
diff --git a/insns/insn_addi.py b/rvfi/insns/insn_addi.py
similarity index 91%
rename from insns/insn_addi.py
rename to rvfi/insns/insn_addi.py
index 9aa5c64..535990b 100644
--- a/insns/insn_addi.py
+++ b/rvfi/insns/insn_addi.py
@@ -1,4 +1,4 @@
-from insn_rv32i_i_type_arith import *
+from .insn_rv32i_i_type_arith import *
 
 """
 ADDI instruction
diff --git a/insns/insn_and.py b/rvfi/insns/insn_and.py
similarity index 93%
rename from insns/insn_and.py
rename to rvfi/insns/insn_and.py
index bb1f822..c82005c 100644
--- a/insns/insn_and.py
+++ b/rvfi/insns/insn_and.py
@@ -1,4 +1,4 @@
-from insn_rv32i_r_type import *
+from .insn_rv32i_r_type import *
 
 """
 AND instruction
diff --git a/insns/insn_andi.py b/rvfi/insns/insn_andi.py
similarity index 91%
rename from insns/insn_andi.py
rename to rvfi/insns/insn_andi.py
index 94d74b2..17f3660 100644
--- a/insns/insn_andi.py
+++ b/rvfi/insns/insn_andi.py
@@ -1,4 +1,4 @@
-from insn_rv32i_i_type_arith import *
+from .insn_rv32i_i_type_arith import *
 
 """
 ANDI instruction
diff --git a/insns/insn_auipc.py b/rvfi/insns/insn_auipc.py
similarity index 93%
rename from insns/insn_auipc.py
rename to rvfi/insns/insn_auipc.py
index d049422..10c35c4 100644
--- a/insns/insn_auipc.py
+++ b/rvfi/insns/insn_auipc.py
@@ -1,4 +1,4 @@
-from insn_rv32i_u_type import *
+from .insn_rv32i_u_type import *
 
 """
 AUIPC instruction
diff --git a/insns/insn_beq.py b/rvfi/insns/insn_beq.py
similarity index 95%
rename from insns/insn_beq.py
rename to rvfi/insns/insn_beq.py
index 918454f..a3509ad 100644
--- a/insns/insn_beq.py
+++ b/rvfi/insns/insn_beq.py
@@ -1,4 +1,4 @@
-from insn_rv32i_sb_type import *
+from .insn_rv32i_sb_type import *
 
 """
 BEQ instruction
diff --git a/insns/insn_bge.py b/rvfi/insns/insn_bge.py
similarity index 95%
rename from insns/insn_bge.py
rename to rvfi/insns/insn_bge.py
index d91e300..94ae31d 100644
--- a/insns/insn_bge.py
+++ b/rvfi/insns/insn_bge.py
@@ -1,4 +1,4 @@
-from insn_rv32i_sb_type import *
+from .insn_rv32i_sb_type import *
 
 """
 BGE instruction
diff --git a/insns/insn_bgeu.py b/rvfi/insns/insn_bgeu.py
similarity index 95%
rename from insns/insn_bgeu.py
rename to rvfi/insns/insn_bgeu.py
index 27c3e7f..aa91a07 100644
--- a/insns/insn_bgeu.py
+++ b/rvfi/insns/insn_bgeu.py
@@ -1,4 +1,4 @@
-from insn_rv32i_sb_type import *
+from .insn_rv32i_sb_type import *
 
 """
 BGEU instruction
diff --git a/insns/insn_blt.py b/rvfi/insns/insn_blt.py
similarity index 95%
rename from insns/insn_blt.py
rename to rvfi/insns/insn_blt.py
index ba3ad17..fbb9076 100644
--- a/insns/insn_blt.py
+++ b/rvfi/insns/insn_blt.py
@@ -1,4 +1,4 @@
-from insn_rv32i_sb_type import *
+from .insn_rv32i_sb_type import *
 
 """
 BLT instruction
diff --git a/insns/insn_bltu.py b/rvfi/insns/insn_bltu.py
similarity index 95%
rename from insns/insn_bltu.py
rename to rvfi/insns/insn_bltu.py
index 5817b60..9b456a8 100644
--- a/insns/insn_bltu.py
+++ b/rvfi/insns/insn_bltu.py
@@ -1,4 +1,4 @@
-from insn_rv32i_sb_type import *
+from .insn_rv32i_sb_type import *
 
 """
 BLTU instruction
diff --git a/insns/insn_bne.py b/rvfi/insns/insn_bne.py
similarity index 95%
rename from insns/insn_bne.py
rename to rvfi/insns/insn_bne.py
index 926acbc..f28df31 100644
--- a/insns/insn_bne.py
+++ b/rvfi/insns/insn_bne.py
@@ -1,4 +1,4 @@
-from insn_rv32i_sb_type import *
+from .insn_rv32i_sb_type import *
 
 """
 BNE instruction
diff --git a/insns/insn_jal.py b/rvfi/insns/insn_jal.py
similarity index 98%
rename from insns/insn_jal.py
rename to rvfi/insns/insn_jal.py
index 82b1892..0fbfeb5 100644
--- a/insns/insn_jal.py
+++ b/rvfi/insns/insn_jal.py
@@ -1,4 +1,4 @@
-from insn import *
+from .insn import *
 
 """
 JAL instruction
diff --git a/insns/insn_jalr.py b/rvfi/insns/insn_jalr.py
similarity index 97%
rename from insns/insn_jalr.py
rename to rvfi/insns/insn_jalr.py
index 34aeeda..0ef1cb5 100644
--- a/insns/insn_jalr.py
+++ b/rvfi/insns/insn_jalr.py
@@ -1,4 +1,4 @@
-from insn_rv32i_i_type import *
+from .insn_rv32i_i_type import *
 
 """
 JALR instruction
diff --git a/insns/insn_lb.py b/rvfi/insns/insn_lb.py
similarity index 88%
rename from insns/insn_lb.py
rename to rvfi/insns/insn_lb.py
index d0ae726..6365204 100644
--- a/insns/insn_lb.py
+++ b/rvfi/insns/insn_lb.py
@@ -1,4 +1,4 @@
-from insn_rv32i_i_type_load import *
+from .insn_rv32i_i_type_load import *
 
 """
 LB instruction
diff --git a/insns/insn_lbu.py b/rvfi/insns/insn_lbu.py
similarity index 88%
rename from insns/insn_lbu.py
rename to rvfi/insns/insn_lbu.py
index c0f4520..bf96511 100644
--- a/insns/insn_lbu.py
+++ b/rvfi/insns/insn_lbu.py
@@ -1,4 +1,4 @@
-from insn_rv32i_i_type_load import *
+from .insn_rv32i_i_type_load import *
 
 """
 LBU instruction
diff --git a/insns/insn_lh.py b/rvfi/insns/insn_lh.py
similarity index 88%
rename from insns/insn_lh.py
rename to rvfi/insns/insn_lh.py
index b9dc25c..bf09497 100644
--- a/insns/insn_lh.py
+++ b/rvfi/insns/insn_lh.py
@@ -1,4 +1,4 @@
-from insn_rv32i_i_type_load import *
+from .insn_rv32i_i_type_load import *
 
 """
 LH instruction
diff --git a/insns/insn_lhu.py b/rvfi/insns/insn_lhu.py
similarity index 88%
rename from insns/insn_lhu.py
rename to rvfi/insns/insn_lhu.py
index d6d4738..5e5ca4b 100644
--- a/insns/insn_lhu.py
+++ b/rvfi/insns/insn_lhu.py
@@ -1,4 +1,4 @@
-from insn_rv32i_i_type_load import *
+from .insn_rv32i_i_type_load import *
 
 """
 LHU instruction
diff --git a/insns/insn_lui.py b/rvfi/insns/insn_lui.py
similarity index 92%
rename from insns/insn_lui.py
rename to rvfi/insns/insn_lui.py
index 9ba4833..867f612 100644
--- a/insns/insn_lui.py
+++ b/rvfi/insns/insn_lui.py
@@ -1,4 +1,4 @@
-from insn_rv32i_u_type import *
+from .insn_rv32i_u_type import *
 
 """
 LUI instruction
diff --git a/insns/insn_lw.py b/rvfi/insns/insn_lw.py
similarity index 88%
rename from insns/insn_lw.py
rename to rvfi/insns/insn_lw.py
index 7609a87..a9a6117 100644
--- a/insns/insn_lw.py
+++ b/rvfi/insns/insn_lw.py
@@ -1,4 +1,4 @@
-from insn_rv32i_i_type_load import *
+from .insn_rv32i_i_type_load import *
 
 """
 LW instruction
diff --git a/insns/insn_or.py b/rvfi/insns/insn_or.py
similarity index 93%
rename from insns/insn_or.py
rename to rvfi/insns/insn_or.py
index ae5e7a4..b6d090d 100644
--- a/insns/insn_or.py
+++ b/rvfi/insns/insn_or.py
@@ -1,4 +1,4 @@
-from insn_rv32i_r_type import *
+from .insn_rv32i_r_type import *
 
 """
 OR instruction
diff --git a/insns/insn_ori.py b/rvfi/insns/insn_ori.py
similarity index 91%
rename from insns/insn_ori.py
rename to rvfi/insns/insn_ori.py
index edbc7fe..9c8be85 100644
--- a/insns/insn_ori.py
+++ b/rvfi/insns/insn_ori.py
@@ -1,4 +1,4 @@
-from insn_rv32i_i_type_arith import *
+from .insn_rv32i_i_type_arith import *
 
 """
 ORI instruction
diff --git a/insns/insn_rv32i_i_type.py b/rvfi/insns/insn_rv32i_i_type.py
similarity index 92%
rename from insns/insn_rv32i_i_type.py
rename to rvfi/insns/insn_rv32i_i_type.py
index 05e7142..a2c4c54 100644
--- a/insns/insn_rv32i_i_type.py
+++ b/rvfi/insns/insn_rv32i_i_type.py
@@ -1,4 +1,4 @@
-from insn import *
+from .insn import *
 
 """
 RV32I I-Type Instruction
diff --git a/insns/insn_rv32i_i_type_arith.py b/rvfi/insns/insn_rv32i_i_type_arith.py
similarity index 96%
rename from insns/insn_rv32i_i_type_arith.py
rename to rvfi/insns/insn_rv32i_i_type_arith.py
index 9862e9d..4dbc828 100644
--- a/insns/insn_rv32i_i_type_arith.py
+++ b/rvfi/insns/insn_rv32i_i_type_arith.py
@@ -1,4 +1,4 @@
-from insn_rv32i_i_type import *
+from .insn_rv32i_i_type import *
 
 """
 RV32I I-Type Instruction (Arithmetic Variation)
diff --git a/insns/insn_rv32i_i_type_load.py b/rvfi/insns/insn_rv32i_i_type_load.py
similarity index 98%
rename from insns/insn_rv32i_i_type_load.py
rename to rvfi/insns/insn_rv32i_i_type_load.py
index bdef487..46524da 100644
--- a/insns/insn_rv32i_i_type_load.py
+++ b/rvfi/insns/insn_rv32i_i_type_load.py
@@ -1,4 +1,4 @@
-from insn_rv32i_i_type import *
+from .insn_rv32i_i_type import *
 
 """
 RV32I I-Type Instruction (Load Variation)
diff --git a/insns/insn_rv32i_i_type_shift.py b/rvfi/insns/insn_rv32i_i_type_shift.py
similarity index 98%
rename from insns/insn_rv32i_i_type_shift.py
rename to rvfi/insns/insn_rv32i_i_type_shift.py
index 5292d9f..ce290b6 100644
--- a/insns/insn_rv32i_i_type_shift.py
+++ b/rvfi/insns/insn_rv32i_i_type_shift.py
@@ -1,4 +1,4 @@
-from insn import *
+from .insn import *
 
 """
 RV32I I-Type Instruction (Shift Variation)
diff --git a/insns/insn_rv32i_r_type.py b/rvfi/insns/insn_rv32i_r_type.py
similarity index 98%
rename from insns/insn_rv32i_r_type.py
rename to rvfi/insns/insn_rv32i_r_type.py
index d61ccf9..e1964de 100644
--- a/insns/insn_rv32i_r_type.py
+++ b/rvfi/insns/insn_rv32i_r_type.py
@@ -1,4 +1,4 @@
-from insn import *
+from .insn import *
 
 """
 RV32I R-Type Instruction
diff --git a/insns/insn_rv32i_s_type.py b/rvfi/insns/insn_rv32i_s_type.py
similarity index 99%
rename from insns/insn_rv32i_s_type.py
rename to rvfi/insns/insn_rv32i_s_type.py
index 1945d1d..8025ce6 100644
--- a/insns/insn_rv32i_s_type.py
+++ b/rvfi/insns/insn_rv32i_s_type.py
@@ -1,4 +1,4 @@
-from insn import *
+from .insn import *
 
 """
 RV32I S-Type Instruction
diff --git a/insns/insn_rv32i_sb_type.py b/rvfi/insns/insn_rv32i_sb_type.py
similarity index 98%
rename from insns/insn_rv32i_sb_type.py
rename to rvfi/insns/insn_rv32i_sb_type.py
index a557c6e..fb11030 100644
--- a/insns/insn_rv32i_sb_type.py
+++ b/rvfi/insns/insn_rv32i_sb_type.py
@@ -1,4 +1,4 @@
-from insn import *
+from .insn import *
 
 """
 RV32I SB-Type Instruction
diff --git a/insns/insn_rv32i_u_type.py b/rvfi/insns/insn_rv32i_u_type.py
similarity index 97%
rename from insns/insn_rv32i_u_type.py
rename to rvfi/insns/insn_rv32i_u_type.py
index d9bb1a0..b755b7c 100644
--- a/insns/insn_rv32i_u_type.py
+++ b/rvfi/insns/insn_rv32i_u_type.py
@@ -1,4 +1,4 @@
-from insn import *
+from .insn import *
 
 """
 RV32I U-Type Instruction
diff --git a/insns/insn_sb.py b/rvfi/insns/insn_sb.py
similarity index 89%
rename from insns/insn_sb.py
rename to rvfi/insns/insn_sb.py
index 8ff936a..7eb9f4f 100644
--- a/insns/insn_sb.py
+++ b/rvfi/insns/insn_sb.py
@@ -1,4 +1,4 @@
-from insn_rv32i_s_type import *
+from .insn_rv32i_s_type import *
 
 """
 SB instruction
diff --git a/insns/insn_sh.py b/rvfi/insns/insn_sh.py
similarity index 89%
rename from insns/insn_sh.py
rename to rvfi/insns/insn_sh.py
index 626a3eb..70cc5b2 100644
--- a/insns/insn_sh.py
+++ b/rvfi/insns/insn_sh.py
@@ -1,4 +1,4 @@
-from insn_rv32i_s_type import *
+from .insn_rv32i_s_type import *
 
 """
 SH instruction
diff --git a/insns/insn_sll.py b/rvfi/insns/insn_sll.py
similarity index 94%
rename from insns/insn_sll.py
rename to rvfi/insns/insn_sll.py
index fe2c297..9832563 100644
--- a/insns/insn_sll.py
+++ b/rvfi/insns/insn_sll.py
@@ -1,4 +1,4 @@
-from insn_rv32i_r_type import *
+from .insn_rv32i_r_type import *
 
 """
 SLL instruction
diff --git a/insns/insn_slli.py b/rvfi/insns/insn_slli.py
similarity index 92%
rename from insns/insn_slli.py
rename to rvfi/insns/insn_slli.py
index f8a3da7..8d7cf88 100644
--- a/insns/insn_slli.py
+++ b/rvfi/insns/insn_slli.py
@@ -1,4 +1,4 @@
-from insn_rv32i_i_type_shift import *
+from .insn_rv32i_i_type_shift import *
 
 """
 SLLI instruction
diff --git a/insns/insn_slt.py b/rvfi/insns/insn_slt.py
similarity index 93%
rename from insns/insn_slt.py
rename to rvfi/insns/insn_slt.py
index a07f0ae..8af854d 100644
--- a/insns/insn_slt.py
+++ b/rvfi/insns/insn_slt.py
@@ -1,4 +1,4 @@
-from insn_rv32i_r_type import *
+from .insn_rv32i_r_type import *
 
 """
 SLT instruction
diff --git a/insns/insn_slti.py b/rvfi/insns/insn_slti.py
similarity index 92%
rename from insns/insn_slti.py
rename to rvfi/insns/insn_slti.py
index 23dc19d..7a4d364 100644
--- a/insns/insn_slti.py
+++ b/rvfi/insns/insn_slti.py
@@ -1,4 +1,4 @@
-from insn_rv32i_i_type_arith import *
+from .insn_rv32i_i_type_arith import *
 
 """
 SLTI instruction
diff --git a/insns/insn_sltiu.py b/rvfi/insns/insn_sltiu.py
similarity index 91%
rename from insns/insn_sltiu.py
rename to rvfi/insns/insn_sltiu.py
index 9cb2136..638b6ae 100644
--- a/insns/insn_sltiu.py
+++ b/rvfi/insns/insn_sltiu.py
@@ -1,4 +1,4 @@
-from insn_rv32i_i_type_arith import *
+from .insn_rv32i_i_type_arith import *
 
 """
 SLTIU instruction
diff --git a/insns/insn_sltu.py b/rvfi/insns/insn_sltu.py
similarity index 93%
rename from insns/insn_sltu.py
rename to rvfi/insns/insn_sltu.py
index 2669fea..237873c 100644
--- a/insns/insn_sltu.py
+++ b/rvfi/insns/insn_sltu.py
@@ -1,4 +1,4 @@
-from insn_rv32i_r_type import *
+from .insn_rv32i_r_type import *
 
 """
 SLTU instruction
diff --git a/insns/insn_sra.py b/rvfi/insns/insn_sra.py
similarity index 95%
rename from insns/insn_sra.py
rename to rvfi/insns/insn_sra.py
index 804089a..56bf8cb 100644
--- a/insns/insn_sra.py
+++ b/rvfi/insns/insn_sra.py
@@ -1,4 +1,4 @@
-from insn_rv32i_r_type import *
+from .insn_rv32i_r_type import *
 
 """
 SRA instruction
diff --git a/insns/insn_srai.py b/rvfi/insns/insn_srai.py
similarity index 93%
rename from insns/insn_srai.py
rename to rvfi/insns/insn_srai.py
index 1c99816..c7b0d27 100644
--- a/insns/insn_srai.py
+++ b/rvfi/insns/insn_srai.py
@@ -1,4 +1,4 @@
-from insn_rv32i_i_type_shift import *
+from .insn_rv32i_i_type_shift import *
 
 """
 SRAI instruction
diff --git a/insns/insn_srl.py b/rvfi/insns/insn_srl.py
similarity index 94%
rename from insns/insn_srl.py
rename to rvfi/insns/insn_srl.py
index 1403af9..6bc4d1d 100644
--- a/insns/insn_srl.py
+++ b/rvfi/insns/insn_srl.py
@@ -1,4 +1,4 @@
-from insn_rv32i_r_type import *
+from .insn_rv32i_r_type import *
 
 """
 SRL instruction
diff --git a/insns/insn_srli.py b/rvfi/insns/insn_srli.py
similarity index 92%
rename from insns/insn_srli.py
rename to rvfi/insns/insn_srli.py
index 6eeb7ae..93bb136 100644
--- a/insns/insn_srli.py
+++ b/rvfi/insns/insn_srli.py
@@ -1,4 +1,4 @@
-from insn_rv32i_i_type_shift import *
+from .insn_rv32i_i_type_shift import *
 
 """
 SRLI instruction
diff --git a/insns/insn_sub.py b/rvfi/insns/insn_sub.py
similarity index 93%
rename from insns/insn_sub.py
rename to rvfi/insns/insn_sub.py
index 9a45e1d..5387b20 100644
--- a/insns/insn_sub.py
+++ b/rvfi/insns/insn_sub.py
@@ -1,4 +1,4 @@
-from insn_rv32i_r_type import *
+from .insn_rv32i_r_type import *
 
 """
 SUB instruction
diff --git a/insns/insn_sw.py b/rvfi/insns/insn_sw.py
similarity index 89%
rename from insns/insn_sw.py
rename to rvfi/insns/insn_sw.py
index aa566ce..855f3db 100644
--- a/insns/insn_sw.py
+++ b/rvfi/insns/insn_sw.py
@@ -1,4 +1,4 @@
-from insn_rv32i_s_type import *
+from .insn_rv32i_s_type import *
 
 """
 SW instruction
diff --git a/insns/insn_xor.py b/rvfi/insns/insn_xor.py
similarity index 93%
rename from insns/insn_xor.py
rename to rvfi/insns/insn_xor.py
index 7624731..dd5135f 100644
--- a/insns/insn_xor.py
+++ b/rvfi/insns/insn_xor.py
@@ -1,4 +1,4 @@
-from insn_rv32i_r_type import *
+from .insn_rv32i_r_type import *
 
 """
 XOR instruction
diff --git a/insns/insn_xori.py b/rvfi/insns/insn_xori.py
similarity index 91%
rename from insns/insn_xori.py
rename to rvfi/insns/insn_xori.py
index 92ed9bf..03235c7 100644
--- a/insns/insn_xori.py
+++ b/rvfi/insns/insn_xori.py
@@ -1,4 +1,4 @@
-from insn_rv32i_i_type_arith import *
+from .insn_rv32i_i_type_arith import *
 
 """
 XORI instruction
diff --git a/insns/isa_rv32i.py b/rvfi/insns/isa_rv32i.py
similarity index 92%
rename from insns/isa_rv32i.py
rename to rvfi/insns/isa_rv32i.py
index 5a4dca1..8b317ea 100644
--- a/insns/isa_rv32i.py
+++ b/rvfi/insns/isa_rv32i.py
@@ -1,40 +1,40 @@
-from insn_lui import *
-from insn_auipc import *
-from insn_jal import *
-from insn_jalr import *
-from insn_beq import *
-from insn_bne import *
-from insn_blt import *
-from insn_bge import *
-from insn_bltu import *
-from insn_bgeu import *
-from insn_lb import *
-from insn_lh import *
-from insn_lw import *
-from insn_lbu import *
-from insn_lhu import *
-from insn_sb import *
-from insn_sh import *
-from insn_sw import *
-from insn_addi import *
-from insn_slti import *
-from insn_sltiu import *
-from insn_xori import *
-from insn_ori import *
-from insn_andi import *
-from insn_slli import *
-from insn_srli import *
-from insn_srai import *
-from insn_add import *
-from insn_sub import *
-from insn_sll import *
-from insn_slt import *
-from insn_sltu import *
-from insn_xor import *
-from insn_srl import *
-from insn_sra import *
-from insn_or import *
-from insn_and import *
+from .insn_lui import *
+from .insn_auipc import *
+from .insn_jal import *
+from .insn_jalr import *
+from .insn_beq import *
+from .insn_bne import *
+from .insn_blt import *
+from .insn_bge import *
+from .insn_bltu import *
+from .insn_bgeu import *
+from .insn_lb import *
+from .insn_lh import *
+from .insn_lw import *
+from .insn_lbu import *
+from .insn_lhu import *
+from .insn_sb import *
+from .insn_sh import *
+from .insn_sw import *
+from .insn_addi import *
+from .insn_slti import *
+from .insn_sltiu import *
+from .insn_xori import *
+from .insn_ori import *
+from .insn_andi import *
+from .insn_slli import *
+from .insn_srli import *
+from .insn_srai import *
+from .insn_add import *
+from .insn_sub import *
+from .insn_sll import *
+from .insn_slt import *
+from .insn_sltu import *
+from .insn_xor import *
+from .insn_srl import *
+from .insn_sra import *
+from .insn_or import *
+from .insn_and import *
 
 """
 RV32I Base ISA