Add RV64I R-Type Instruction
This commit is contained in:
parent
cf295596ef
commit
6e4ecdcee0
|
@ -0,0 +1,27 @@
|
|||
from .insn import *
|
||||
|
||||
"""
|
||||
RV64I R-Type Instruction
|
||||
"""
|
||||
|
||||
class InsnRV64IRType(Insn):
|
||||
def __init__(self, params, funct7, funct3):
|
||||
super().__init__(params)
|
||||
self.funct7 = funct7
|
||||
self.funct3 = funct3
|
||||
def elaborate(self, platform):
|
||||
m = super().elaborate(platform)
|
||||
|
||||
if self.params.csr_misa:
|
||||
m.d.comb += self.misa_ok.eq((self.rvfi_Csr_misa_rdata & 0) == 0)
|
||||
m.d.comb += self.spec_csr_misa_rmask.eq(0)
|
||||
else:
|
||||
m.d.comb += self.misa_ok.eq(1)
|
||||
|
||||
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == self.funct7) & (self.insn_funct3 == self.funct3) & (self.insn_opcode == 0b0111011))
|
||||
m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
|
||||
m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
|
||||
m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
|
||||
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
|
||||
|
||||
return m
|
Loading…
Reference in New Issue