From 6e4ecdcee0e36cefb6d6b7b90a96c81b5403f830 Mon Sep 17 00:00:00 2001
From: Donald Sebastian Leung <dl@m-labs.hk>
Date: Thu, 27 Aug 2020 15:39:09 +0800
Subject: [PATCH] Add RV64I R-Type Instruction

---
 rvfi/insns/insn_rv64i_r_type.py | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)
 create mode 100644 rvfi/insns/insn_rv64i_r_type.py

diff --git a/rvfi/insns/insn_rv64i_r_type.py b/rvfi/insns/insn_rv64i_r_type.py
new file mode 100644
index 0000000..5a596b6
--- /dev/null
+++ b/rvfi/insns/insn_rv64i_r_type.py
@@ -0,0 +1,27 @@
+from .insn import *
+
+"""
+RV64I R-Type Instruction
+"""
+
+class InsnRV64IRType(Insn):
+    def __init__(self, params, funct7, funct3):
+        super().__init__(params)
+        self.funct7 = funct7
+        self.funct3 = funct3
+    def elaborate(self, platform):
+        m = super().elaborate(platform)
+
+        if self.params.csr_misa:
+            m.d.comb += self.misa_ok.eq((self.rvfi_Csr_misa_rdata & 0) == 0)
+            m.d.comb += self.spec_csr_misa_rmask.eq(0)
+        else:
+            m.d.comb += self.misa_ok.eq(1)
+
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == self.funct7) & (self.insn_funct3 == self.funct3) & (self.insn_opcode == 0b0111011))
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
+        m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
+        m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
+        m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
+
+        return m