From 64964655ff40a37d3a3ac303cd0f620ee06c44b0 Mon Sep 17 00:00:00 2001
From: Donald Sebastian Leung <dl@m-labs.hk>
Date: Fri, 28 Aug 2020 12:01:00 +0800
Subject: [PATCH] Add REMW instruction

---
 rvfi/insns/insn_remw.py | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)
 create mode 100644 rvfi/insns/insn_remw.py

diff --git a/rvfi/insns/insn_remw.py b/rvfi/insns/insn_remw.py
new file mode 100644
index 0000000..1d14aae
--- /dev/null
+++ b/rvfi/insns/insn_remw.py
@@ -0,0 +1,20 @@
+from .insn_rv64m_r_type import *
+
+"""
+REMW instruction
+"""
+
+class InsnRemw(InsnRV64MRType):
+    def __init__(self, params):
+        super.__init__(params, 0b110)
+    def elaborate(self, platform):
+        m = super().elaborate(platform)
+
+        result = Signal(32)
+        if self.params.altops:
+            m.d.comb += result.eq((self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ 0xf5b7d8538da68fa5)
+        else:
+            m.d.comb += result.eq(Mux(self.rvfi_rs2_rdata == 0, self.rvfi_rs1_rdata, Mux((self.rvfi_rs1_rdata == (1 << 31)) & (self.rvfi_rs2_rdata == 2 ** 32 - 1), 0, Value.as_signed(self.rvfi_rs1_rdata[:32]) % Value.as_signed(self.rvfi_rs2_rdata[:32]))))
+        m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, (Mux(result[31], 2 ** (self.params.xlen - 32) - 1, 0) << 32) | result, 0))
+
+        return m