diff --git a/insns/InsnBeq.py b/insns/InsnBeq.py
new file mode 100644
index 0000000..cb1f2bd
--- /dev/null
+++ b/insns/InsnBeq.py
@@ -0,0 +1,18 @@
+from InsnRV32ISBType import *
+
+"""
+BEQ instruction
+"""
+
+class InsnBeq(InsnRV32ISBType):
+    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED):
+        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b000)
+    def elaborate(self, platform):
+        m = super().elaborate(platform)
+
+        next_pc = Signal(self.RISCV_FORMAL_XLEN)
+        m.d.comb += next_pc.eq(Mux(self.rvfi_rs1_rdata == self.rvfi_rs2_rdata, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4))
+        m.d.comb += self.spec_pc_wdata.eq(next_pc)
+        m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok)
+
+        return m