From 504d6e1984cb1c08bccef5a471903899084ade35 Mon Sep 17 00:00:00 2001
From: Donald Sebastian Leung <dl@m-labs.hk>
Date: Tue, 11 Aug 2020 16:55:58 +0800
Subject: [PATCH] Add BLTU instruction

---
 insns/InsnBltu.py | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)
 create mode 100644 insns/InsnBltu.py

diff --git a/insns/InsnBltu.py b/insns/InsnBltu.py
new file mode 100644
index 0000000..fb39c75
--- /dev/null
+++ b/insns/InsnBltu.py
@@ -0,0 +1,18 @@
+from InsnRV32ISBType import *
+
+"""
+BLTU instruction
+"""
+
+class InsnBltu(InsnRV32ISBType):
+    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED):
+        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b110)
+    def elaborate(self, platform):
+        m = super().elaborate(platform)
+
+        next_pc = Signal(self.RISCV_FORMAL_XLEN)
+        m.d.comb += next_pc.eq(Mux(self.rvfi_rs1_rdata < self.rvfi_rs2_rdata, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4))
+        m.d.comb += self.spec_pc_wdata.eq(next_pc)
+        m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok)
+
+        return m