diff --git a/insns/InsnSrl.py b/insns/InsnSrl.py
new file mode 100644
index 0000000..51c1b06
--- /dev/null
+++ b/insns/InsnSrl.py
@@ -0,0 +1,11 @@
+from InsnRV32IRType import *
+
+class InsnSrl(InsnRV32IRType):
+    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED):
+        super(InsnSrl, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b100, 0b0110011)
+    def elaborate(self, platform):
+        m = super(InsnSrl, self).elaborate(platform)
+
+        m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata >> Mux(self.RISCV_FORMAL_XLEN == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5]), 0))
+
+        return m