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riscv-formal-nmigen
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Parallelize all verification tasks for Minerva

This commit is contained in:
Donald Sebastian Leung 2020-09-18 15:59:59 +08:00
parent b0a914b48e
commit 425bc49784
2 changed files with 40 additions and 21 deletions
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2
README.md
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@ -27,8 +27,6 @@ This should run the tests (cache, multiplier, divider) provided by Minerva itsel
$ python -m rvfi.cores.minerva.verify
```
This should complete within 2 hours.
## Scope
The RV32I, RV32M, RV64I and RV64M ISAs are currently implemented but only RV32IM are being tested by integrating with the Minerva core.

59
rvfi/cores/minerva/verify.py
View File

@ -230,8 +230,9 @@ class PcFwdSpec(Elaboratable):
class PcFwdTestCase(FHDLTestCase):
def verify(self):
self.assertFormal(PcFwdSpec(), mode="cover", depth=20)
self.assertFormal(PcFwdSpec(), mode="bmc", depth=20)
self.assertFormal(PcFwdSpec(), mode="cover", depth=20, spec_name="verify_pc_fwd")
self.assertFormal(PcFwdSpec(), mode="bmc", depth=20, spec_name="verify_pc_fwd")
print("verify_pc_fwd PASS")
class PcBwdSpec(Elaboratable):
def elaborate(self, platform):
@ -279,8 +280,9 @@ class PcBwdSpec(Elaboratable):
class PcBwdTestCase(FHDLTestCase):
def verify(self):
self.assertFormal(PcBwdSpec(), mode="cover", depth=20)
self.assertFormal(PcBwdSpec(), mode="bmc", depth=20)
self.assertFormal(PcBwdSpec(), mode="cover", depth=20, spec_name="verify_pc_bwd")
self.assertFormal(PcBwdSpec(), mode="bmc", depth=20, spec_name="verify_pc_bwd")
print("verify_pc_bwd PASS")
class RegSpec(Elaboratable):
def elaborate(self, platform):
@ -330,8 +332,9 @@ class RegSpec(Elaboratable):
class RegTestCase(FHDLTestCase):
def verify(self):
self.assertFormal(RegSpec(), mode="cover", depth=10)
self.assertFormal(RegSpec(), mode="bmc", depth=10)
self.assertFormal(RegSpec(), mode="cover", depth=10, spec_name="verify_reg")
self.assertFormal(RegSpec(), mode="bmc", depth=10, spec_name="verify_reg")
print("verify_reg PASS")
class CausalSpec(Elaboratable):
def elaborate(self, platform):
@ -378,8 +381,9 @@ class CausalSpec(Elaboratable):
class CausalTestCase(FHDLTestCase):
def verify(self):
self.assertFormal(CausalSpec(), mode="cover", depth=20)
self.assertFormal(CausalSpec(), mode="bmc", depth=20)
self.assertFormal(CausalSpec(), mode="cover", depth=20, spec_name="verify_causal")
self.assertFormal(CausalSpec(), mode="bmc", depth=20, spec_name="verify_causal")
print("verify_causal PASS")
class LivenessSpec(Elaboratable):
def elaborate(self, platform):
@ -444,8 +448,9 @@ class LivenessSpec(Elaboratable):
class LivenessTestCase(FHDLTestCase):
def verify(self):
self.assertFormal(LivenessSpec(), mode="cover", depth=40)
self.assertFormal(LivenessSpec(), mode="bmc", depth=40)
self.assertFormal(LivenessSpec(), mode="cover", depth=40, spec_name="verify_liveness")
self.assertFormal(LivenessSpec(), mode="bmc", depth=40, spec_name="verify_liveness")
print("verify_liveness PASS")
class UniqueSpec(Elaboratable):
def elaborate(self, platform):
@ -493,8 +498,9 @@ class UniqueSpec(Elaboratable):
class UniqueTestCase(FHDLTestCase):
def verify(self):
self.assertFormal(UniqueSpec(), mode="cover", depth=25)
self.assertFormal(UniqueSpec(), mode="bmc", depth=25)
self.assertFormal(UniqueSpec(), mode="cover", depth=25, spec_name="verify_uniqueness")
self.assertFormal(UniqueSpec(), mode="bmc", depth=25, spec_name="verify_uniqueness")
print("verify_uniqueness PASS")
print('*' * 80)
print('*' + ' ' * 78 + '*')
@ -503,25 +509,40 @@ print('*' + ' ' * 78 + '*')
print('*' * 80)
print("Verifying RV32M instructions ...")
InsnTestCase().verify()
p_insn = Process(target=InsnTestCase().verify)
p_insn.start()
print("Verifying PC forward checks ...")
PcFwdTestCase().verify()
p_pc_fwd = Process(target=PcFwdTestCase().verify)
p_pc_fwd.start()
print("Verifying PC backward checks ...")
PcBwdTestCase().verify()
p_pc_bwd = Process(target=PcBwdTestCase().verify)
p_pc_bwd.start()
print("Verifying register checks ...")
RegTestCase().verify()
p_reg = Process(target=RegTestCase().verify)
p_reg.start()
print("Verifying causal checks ...")
CausalTestCase().verify()
p_causal = Process(target=CausalTestCase().verify)
p_causal.start()
print("Verifying liveness checks ...")
LivenessTestCase().verify()
p_liveness = Process(target=LivenessTestCase().verify)
p_liveness.start()
print("Verifying uniqueness checks ...")
UniqueTestCase().verify()
p_uniqueness = Process(target=UniqueTestCase().verify)
p_uniqueness.start()
p_insn.join()
p_pc_fwd.join()
p_pc_bwd.join()
p_reg.join()
p_causal.join()
p_liveness.join()
p_uniqueness.join()
print('*' * 80)
print('*' + ' ' * 78 + '*')