diff --git a/insns/IsaRV32I.py b/insns/IsaRV32I.py index e895d8d..c1a7985 100644 --- a/insns/IsaRV32I.py +++ b/insns/IsaRV32I.py @@ -143,6 +143,75 @@ class IsaRV32I(Elaboratable): m.submodules._or = insn_submodules['or'] = InsnOr(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA) m.submodules._and = insn_submodules['and'] = InsnAnd(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA) - # TODO + for _, insn in insn_submodules.items(): + m.d.comb += insn.rvfi_valid.eq(self.rvfi_valid) + m.d.comb += insn.rvfi_insn.eq(self.rvfi_insn) + m.d.comb += insn.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) + m.d.comb += insn.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) + m.d.comb += insn.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) + m.d.comb += insn.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) + if self.RISCV_FORMAL_CSR_MISA: + m.d.comb += insn.rvfi_csr_misa_rdata.eq(self.rvfi_csr_misa_rdata) + + spec_valid = 0 + for _, insn in insn_submodules.items(): + spec_valid = Mux(insn.spec_valid, insn.spec_valid, spec_valid) + m.d.comb += self.spec_valid.eq(spec_valid) + + spec_trap = 0 + for _, insn in insn_submodules.items(): + spec_trap = Mux(insn.spec_valid, insn.spec_trap, spec_trap) + m.d.comb += self.spec_trap.eq(spec_trap) + + spec_rs1_addr = 0 + for _, insn in insn_submodules.items(): + spec_rs1_addr = Mux(insn.spec_valid, insn.spec_rs1_addr, spec_rs1_addr) + m.d.comb += self.spec_rs1_addr.eq(spec_rs1_addr) + + spec_rs2_addr = 0 + for _, insn in insn_submodules.items(): + spec_rs2_addr = Mux(insn.spec_valid, insn.spec_rs2_addr, spec_rs2_addr) + m.d.comb += self.spec_rs2_addr.eq(spec_rs2_addr) + + spec_rd_addr = 0 + for _, insn in insn_submodules.items(): + spec_rd_addr = Mux(insn.spec_valid, insn.spec_rd_addr, spec_rd_addr) + m.d.comb += self.spec_rd_addr.eq(spec_rd_addr) + + spec_rd_wdata = 0 + for _, insn in insn_submodules.items(): + spec_rd_wdata = Mux(insn.spec_valid, insn.spec_rd_wdata, spec_rd_wdata) + m.d.comb += self.spec_rd_wdata.eq(spec_rd_wdata) + + spec_pc_wdata = 0 + for _, insn in insn_submodules.items(): + spec_pc_wdata = Mux(insn.spec_valid, insn.spec_pc_wdata, spec_pc_wdata) + m.d.comb += self.spec_pc_wdata.eq(spec_pc_wdata) + + spec_mem_addr = 0 + for _, insn in insn_submodules.items(): + spec_mem_addr = Mux(insn.spec_valid, insn.spec_mem_addr, spec_mem_addr) + m.d.comb += self.spec_mem_addr.eq(spec_mem_addr) + + spec_mem_rmask = 0 + for _, insn in insn_submodules.items(): + spec_mem_rmask = Mux(insn.spec_valid, insn.spec_mem_rmask, spec_mem_rmask) + m.d.comb += self.spec_mem_rmask.eq(spec_mem_rmask) + + spec_mem_wmask = 0 + for _, insn in insn_submodules.items(): + spec_mem_wmask = Mux(insn.spec_valid, insn.spec_mem_wmask, spec_mem_wmask) + m.d.comb += self.spec_mem_wmask.eq(spec_mem_wmask) + + spec_mem_wdata = 0 + for _, insn in insn_submodules.items(): + spec_mem_wdata = Mux(insn.spec_valid, insn.spec_mem_wdata, spec_mem_wdata) + m.d.comb += self.spec_mem_wdata.eq(spec_mem_wdata) + + if self.RISCV_FORMAL_CSR_MISA: + spec_csr_misa_rmask = 0 + for _, insn in insn_submodules.items(): + spec_csr_misa_rmask = Mux(insn.spec_valid, insn.spec_csr_misa_rmask, spec_csr_misa_rmask) + m.d.comb += self.spec_csr_misa_rmask.eq(spec_csr_misa_rmask) return m