diff --git a/README.md b/README.md
index 603f60e..93bc8ca 100644
--- a/README.md
+++ b/README.md
@@ -5,6 +5,8 @@ A port of [riscv-formal](https://github.com/SymbioticEDA/riscv-formal) to nMigen
 ## Dependencies
 
 - [nMigen](https://github.com/m-labs/nmigen)
+- [Yosys](https://github.com/YosysHQ/yosys)
+- [SymbiYosys](https://github.com/YosysHQ/SymbiYosys)
 
 ## Breakdown
 
@@ -17,7 +19,13 @@ A port of [riscv-formal](https://github.com/SymbioticEDA/riscv-formal) to nMigen
 
 ## Build
 
-This framework is not ready to be used to verify RISC-V compliant cores at the time of writing. Instructions for running the framework against such a core will be added once the framework is ready for use.
+### Minerva
+
+`cd` to the root directory of this project and do:
+
+```python
+$ python -m rvfi.cores.minerva.verify
+```
 
 ## Scope
 
diff --git a/rvfi/cores/minerva/verify.py b/rvfi/cores/minerva/verify.py
new file mode 100644
index 0000000..6db55d9
--- /dev/null
+++ b/rvfi/cores/minerva/verify.py
@@ -0,0 +1,9 @@
+import unittest
+from .test.test_cache import *
+from .test.test_units_divider import *
+from .test.test_units_multiplier import *
+
+test = L1CacheTestCase()
+test.test_direct_mapped()
+test.test_2_ways()
+unittest.main()