From 3eaed129c295d6a15ce618ebc527e606c8aca095 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Thu, 6 Aug 2020 12:36:01 +0800 Subject: [PATCH] Begin re-organization of project structure --- README.md | 2 +- checks/rvfi_causal_check.py | 81 -- checks/rvfi_channel.py | 103 --- checks/rvfi_dmem_check.py | 82 -- checks/rvfi_hang_check.py | 77 -- checks/rvfi_ill_check.py | 109 --- checks/rvfi_imem_check.py | 88 -- checks/rvfi_insn_check.py | 205 ----- checks/rvfi_liveness_check.py | 79 -- checks/rvfi_pc_bwd_check.py | 82 -- checks/rvfi_pc_fwd_check.py | 82 -- checks/rvfi_reg_check.py | 84 -- checks/rvfi_unique_check.py | 78 -- insns/README.md | 28 - insns/insn.py | 51 -- insns/insn_I.py | 38 - insns/insn_I_shift.py | 38 - insns/insn_R.py | 37 - insns/insn_S.py | 32 - insns/insn_SB.py | 38 - insns/insn_U.py | 33 - insns/insn_UJ.py | 34 - insns/insn_add.py | 21 - insns/insn_addi.py | 20 - insns/insn_and.py | 21 - insns/insn_andi.py | 20 - insns/insn_auipc.py | 17 - insns/insn_beq.py | 22 - insns/insn_bge.py | 22 - insns/insn_bgeu.py | 22 - insns/insn_blt.py | 22 - insns/insn_bltu.py | 22 - insns/insn_bne.py | 22 - insns/insn_div.py | 23 - insns/insn_divu.py | 23 - insns/insn_jal.py | 20 - insns/insn_jalr.py | 21 - insns/insn_lb.py | 25 - insns/insn_lbu.py | 25 - insns/insn_lh.py | 25 - insns/insn_lhu.py | 25 - insns/insn_lui.py | 17 - insns/insn_lw.py | 25 - insns/insn_mul.py | 23 - insns/insn_mulh.py | 23 - insns/insn_mulhsu.py | 23 - insns/insn_mulhu.py | 23 - insns/insn_or.py | 21 - insns/insn_ori.py | 20 - insns/insn_rem.py | 23 - insns/insn_remu.py | 23 - insns/insn_sb.py | 23 - insns/insn_sh.py | 23 - insns/insn_sll.py | 23 - insns/insn_slli.py | 20 - insns/insn_slt.py | 21 - insns/insn_slti.py | 20 - insns/insn_sltiu.py | 20 - insns/insn_sltu.py | 21 - insns/insn_sra.py | 23 - insns/insn_srai.py | 20 - insns/insn_srl.py | 23 - insns/insn_srli.py | 20 - insns/insn_sub.py | 21 - insns/insn_sw.py | 23 - insns/insn_types.md | 11 - insns/insn_xor.py | 21 - insns/insn_xori.py | 20 - insns/isa_rv32i.py | 1211 --------------------------- insns/isa_rv32i.txt | 37 - insns/isa_rv32i_gen.py | 107 --- insns/isa_rv32im.py | 1459 --------------------------------- insns/isa_rv32im.txt | 45 - insns/isa_rv32im_gen.py | 107 --- 74 files changed, 1 insertion(+), 5438 deletions(-) delete mode 100644 checks/rvfi_causal_check.py delete mode 100644 checks/rvfi_channel.py delete mode 100644 checks/rvfi_dmem_check.py delete mode 100644 checks/rvfi_hang_check.py delete mode 100644 checks/rvfi_ill_check.py delete mode 100644 checks/rvfi_imem_check.py delete mode 100644 checks/rvfi_insn_check.py delete mode 100644 checks/rvfi_liveness_check.py delete mode 100644 checks/rvfi_pc_bwd_check.py delete mode 100644 checks/rvfi_pc_fwd_check.py delete mode 100644 checks/rvfi_reg_check.py delete mode 100644 checks/rvfi_unique_check.py delete mode 100644 insns/README.md delete mode 100644 insns/insn.py delete mode 100644 insns/insn_I.py delete mode 100644 insns/insn_I_shift.py delete mode 100644 insns/insn_R.py delete mode 100644 insns/insn_S.py delete mode 100644 insns/insn_SB.py delete mode 100644 insns/insn_U.py delete mode 100644 insns/insn_UJ.py delete mode 100644 insns/insn_add.py delete mode 100644 insns/insn_addi.py delete mode 100644 insns/insn_and.py delete mode 100644 insns/insn_andi.py delete mode 100644 insns/insn_auipc.py delete mode 100644 insns/insn_beq.py delete mode 100644 insns/insn_bge.py delete mode 100644 insns/insn_bgeu.py delete mode 100644 insns/insn_blt.py delete mode 100644 insns/insn_bltu.py delete mode 100644 insns/insn_bne.py delete mode 100644 insns/insn_div.py delete mode 100644 insns/insn_divu.py delete mode 100644 insns/insn_jal.py delete mode 100644 insns/insn_jalr.py delete mode 100644 insns/insn_lb.py delete mode 100644 insns/insn_lbu.py delete mode 100644 insns/insn_lh.py delete mode 100644 insns/insn_lhu.py delete mode 100644 insns/insn_lui.py delete mode 100644 insns/insn_lw.py delete mode 100644 insns/insn_mul.py delete mode 100644 insns/insn_mulh.py delete mode 100644 insns/insn_mulhsu.py delete mode 100644 insns/insn_mulhu.py delete mode 100644 insns/insn_or.py delete mode 100644 insns/insn_ori.py delete mode 100644 insns/insn_rem.py delete mode 100644 insns/insn_remu.py delete mode 100644 insns/insn_sb.py delete mode 100644 insns/insn_sh.py delete mode 100644 insns/insn_sll.py delete mode 100644 insns/insn_slli.py delete mode 100644 insns/insn_slt.py delete mode 100644 insns/insn_slti.py delete mode 100644 insns/insn_sltiu.py delete mode 100644 insns/insn_sltu.py delete mode 100644 insns/insn_sra.py delete mode 100644 insns/insn_srai.py delete mode 100644 insns/insn_srl.py delete mode 100644 insns/insn_srli.py delete mode 100644 insns/insn_sub.py delete mode 100644 insns/insn_sw.py delete mode 100644 insns/insn_types.md delete mode 100644 insns/insn_xor.py delete mode 100644 insns/insn_xori.py delete mode 100644 insns/isa_rv32i.py delete mode 100644 insns/isa_rv32i.txt delete mode 100644 insns/isa_rv32i_gen.py delete mode 100644 insns/isa_rv32im.py delete mode 100644 insns/isa_rv32im.txt delete mode 100644 insns/isa_rv32im_gen.py diff --git a/README.md b/README.md index e08822d..4da6fa1 100644 --- a/README.md +++ b/README.md @@ -12,7 +12,7 @@ TODO ## Scope -The full [RISC-V specification](https://riscv.org/specifications/) is hundreds of pages long including numerous possible extensions, some of which are still under active development at the time of writing. Therefore, this project does not aim to formalize the entire specification, but only the core parts of the specification, namely RV32I (except FENCE, ECALL and EBREAK) and perhaps RV32IM. Support for other extensions of the RISC-V specification may be added in the future. +As with the original riscv-formal, support is planned for the RV32I and RV64I base ISAs, as well as the M and C extensions and combinations thereof (e.g. RV32IM, RV64IMC). ## License diff --git a/checks/rvfi_causal_check.py b/checks/rvfi_causal_check.py deleted file mode 100644 index df87bab..0000000 --- a/checks/rvfi_causal_check.py +++ /dev/null @@ -1,81 +0,0 @@ -from nmigen import * -from nmigen.hdl.ast import * - -class rvfi_causal_check(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.reset = Signal(1) - self.check = Signal(1) - self.rvfi_valid = Signal(1) - self.rvfi_order = Signal(64) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_trap = Signal(1) - self.rvfi_halt = Signal(1) - self.rvfi_intr = Signal(1) - self.rvfi_mode = Signal(2) - self.rvfi_ixl = Signal(2) - self.rvfi_rs1_addr = Signal(5) - self.rvfi_rs2_addr = Signal(5) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rd_addr = Signal(5) - self.rvfi_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.reset, - self.check, - self.rvfi_valid, - self.rvfi_order, - self.rvfi_insn, - self.rvfi_trap, - self.rvfi_halt, - self.rvfi_intr, - self.rvfi_mode, - self.rvfi_ixl, - self.rvfi_rs1_addr, - self.rvfi_rs2_addr, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_rd_addr, - self.rvfi_rd_wdata, - self.rvfi_pc_rdata, - self.rvfi_pc_wdata, - self.rvfi_mem_addr, - self.rvfi_mem_rmask, - self.rvfi_mem_wmask, - self.rvfi_mem_rdata, - self.rvfi_mem_wdata - ] - output_ports = [] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - insn_order = AnyConst(64) - register_index = AnyConst(5) - found_non_causal = Signal(1, reset=0) - - with m.If(self.reset): - m.d.sync += found_non_causal.eq(0) - with m.Else(): - with m.If(self.check): - m.d.comb += Assume(register_index != 0) - m.d.comb += Assume(self.rvfi_valid) - m.d.comb += Assume(register_index == self.rvfi_rd_addr) - m.d.comb += Assume(insn_order == self.rvfi_order) - m.d.comb += Assert(~found_non_causal) - with m.Else(): - with m.If(self.rvfi_valid & (self.rvfi_order > insn_order) & \ - ((register_index == self.rvfi_rs1_addr) | \ - (register_index == self.rvfi_rs2_addr))): - m.d.sync += found_non_causal.eq(1) - - return m diff --git a/checks/rvfi_channel.py b/checks/rvfi_channel.py deleted file mode 100644 index e149c19..0000000 --- a/checks/rvfi_channel.py +++ /dev/null @@ -1,103 +0,0 @@ -from nmigen import * -from nmigen.hdl.ast import * - -class rvfi_channel(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_order = Signal(64) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_trap = Signal(1) - self.rvfi_halt = Signal(1) - self.rvfi_intr = Signal(1) - self.rvfi_mode = Signal(2) - self.rvfi_ixl = Signal(2) - self.rvfi_rs1_addr = Signal(5) - self.rvfi_rs2_addr = Signal(5) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rd_addr = Signal(5) - self.rvfi_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_order, - self.rvfi_insn, - self.rvfi_trap, - self.rvfi_halt, - self.rvfi_intr, - self.rvfi_mode, - self.rvfi_ixl, - self.rvfi_rs1_addr, - self.rvfi_rs2_addr, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_rd_addr, - self.rvfi_rd_wdata, - self.rvfi_pc_rdata, - self.rvfi_pc_wdata, - self.rvfi_mem_addr, - self.rvfi_mem_rmask, - self.rvfi_mem_wmask, - self.rvfi_mem_rdata, - self.rvfi_mem_wdata - ] - output_ports = [] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - valid = Signal(1) - m.d.comb += valid.eq(self.rvfi_valid) - order = Signal(64) - m.d.comb += order.eq(self.rvfi_order) - insn = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn.eq(self.rvfi_insn) - trap = Signal(1) - m.d.comb += trap.eq(self.rvfi_trap) - halt = Signal(1) - m.d.comb += halt.eq(self.rvfi_halt) - intr = Signal(1) - m.d.comb += intr.eq(self.rvfi_intr) - mode = Signal(2) - m.d.comb += mode.eq(self.rvfi_mode) - ixl = Signal(2) - m.d.comb += ixl.eq(self.rvfi_ixl) - - rs1_addr = Signal(5) - m.d.comb += rs1_addr.eq(self.rvfi_rs1_addr) - rs2_addr = Signal(5) - m.d.comb += rs2_addr.eq(self.rvfi_rs2_addr) - rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += rs1_rdata.eq(self.rvfi_rs1_rdata) - rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += rs2_rdata.eq(self.rvfi_rs2_rdata) - rd_addr = Signal(5) - m.d.comb += rd_addr.eq(self.rvfi_rd_addr) - rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += rd_wdata.eq(self.rvfi_rd_wdata) - pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += pc_rdata.eq(self.rvfi_pc_rdata) - pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += pc_wdata.eq(self.rvfi_pc_wdata) - - mem_addr = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += mem_addr.eq(self.rvfi_mem_addr) - mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - m.d.comb += mem_rmask.eq(self.rvfi_mem_rmask) - mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - m.d.comb += mem_wmask.eq(self.rvfi_mem_wmask) - mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += mem_rdata.eq(self.rvfi_mem_rdata) - mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += mem_wdata.eq(self.rvfi_mem_wdata) - - return m diff --git a/checks/rvfi_dmem_check.py b/checks/rvfi_dmem_check.py deleted file mode 100644 index 4444ed7..0000000 --- a/checks/rvfi_dmem_check.py +++ /dev/null @@ -1,82 +0,0 @@ -from nmigen import * -from nmigen.hdl.ast import * - -class rvfi_dmem_check(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.reset = Signal(1) - self.enable = Signal(1) - self.dmem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_valid = Signal(1) - self.rvfi_order = Signal(64) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_trap = Signal(1) - self.rvfi_halt = Signal(1) - self.rvfi_intr = Signal(1) - self.rvfi_mode = Signal(2) - self.rvfi_ixl = Signal(2) - self.rvfi_rs1_addr = Signal(5) - self.rvfi_rs2_addr = Signal(5) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rd_addr = Signal(5) - self.rvfi_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.reset, - self.enable, - self.rvfi_valid, - self.rvfi_order, - self.rvfi_insn, - self.rvfi_trap, - self.rvfi_halt, - self.rvfi_intr, - self.rvfi_mode, - self.rvfi_ixl, - self.rvfi_rs1_addr, - self.rvfi_rs2_addr, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_rd_addr, - self.rvfi_rd_wdata, - self.rvfi_pc_rdata, - self.rvfi_pc_wdata, - self.rvfi_mem_addr, - self.rvfi_mem_rmask, - self.rvfi_mem_wmask, - self.rvfi_mem_rdata, - self.rvfi_mem_wdata - ] - output_ports = [ - self.dmem_addr - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - dmem_addr_randval = AnyConst(self.RISCV_FORMAL_XLEN) - m.d.comb += self.dmem_addr.eq(dmem_addr_randval) - - dmem_shadow = Signal(self.RISCV_FORMAL_XLEN) - dmem_written = Signal(int(self.RISCV_FORMAL_XLEN // 8), reset=0) - - with m.If(self.reset): - m.d.sync += dmem_written.eq(0) - with m.Else(): - with m.If(self.rvfi_valid & (self.rvfi_mem_addr == self.dmem_addr) & 1): - for i in range(int(self.RISCV_FORMAL_XLEN // 8)): - with m.If(self.enable & self.rvfi_mem_rmask[i] & dmem_written[i]): - m.d.comb += Assert(dmem_shadow[i*8:i*8+8] == self.rvfi_mem_rdata[i*8:i*8+8]) - with m.If(self.rvfi_mem_wmask[i]): - m.d.sync += dmem_shadow[i*8:i*8+8].eq(self.rvfi_mem_wdata[i*8:i*8+8]) - m.d.sync += dmem_written[i].eq(1) - - return m diff --git a/checks/rvfi_hang_check.py b/checks/rvfi_hang_check.py deleted file mode 100644 index acfc371..0000000 --- a/checks/rvfi_hang_check.py +++ /dev/null @@ -1,77 +0,0 @@ -from nmigen import * -from nmigen.hdl.ast import * - -class rvfi_hang_check(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.reset = Signal(1) - self.trig = Signal(1) - self.check = Signal(1) - self.rvfi_valid = Signal(1) - self.rvfi_order = Signal(64) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_trap = Signal(1) - self.rvfi_halt = Signal(1) - self.rvfi_intr = Signal(1) - self.rvfi_mode = Signal(2) - self.rvfi_ixl = Signal(2) - self.rvfi_rs1_addr = Signal(5) - self.rvfi_rs2_addr = Signal(5) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rd_addr = Signal(5) - self.rvfi_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.reset, - self.trig, - self.check, - self.rvfi_valid, - self.rvfi_order, - self.rvfi_insn, - self.rvfi_trap, - self.rvfi_halt, - self.rvfi_intr, - self.rvfi_mode, - self.rvfi_ixl, - self.rvfi_rs1_addr, - self.rvfi_rs2_addr, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_rd_addr, - self.rvfi_rd_wdata, - self.rvfi_pc_rdata, - self.rvfi_pc_wdata, - self.rvfi_mem_addr, - self.rvfi_mem_rmask, - self.rvfi_mem_wmask, - self.rvfi_mem_rdata, - self.rvfi_mem_wdata - ] - output_ports = [] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - okay = Signal(1, reset=0) - - with m.If(self.reset): - m.d.sync += okay.eq(0) - with m.Else(): - with m.If(self.rvfi_valid): - m.d.sync += okay.eq(1) - with m.If(self.check): - m.d.comb += Assert(okay) - with m.If(self.rvfi_valid): - m.d.comb += Assume(~self.rvfi_halt) - m.d.comb += Assume(self.rvfi_insn != 0b00010000010100000000000001110011) # WFI - - return m diff --git a/checks/rvfi_ill_check.py b/checks/rvfi_ill_check.py deleted file mode 100644 index e2e17f7..0000000 --- a/checks/rvfi_ill_check.py +++ /dev/null @@ -1,109 +0,0 @@ -from nmigen import * -from nmigen.hdl.ast import * - -class rvfi_ill_check(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.reset = Signal(1) - self.check = Signal(1) - self.rvfi_valid = Signal(1) - self.rvfi_order = Signal(64) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_trap = Signal(1) - self.rvfi_halt = Signal(1) - self.rvfi_intr = Signal(1) - self.rvfi_mode = Signal(2) - self.rvfi_ixl = Signal(2) - self.rvfi_rs1_addr = Signal(5) - self.rvfi_rs2_addr = Signal(5) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rd_addr = Signal(5) - self.rvfi_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.reset, - self.check, - self.rvfi_valid, - self.rvfi_order, - self.rvfi_insn, - self.rvfi_trap, - self.rvfi_halt, - self.rvfi_intr, - self.rvfi_mode, - self.rvfi_ixl, - self.rvfi_rs1_addr, - self.rvfi_rs2_addr, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_rd_addr, - self.rvfi_rd_wdata, - self.rvfi_pc_rdata, - self.rvfi_pc_wdata, - self.rvfi_mem_addr, - self.rvfi_mem_rmask, - self.rvfi_mem_wmask, - self.rvfi_mem_rdata, - self.rvfi_mem_wdata - ] - output_ports = [] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - valid = Signal(1) - m.d.comb += valid.eq((~self.reset) & self.rvfi_valid) - insn = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn.eq(self.rvfi_insn) - trap = Signal(1) - m.d.comb += trap.eq(self.rvfi_trap) - halt = Signal(1) - m.d.comb += halt.eq(self.rvfi_halt) - intr = Signal(1) - m.d.comb += intr.eq(self.rvfi_intr) - rs1_addr = Signal(5) - m.d.comb += rs1_addr.eq(self.rvfi_rs1_addr) - rs2_addr = Signal(5) - m.d.comb += rs2_addr.eq(self.rvfi_rs2_addr) - rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += rs1_rdata.eq(self.rvfi_rs1_rdata) - rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += rs2_rdata.eq(self.rvfi_rs2_rdata) - rd_addr = Signal(5) - m.d.comb += rd_addr.eq(self.rvfi_rd_addr) - rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += rd_wdata.eq(self.rvfi_rd_wdata) - pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += pc_rdata.eq(self.rvfi_pc_rdata) - pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += pc_wdata.eq(self.rvfi_pc_wdata) - - mem_addr = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += mem_addr.eq(self.rvfi_mem_addr) - mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - m.d.comb += mem_rmask.eq(self.rvfi_mem_rmask) - mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - m.d.comb += mem_wmask.eq(self.rvfi_mem_wmask) - mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += mem_rdata.eq(self.rvfi_mem_rdata) - mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += mem_wdata.eq(self.rvfi_mem_wdata) - - m.d.comb += Cover((~self.reset) & self.check & valid & (insn == 0)) - with m.If((~self.reset) & self.check): - m.d.comb += Assume(valid) - m.d.comb += Assume(insn == 0) - m.d.comb += Assert(trap) - m.d.comb += Assert(rd_addr == 0) - m.d.comb += Assert(rd_wdata == 0) - m.d.comb += Assert(mem_wmask == 0) - - return m diff --git a/checks/rvfi_imem_check.py b/checks/rvfi_imem_check.py deleted file mode 100644 index 304a988..0000000 --- a/checks/rvfi_imem_check.py +++ /dev/null @@ -1,88 +0,0 @@ -from nmigen import * -from nmigen.hdl.ast import * - -class rvfi_imem_check(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.reset = Signal(1) - self.enable = Signal(1) - self.imem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.imem_data = Signal(16) - self.rvfi_valid = Signal(1) - self.rvfi_order = Signal(64) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_trap = Signal(1) - self.rvfi_halt = Signal(1) - self.rvfi_intr = Signal(1) - self.rvfi_mode = Signal(2) - self.rvfi_ixl = Signal(2) - self.rvfi_rs1_addr = Signal(5) - self.rvfi_rs2_addr = Signal(5) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rd_addr = Signal(5) - self.rvfi_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.reset, - self.enable, - self.rvfi_valid, - self.rvfi_order, - self.rvfi_insn, - self.rvfi_trap, - self.rvfi_halt, - self.rvfi_intr, - self.rvfi_mode, - self.rvfi_ixl, - self.rvfi_rs1_addr, - self.rvfi_rs2_addr, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_rd_addr, - self.rvfi_rd_wdata, - self.rvfi_pc_rdata, - self.rvfi_pc_wdata, - self.rvfi_mem_addr, - self.rvfi_mem_rmask, - self.rvfi_mem_wmask, - self.rvfi_mem_rdata, - self.rvfi_mem_wdata - ] - output_ports = [ - self.imem_addr, - self.imem_data - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - imem_addr_randval = AnyConst(self.RISCV_FORMAL_XLEN) - imem_data_randval = AnyConst(16) - m.d.comb += self.imem_addr.eq(imem_addr_randval) - m.d.comb += self.imem_data.eq(imem_data_randval) - - pc = Signal(self.RISCV_FORMAL_XLEN) - insn = Signal(self.RISCV_FORMAL_ILEN) - - with m.If(self.reset): - pass - with m.Else(): - with m.If(self.enable & self.rvfi_valid): - m.d.sync += pc.eq(self.rvfi_pc_rdata) - m.d.sync += insn.eq(self.rvfi_insn) - - with m.If(pc == self.imem_addr): - m.d.comb += Assert(insn[:16] == self.imem_data) - - with m.If((insn[:2] == 0b11) & (pc + 2 == self.imem_addr)): - m.d.comb += Assert(insn[16:32] == self.imem_data) - - return m diff --git a/checks/rvfi_insn_check.py b/checks/rvfi_insn_check.py deleted file mode 100644 index 5a9b4cf..0000000 --- a/checks/rvfi_insn_check.py +++ /dev/null @@ -1,205 +0,0 @@ -from nmigen import * -from nmigen.hdl.ast import * - -# Ugly hack for now to get the insn_add import working -import sys -sys.path.append('../insns') -from insn_add import * - -class rvfi_insn_check(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.reset = Signal(1) - self.check = Signal(1) - self.rvfi_valid = Signal(1) - self.rvfi_order = Signal(64) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_trap = Signal(1) - self.rvfi_halt = Signal(1) - self.rvfi_intr = Signal(1) - self.rvfi_mode = Signal(2) - self.rvfi_ixl = Signal(2) - self.rvfi_rs1_addr = Signal(5) - self.rvfi_rs2_addr = Signal(5) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rd_addr = Signal(5) - self.rvfi_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.reset, - self.check, - self.rvfi_valid, - self.rvfi_order, - self.rvfi_insn, - self.rvfi_trap, - self.rvfi_halt, - self.rvfi_intr, - self.rvfi_mode, - self.rvfi_ixl, - self.rvfi_rs1_addr, - self.rvfi_rs2_addr, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_rd_addr, - self.rvfi_rd_wdata, - self.rvfi_pc_rdata, - self.rvfi_pc_wdata, - self.rvfi_mem_addr, - self.rvfi_mem_rmask, - self.rvfi_mem_wmask, - self.rvfi_mem_rdata, - self.rvfi_mem_wdata - ] - output_ports = [] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - valid = Signal(1) - m.d.comb += valid.eq((~self.reset) & self.rvfi_valid) - insn = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn.eq(self.rvfi_insn) - trap = Signal(1) - m.d.comb += trap.eq(self.rvfi_trap) - halt = Signal(1) - m.d.comb += halt.eq(self.rvfi_halt) - intr = Signal(1) - m.d.comb += intr.eq(self.rvfi_intr) - rs1_addr = Signal(5) - m.d.comb += rs1_addr.eq(self.rvfi_rs1_addr) - rs2_addr = Signal(5) - m.d.comb += rs2_addr.eq(self.rvfi_rs2_addr) - rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += rs1_rdata.eq(self.rvfi_rs1_rdata) - rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += rs2_rdata.eq(self.rvfi_rs2_rdata) - rd_addr = Signal(5) - m.d.comb += rd_addr.eq(self.rvfi_rd_addr) - rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += rd_wdata.eq(self.rvfi_rd_wdata) - pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += pc_rdata.eq(self.rvfi_pc_rdata) - pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += pc_wdata.eq(self.rvfi_pc_wdata) - - mem_addr = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += mem_addr.eq(self.rvfi_mem_addr) - mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - m.d.comb += mem_rmask.eq(self.rvfi_mem_rmask) - mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - m.d.comb += mem_wmask.eq(self.rvfi_mem_wmask) - mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += mem_rdata.eq(self.rvfi_mem_rdata) - mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += mem_wdata.eq(self.rvfi_mem_wdata) - - spec_valid = Signal(1) - spec_trap = Signal(1) - spec_rs1_addr = Signal(5) - spec_rs2_addr = Signal(5) - spec_rd_addr = Signal(5) - spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - - rs1_rdata_or_zero = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += rs1_rdata_or_zero.eq(Mux(spec_rs1_addr != 0, rs1_rdata, 0)) - rs2_rdata_or_zero = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += rs2_rdata_or_zero.eq(Mux(spec_rs2_addr != 0, rs2_rdata, 0)) - - # Change this submodule accordingly to test for different instructions(?) - m.submodules.insn_spec = insn_spec = rvfi_insn_add(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN) - - m.d.comb += insn_spec.rvfi_valid.eq(valid) - m.d.comb += insn_spec.rvfi_insn.eq(insn) - m.d.comb += insn_spec.rvfi_pc_rdata.eq(pc_rdata) - m.d.comb += insn_spec.rvfi_rs1_rdata.eq(rs1_rdata_or_zero) - m.d.comb += insn_spec.rvfi_rs2_rdata.eq(rs2_rdata_or_zero) - m.d.comb += insn_spec.rvfi_mem_rdata.eq(mem_rdata) - - m.d.comb += spec_valid.eq(insn_spec.spec_valid) - m.d.comb += spec_trap.eq(insn_spec.spec_trap) - m.d.comb += spec_rs1_addr.eq(insn_spec.spec_rs1_addr) - m.d.comb += spec_rs2_addr.eq(insn_spec.spec_rs2_addr) - m.d.comb += spec_rd_addr.eq(insn_spec.spec_rd_addr) - m.d.comb += spec_rd_wdata.eq(insn_spec.spec_rd_wdata) - m.d.comb += spec_pc_wdata.eq(insn_spec.spec_pc_wdata) - m.d.comb += spec_mem_addr.eq(insn_spec.spec_mem_addr) - m.d.comb += spec_mem_rmask.eq(insn_spec.spec_mem_rmask) - m.d.comb += spec_mem_wmask.eq(insn_spec.spec_mem_wmask) - m.d.comb += spec_mem_wdata.eq(insn_spec.spec_mem_wdata) - - insn_pma_x = Signal(1) - mem_pma_r = Signal(1) - mem_pma_w = Signal(1) - - mem_log2len = Signal(2) - m.d.comb += mem_log2len.eq(Mux((spec_mem_rmask | spec_mem_wmask) & 0b11110000, 3, Mux((spec_mem_rmask | spec_mem_wmask) & 0b00001100, 2, Mux((spec_mem_rmask | spec_mem_wmask) & 0b00000010, 1, 0)))) - - m.d.comb += insn_pma_x.eq(1) - m.d.comb += mem_pma_r.eq(1) - m.d.comb += mem_pma_w.eq(1) - - mem_access_fault = Signal(1) - m.d.comb += mem_access_fault.eq((spec_mem_rmask & ~mem_pma_r) | (spec_mem_wmask & ~mem_pma_w) | (spec_mem_rmask | spec_mem_wmask)) - - with m.If(~self.reset): - m.d.comb += Cover(spec_valid) - m.d.comb += Cover(spec_valid & ~trap) - m.d.comb += Cover(self.check & spec_valid) - m.d.comb += Cover(self.check & spec_valid & ~trap) - with m.If((~self.reset) & self.check): - m.d.comb += Assume(spec_valid) - - with m.If((~insn_pma_x) | mem_access_fault): - m.d.comb += Assert(trap) - m.d.comb += Assert(rd_addr == 0) - m.d.comb += Assert(rd_wdata == 0) - m.d.comb += Assert(mem_wmask == 0) - with m.Else(): - with m.If(rs1_addr == 0): - m.d.comb += Assert(rs1_rdata == 0) - - with m.If(rs2_addr == 0): - m.d.comb += Assert(rs2_rdata == 0) - - with m.If(~spec_trap): - with m.If(spec_rs1_addr != 0): - m.d.comb += Assert(spec_rs1_addr == rs1_addr) - - with m.If(spec_rs2_addr != 0): - m.d.comb += Assert(spec_rs2_addr == rs2_addr) - - m.d.comb += Assert(spec_rd_addr == rd_addr) - m.d.comb += Assert(spec_rd_wdata == rd_wdata) - m.d.comb += Assert(spec_pc_wdata == pc_wdata) - - with m.If(spec_mem_wmask | spec_mem_rmask): - m.d.comb += Assert(spec_mem_addr == mem_addr) - - for i in range(int(self.RISCV_FORMAL_XLEN // 8)): - with m.If(spec_mem_wmask[i]): - m.d.comb += Assert(mem_wmask[i]) - m.d.comb += Assert(spec_mem_wdata[i*8:i*8+8] == mem_wdata[i*8:i*8+8]) - with m.Elif(mem_wmask[i]): - m.d.comb += Assert(mem_rmask[i]) - m.d.comb += Assert(mem_rdata[i*8:i*8+8] == mem_wdata[i*8:i*8+8]) - with m.If(spec_mem_rmask[i]): - m.d.comb += Assert(mem_rmask[i]) - - - m.d.comb += Assert(spec_trap == trap) - - return m diff --git a/checks/rvfi_liveness_check.py b/checks/rvfi_liveness_check.py deleted file mode 100644 index 29210df..0000000 --- a/checks/rvfi_liveness_check.py +++ /dev/null @@ -1,79 +0,0 @@ -from nmigen import * -from nmigen.hdl.ast import * - -class rvfi_liveness_check(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.reset = Signal(1) - self.trig = Signal(1) - self.check = Signal(1) - self.rvfi_valid = Signal(1) - self.rvfi_order = Signal(64) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_trap = Signal(1) - self.rvfi_halt = Signal(1) - self.rvfi_intr = Signal(1) - self.rvfi_mode = Signal(2) - self.rvfi_ixl = Signal(2) - self.rvfi_rs1_addr = Signal(5) - self.rvfi_rs2_addr = Signal(5) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rd_addr = Signal(5) - self.rvfi_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.reset, - self.trig, - self.check, - self.rvfi_valid, - self.rvfi_order, - self.rvfi_insn, - self.rvfi_trap, - self.rvfi_halt, - self.rvfi_intr, - self.rvfi_mode, - self.rvfi_ixl, - self.rvfi_rs1_addr, - self.rvfi_rs2_addr, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_rd_addr, - self.rvfi_rd_wdata, - self.rvfi_pc_rdata, - self.rvfi_pc_wdata, - self.rvfi_mem_addr, - self.rvfi_mem_rmask, - self.rvfi_mem_wmask, - self.rvfi_mem_rdata, - self.rvfi_mem_wdata - ] - output_ports = [] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - insn_order = AnyConst(64) - found_next_insn = Signal(1, reset=0) - - with m.If(self.reset): - m.d.sync += found_next_insn.eq(0) - with m.Else(): - with m.If(self.rvfi_valid & (self.rvfi_order == insn_order + 1)): - m.d.sync += found_next_insn.eq(1) - with m.If(self.trig): - m.d.comb += Assume(self.rvfi_valid) - m.d.comb += Assume(~self.rvfi_halt) - m.d.comb += Assume(insn_order == self.rvfi_order) - with m.If(self.check): - m.d.comb += Assert(found_next_insn) - - return m diff --git a/checks/rvfi_pc_bwd_check.py b/checks/rvfi_pc_bwd_check.py deleted file mode 100644 index c025fa0..0000000 --- a/checks/rvfi_pc_bwd_check.py +++ /dev/null @@ -1,82 +0,0 @@ -from nmigen import * -from nmigen.hdl.ast import * - -class rvfi_pc_bwd_check(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.reset = Signal(1) - self.check = Signal(1) - self.rvfi_valid = Signal(1) - self.rvfi_order = Signal(64) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_trap = Signal(1) - self.rvfi_halt = Signal(1) - self.rvfi_intr = Signal(1) - self.rvfi_mode = Signal(2) - self.rvfi_ixl = Signal(2) - self.rvfi_rs1_addr = Signal(5) - self.rvfi_rs2_addr = Signal(5) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rd_addr = Signal(5) - self.rvfi_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.reset, - self.check, - self.rvfi_valid, - self.rvfi_order, - self.rvfi_insn, - self.rvfi_trap, - self.rvfi_halt, - self.rvfi_intr, - self.rvfi_mode, - self.rvfi_ixl, - self.rvfi_rs1_addr, - self.rvfi_rs2_addr, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_rd_addr, - self.rvfi_rd_wdata, - self.rvfi_pc_rdata, - self.rvfi_pc_wdata, - self.rvfi_mem_addr, - self.rvfi_mem_rmask, - self.rvfi_mem_wmask, - self.rvfi_mem_rdata, - self.rvfi_mem_wdata - ] - output_ports = [] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - insn_order = AnyConst(64) - expect_pc = Signal(self.RISCV_FORMAL_XLEN) - expect_pc_valid = Signal(1, reset=0) - - pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += pc_wdata.eq(self.rvfi_pc_wdata) - - with m.If(self.reset): - m.d.sync += expect_pc_valid.eq(0) - with m.Else(): - with m.If(self.check): - m.d.comb += Assume(self.rvfi_valid) - m.d.comb += Assume(insn_order == self.rvfi_order) - with m.If(expect_pc_valid): - m.d.comb += Assert(expect_pc == pc_wdata) - with m.Else(): - with m.If(self.rvfi_valid & (self.rvfi_order == insn_order + 1)): - m.d.sync += expect_pc.eq(self.rvfi_pc_rdata) - m.d.sync += expect_pc_valid.eq(1) - - return m diff --git a/checks/rvfi_pc_fwd_check.py b/checks/rvfi_pc_fwd_check.py deleted file mode 100644 index 9fa5c61..0000000 --- a/checks/rvfi_pc_fwd_check.py +++ /dev/null @@ -1,82 +0,0 @@ -from nmigen import * -from nmigen.hdl.ast import * - -class rvfi_pc_fwd_check(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.reset = Signal(1) - self.check = Signal(1) - self.rvfi_valid = Signal(1) - self.rvfi_order = Signal(64) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_trap = Signal(1) - self.rvfi_halt = Signal(1) - self.rvfi_intr = Signal(1) - self.rvfi_mode = Signal(2) - self.rvfi_ixl = Signal(2) - self.rvfi_rs1_addr = Signal(5) - self.rvfi_rs2_addr = Signal(5) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rd_addr = Signal(5) - self.rvfi_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.reset, - self.check, - self.rvfi_valid, - self.rvfi_order, - self.rvfi_insn, - self.rvfi_trap, - self.rvfi_halt, - self.rvfi_intr, - self.rvfi_mode, - self.rvfi_ixl, - self.rvfi_rs1_addr, - self.rvfi_rs2_addr, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_rd_addr, - self.rvfi_rd_wdata, - self.rvfi_pc_rdata, - self.rvfi_pc_wdata, - self.rvfi_mem_addr, - self.rvfi_mem_rmask, - self.rvfi_mem_wmask, - self.rvfi_mem_rdata, - self.rvfi_mem_wdata - ] - output_ports = [] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - insn_order = AnyConst(64) - expect_pc = Signal(self.RISCV_FORMAL_XLEN) - expect_pc_valid = Signal(1, reset=0) - - pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += pc_rdata.eq(self.rvfi_pc_rdata) - - with m.If(self.reset): - m.d.sync += expect_pc_valid.eq(0) - with m.Else(): - with m.If(self.check): - m.d.comb += Assume(self.rvfi_valid) - m.d.comb += Assume(insn_order == self.rvfi_order) - with m.If(expect_pc_valid): - m.d.comb += Assert(expect_pc == pc_rdata) - with m.Else(): - with m.If(self.rvfi_valid & (self.rvfi_order == insn_order - 1)): - m.d.sync += expect_pc.eq(self.rvfi_pc_wdata) - m.d.sync += expect_pc_valid.eq(1) - - return m diff --git a/checks/rvfi_reg_check.py b/checks/rvfi_reg_check.py deleted file mode 100644 index 5347be8..0000000 --- a/checks/rvfi_reg_check.py +++ /dev/null @@ -1,84 +0,0 @@ -from nmigen import * -from nmigen.hdl.ast import * - -class rvfi_reg_check(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.reset = Signal(1) - self.check = Signal(1) - self.rvfi_valid = Signal(1) - self.rvfi_order = Signal(64) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_trap = Signal(1) - self.rvfi_halt = Signal(1) - self.rvfi_intr = Signal(1) - self.rvfi_mode = Signal(2) - self.rvfi_ixl = Signal(2) - self.rvfi_rs1_addr = Signal(5) - self.rvfi_rs2_addr = Signal(5) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rd_addr = Signal(5) - self.rvfi_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.reset, - self.check, - self.rvfi_valid, - self.rvfi_order, - self.rvfi_insn, - self.rvfi_trap, - self.rvfi_halt, - self.rvfi_intr, - self.rvfi_mode, - self.rvfi_ixl, - self.rvfi_rs1_addr, - self.rvfi_rs2_addr, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_rd_addr, - self.rvfi_rd_wdata, - self.rvfi_pc_rdata, - self.rvfi_pc_wdata, - self.rvfi_mem_addr, - self.rvfi_mem_rmask, - self.rvfi_mem_wmask, - self.rvfi_mem_rdata, - self.rvfi_mem_wdata - ] - output_ports = [] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - insn_order = AnyConst(64) - register_index = AnyConst(5) - register_shadow = Signal(self.RISCV_FORMAL_XLEN, reset=0) - register_written = Signal(1, reset=0) - - with m.If(self.reset): - m.d.sync += register_shadow.eq(0) - m.d.sync += register_written.eq(0) - with m.Else(): - with m.If(self.check): - m.d.comb += Assume(self.rvfi_valid) - m.d.comb += Assume(insn_order == self.rvfi_order) - - with m.If(register_written & (register_index == self.rvfi_rs1_addr)): - m.d.comb += Assert(register_shadow == self.rvfi_rs1_rdata) - with m.If(register_written & (register_index == self.rvfi_rs2_addr)): - m.d.comb += Assert(register_shadow == self.rvfi_rs2_rdata) - with m.Else(): - with m.If(self.rvfi_valid & (self.rvfi_order < insn_order) & (register_index == self.rvfi_rd_addr)): - m.d.sync += register_shadow.eq(self.rvfi_rd_wdata) - m.d.sync += register_written.eq(1) - - return m diff --git a/checks/rvfi_unique_check.py b/checks/rvfi_unique_check.py deleted file mode 100644 index fe73ba5..0000000 --- a/checks/rvfi_unique_check.py +++ /dev/null @@ -1,78 +0,0 @@ -from nmigen import * -from nmigen.hdl.ast import * - -class rvfi_unique_check(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.reset = Signal(1) - self.trig = Signal(1) - self.check = Signal(1) - self.rvfi_valid = Signal(1) - self.rvfi_order = Signal(64) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_trap = Signal(1) - self.rvfi_halt = Signal(1) - self.rvfi_intr = Signal(1) - self.rvfi_mode = Signal(2) - self.rvfi_ixl = Signal(2) - self.rvfi_rs1_addr = Signal(5) - self.rvfi_rs2_addr = Signal(5) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rd_addr = Signal(5) - self.rvfi_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.reset, - self.trig, - self.check, - self.rvfi_valid, - self.rvfi_order, - self.rvfi_insn, - self.rvfi_trap, - self.rvfi_halt, - self.rvfi_intr, - self.rvfi_mode, - self.rvfi_ixl, - self.rvfi_rs1_addr, - self.rvfi_rs2_addr, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_rd_addr, - self.rvfi_rd_wdata, - self.rvfi_pc_rdata, - self.rvfi_pc_wdata, - self.rvfi_mem_addr, - self.rvfi_mem_rmask, - self.rvfi_mem_wmask, - self.rvfi_mem_rdata, - self.rvfi_mem_wdata - ] - output_ports = [] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - insn_order = AnyConst(64) - found_other_insn = Signal(1, reset=0) - - with m.If(self.reset): - m.d.sync += found_other_insn.eq(0) - with m.Else(): - with m.If(self.rvfi_valid & (self.rvfi_order == insn_order) & ~self.trig): - m.d.sync += found_other_insn.eq(1) - with m.If(self.trig): - m.d.comb += Assume(self.rvfi_valid) - m.d.comb += Assume(insn_order == self.rvfi_order) - with m.If(self.check): - m.d.comb += Assert(~found_other_insn) - - return m diff --git a/insns/README.md b/insns/README.md deleted file mode 100644 index 034ebc4..0000000 --- a/insns/README.md +++ /dev/null @@ -1,28 +0,0 @@ -# RISC-V Instructions - -Refer to the table below for the instructions currently supported. At the time of writing, it covers the instructions in the RV32I base ISA except FENCE, ECALL and EBREAK, as well as the RV32M extension\*. - -| Instruction type | Instructions | -| --- | --- | -| U-type | lui, auipc | -| UJ-type | jal | -| I-type | jalr, lb, lh, lw, lbu, lhu, addi, slti, sltiu, xori, ori, andi | -| SB-type | beq, bne, blt, bge, bltu, bgeu | -| S-type | sb, sh, sw | -| I-type (shift variation) | slli, srli, srai | -| R-type | add, sub, sll, slt, sltu, xor, srl, sra, or, and, mul, mulh, mulhsu, mulhu, div, divu, rem, remu | - -\* Due to limitations with modern solvers, they are sometimes unable to verify assertions involving multiplication and/or division; therefore, the core under test is expected to implement alternative operations for the RV32M extensions for the purposes of formal verification only, replacing multiplication/division operations with addition/subtraction and XORing with selected bitmasks. - -## Caveats - -At the time of writing, the set of instructions supported in this port of riscv-formal is a mere subset of those supported in the original riscv-formal; for example, compressed instructions and 64-bit ISAs/extensions are not supported. Also note that the original riscv-formal contains tunable parameters that have been fixed to certain values in this translation: - -| Parameter from riscv-formal | Fixed value in riscv-formal-nmigen | -| --- | --- | -| `RISCV_FORMAL_ILEN` | 32 | -| `RISCV_FORMAL_XLEN` | 32 | -| `RISCV_FORMAL_CSR_MISA` | undefined | -| `RISCV_FORMAL_COMPRESSED` | undefined | -| `RISCV_FORMAL_ALIGNED_MEM` | undefined | -| `RISCV_FORMAL_ALTOPS` | defined | diff --git a/insns/insn.py b/insns/insn.py deleted file mode 100644 index 4588ff3..0000000 --- a/insns/insn.py +++ /dev/null @@ -1,51 +0,0 @@ -from nmigen import * - -class rvfi_insn(Elaboratable): - def __init__(self): - # Input ports - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(32) - self.rvfi_pc_rdata = Signal(32) - self.rvfi_rs1_rdata = Signal(32) - self.rvfi_rs2_rdata = Signal(32) - self.rvfi_mem_rdata = Signal(32) - - # Output ports - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(32) - self.spec_pc_wdata = Signal(32) - self.spec_mem_addr = Signal(32) - self.spec_mem_rmask = Signal(4) - self.spec_mem_wmask = Signal(4) - self.spec_mem_wdata = Signal(32) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - return m diff --git a/insns/insn_I.py b/insns/insn_I.py deleted file mode 100644 index 3d0c7e3..0000000 --- a/insns/insn_I.py +++ /dev/null @@ -1,38 +0,0 @@ -from insn import * - -class rvfi_insn_I(rvfi_insn): - def __init__(self): - super(rvfi_insn_I, self).__init__() - self.insn_padding = Signal(32) - self.insn_imm = Signal(32) - self.insn_rs1 = Signal(5) - self.insn_funct3 = Signal(3) - self.insn_rd = Signal(5) - self.insn_opcode = Signal(7) - self.misa_ok = Signal(1) - self.ialign16 = Signal(1) - def ports(self): - return super(rvfi_insn_I, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_I, self).elaborate(platform) - - # I-type instruction format - m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32) - m.d.comb += self.insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32])) - m.d.comb += self.insn_rs1.eq(self.rvfi_insn[15:20]) - m.d.comb += self.insn_funct3.eq(self.rvfi_insn[12:15]) - m.d.comb += self.insn_rd.eq(self.rvfi_insn[7:12]) - m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7]) - - m.d.comb += self.misa_ok.eq(1) - m.d.comb += self.ialign16.eq(0) - - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_trap.eq(~self.misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_I_shift.py b/insns/insn_I_shift.py deleted file mode 100644 index 45f2819..0000000 --- a/insns/insn_I_shift.py +++ /dev/null @@ -1,38 +0,0 @@ -from insn import * - -class rvfi_insn_I_shift(rvfi_insn): - def __init__(self): - super(rvfi_insn_I_shift, self).__init__() - self.insn_padding = Signal(32) - self.insn_funct6 = Signal(7) - self.insn_shamt = Signal(6) - self.insn_rs1 = Signal(5) - self.insn_funct3 = Signal(3) - self.insn_rd = Signal(5) - self.insn_opcode = Signal(7) - self.misa_ok = Signal(1) - def ports(self): - return super(rvfi_insn_I_shift, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_I_shift, self).elaborate(platform) - - # I-type instruction format (shift variation) - m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32) - m.d.comb += self.insn_funct6.eq(self.rvfi_insn[26:32]) - m.d.comb += self.insn_shamt.eq(self.rvfi_insn[20:26]) - m.d.comb += self.insn_rs1.eq(self.rvfi_insn[15:20]) - m.d.comb += self.insn_funct3.eq(self.rvfi_insn[12:15]) - m.d.comb += self.insn_rd.eq(self.rvfi_insn[7:12]) - m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7]) - - m.d.comb += self.misa_ok.eq(1) - - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_trap.eq(~self.misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_R.py b/insns/insn_R.py deleted file mode 100644 index 8fb73fb..0000000 --- a/insns/insn_R.py +++ /dev/null @@ -1,37 +0,0 @@ -from insn import * - -class rvfi_insn_R(rvfi_insn): - def __init__(self): - super(rvfi_insn_R, self).__init__() - self.insn_padding = Signal(32) - self.insn_funct7 = Signal(7) - self.insn_rs2 = Signal(5) - self.insn_rs1 = Signal(5) - self.insn_funct3 = Signal(3) - self.insn_rd = Signal(5) - self.insn_opcode = Signal(7) - self.misa_ok = Signal(1) - def ports(self): - return super(rvfi_insn_R, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_R, self).elaborate(platform) - - # R-type instruction format - m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32) - m.d.comb += self.insn_funct7.eq(self.rvfi_insn[25:32]) - m.d.comb += self.insn_rs2.eq(self.rvfi_insn[20:25]) - m.d.comb += self.insn_rs1.eq(self.rvfi_insn[15:20]) - m.d.comb += self.insn_funct3.eq(self.rvfi_insn[12:15]) - m.d.comb += self.insn_rd.eq(self.rvfi_insn[7:12]) - m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7]) - - m.d.comb += self.misa_ok.eq(1) - - # default assignments - m.d.comb += self.spec_trap.eq(~self.misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_S.py b/insns/insn_S.py deleted file mode 100644 index b757fbf..0000000 --- a/insns/insn_S.py +++ /dev/null @@ -1,32 +0,0 @@ -from insn import * -class rvfi_insn_S(rvfi_insn): - def __init__(self): - super(rvfi_insn_S, self).__init__() - self.insn_padding = Signal(32) - self.insn_imm = Signal(32) - self.insn_rs2 = Signal(5) - self.insn_rs1 = Signal(5) - self.insn_funct3 = Signal(3) - self.insn_opcode = Signal(7) - self.misa_ok = Signal(1) - def ports(self): - return super(rvfi_insn_S, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_S, self).elaborate(platform) - - # S-type instruction format - m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32) - m.d.comb += self.insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[7:12], self.rvfi_insn[25:32]))) - m.d.comb += self.insn_rs2.eq(self.rvfi_insn[20:25]) - m.d.comb += self.insn_rs1.eq(self.rvfi_insn[15:20]) - m.d.comb += self.insn_funct3.eq(self.rvfi_insn[12:15]) - m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7]) - - m.d.comb += self.misa_ok.eq(1) - - # default assignments - m.d.comb += self.spec_rd_addr.eq(0) - m.d.comb += self.spec_rd_wdata.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - - return m diff --git a/insns/insn_SB.py b/insns/insn_SB.py deleted file mode 100644 index 352f0c6..0000000 --- a/insns/insn_SB.py +++ /dev/null @@ -1,38 +0,0 @@ -from insn import * - -class rvfi_insn_SB(rvfi_insn): - def __init__(self): - super(rvfi_insn_SB, self).__init__() - self.insn_padding = Signal(32) - self.insn_imm = Signal(32) - self.insn_rs2 = Signal(5) - self.insn_rs1 = Signal(5) - self.insn_funct3 = Signal(3) - self.insn_opcode = Signal(7) - self.misa_ok = Signal(1) - self.ialign16 = Signal(1) - def ports(self): - return super(rvfi_insn_SB, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_SB, self).elaborate(platform) - - # SB-type instruction format - m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32) - m.d.comb += self.insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[8:12], self.rvfi_insn[25:31], self.rvfi_insn[7], self.rvfi_insn[31]) << 1)) - m.d.comb += self.insn_rs2.eq(self.rvfi_insn[20:25]) - m.d.comb += self.insn_rs1.eq(self.rvfi_insn[15:20]) - m.d.comb += self.insn_funct3.eq(self.rvfi_insn[12:15]) - m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7]) - - m.d.comb += self.misa_ok.eq(1) - m.d.comb += self.ialign16.eq(0) - - # default assignments - m.d.comb += self.spec_rd_addr.eq(0) - m.d.comb += self.spec_rd_wdata.eq(0) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_U.py b/insns/insn_U.py deleted file mode 100644 index aec6828..0000000 --- a/insns/insn_U.py +++ /dev/null @@ -1,33 +0,0 @@ -from insn import * - -class rvfi_insn_U(rvfi_insn): - def __init__(self): - super(rvfi_insn_U, self).__init__() - self.insn_padding = Signal(32) - self.insn_imm = Signal(32) - self.insn_rd = Signal(5) - self.insn_opcode = Signal(7) - self.misa_ok = Signal(1) - def ports(self): - return super(rvfi_insn_U, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_U, self).elaborate(platform) - - # U-type instruction format - m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32) - m.d.comb += self.insn_imm.eq(Value.as_signed(self.rvfi_insn[12:32] << 12)) - m.d.comb += self.insn_rd.eq(self.rvfi_insn[7:12]) - m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7]) - - m.d.comb += self.misa_ok.eq(1) - - # Default assignments - m.d.comb += self.spec_rs1_addr.eq(0) - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_trap.eq(~self.misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_UJ.py b/insns/insn_UJ.py deleted file mode 100644 index d5d2b8f..0000000 --- a/insns/insn_UJ.py +++ /dev/null @@ -1,34 +0,0 @@ -from insn import * - -class rvfi_insn_UJ(rvfi_insn): - def __init__(self): - super(rvfi_insn_UJ, self).__init__() - self.insn_padding = Signal(32) - self.insn_imm = Signal(32) - self.insn_rd = Signal(5) - self.insn_opcode = Signal(7) - self.misa_ok = Signal(1) - self.ialign16 = Signal(1) - def ports(self): - return super(rvfi_insn_UJ, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_UJ, self).elaborate(platform) - - # UJ-type instruction format - m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32) - m.d.comb += self.insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[21:31], self.rvfi_insn[20], self.rvfi_insn[12:20], self.rvfi_insn[31]) << 1)) - m.d.comb += self.insn_rd.eq(self.rvfi_insn[7:12]) - m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7]) - - m.d.comb += self.misa_ok.eq(1) - m.d.comb += self.ialign16.eq(0) - - # Default assignments - m.d.comb += self.spec_rs1_addr.eq(0) - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_add.py b/insns/insn_add.py deleted file mode 100644 index 58a9300..0000000 --- a/insns/insn_add.py +++ /dev/null @@ -1,21 +0,0 @@ -from insn_R import * - -class rvfi_insn_add(rvfi_insn_R): - def __init__(self): - super(rvfi_insn_add, self).__init__() - def ports(self): - return super(rvfi_insn_add, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_add, self).elaborate(platform) - - # ADD instruction - result = Signal(32) - m.d.comb += result.eq(self.rvfi_rs1_rdata + self.rvfi_rs2_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000000) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_addi.py b/insns/insn_addi.py deleted file mode 100644 index 70c7537..0000000 --- a/insns/insn_addi.py +++ /dev/null @@ -1,20 +0,0 @@ -from insn_I import * - -class rvfi_insn_addi(rvfi_insn_I): - def __init__(self): - super(rvfi_insn_addi, self).__init__() - def ports(self): - return super(rvfi_insn_addi, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_addi, self).elaborate(platform) - - # ADDI instruction - result = Signal(32) - m.d.comb += result.eq(self.rvfi_rs1_rdata + self.insn_imm) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b0010011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_and.py b/insns/insn_and.py deleted file mode 100644 index 4cf5a52..0000000 --- a/insns/insn_and.py +++ /dev/null @@ -1,21 +0,0 @@ -from insn_R import * - -class rvfi_insn_and(rvfi_insn_R): - def __init__(self): - super(rvfi_insn_and, self).__init__() - def ports(self): - return super(rvfi_insn_and, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_and, self).elaborate(platform) - - # AND instruction - result = Signal(32) - m.d.comb += result.eq(self.rvfi_rs1_rdata & self.rvfi_rs2_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000000) & (self.insn_funct3 == 0b111) & (self.insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_andi.py b/insns/insn_andi.py deleted file mode 100644 index 6d4c0fa..0000000 --- a/insns/insn_andi.py +++ /dev/null @@ -1,20 +0,0 @@ -from insn_I import * - -class rvfi_insn_andi(rvfi_insn_I): - def __init__(self): - super(rvfi_insn_andi, self).__init__() - def ports(self): - return super(rvfi_insn_andi, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_andi, self).elaborate(platform) - - # ANDI instruction - result = Signal(32) - m.d.comb += result.eq(self.rvfi_rs1_rdata & self.insn_imm) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b111) & (self.insn_opcode == 0b0010011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_auipc.py b/insns/insn_auipc.py deleted file mode 100644 index 07a9f63..0000000 --- a/insns/insn_auipc.py +++ /dev/null @@ -1,17 +0,0 @@ -from insn_U import * - -class rvfi_insn_auipc(rvfi_insn_U): - def __init__(self): - super(rvfi_insn_auipc, self).__init__() - def ports(self): - return super(rvfi_insn_auipc, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_auipc, self).elaborate(platform) - - # AUIPC instruction - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_opcode == 0b0010111)) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_pc_rdata + self.insn_imm, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_beq.py b/insns/insn_beq.py deleted file mode 100644 index 582a331..0000000 --- a/insns/insn_beq.py +++ /dev/null @@ -1,22 +0,0 @@ -from insn_SB import * - -class rvfi_insn_beq(rvfi_insn_SB): - def __init__(self): - super(rvfi_insn_beq, self).__init__() - def ports(self): - return super(rvfi_insn_beq, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_beq, self).elaborate(platform) - - # BEQ instruction - cond = Signal(1) - m.d.comb += cond.eq(self.rvfi_rs1_rdata == self.rvfi_rs2_rdata) - next_pc = Signal(32) - m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b1100011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) - - return m diff --git a/insns/insn_bge.py b/insns/insn_bge.py deleted file mode 100644 index 3309baa..0000000 --- a/insns/insn_bge.py +++ /dev/null @@ -1,22 +0,0 @@ -from insn_SB import * - -class rvfi_insn_bge(rvfi_insn_SB): - def __init__(self): - super(rvfi_insn_bge, self).__init__() - def ports(self): - return super(rvfi_insn_bge, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_bge, self).elaborate(platform) - - # BGE instruction - cond = Signal(1) - m.d.comb += cond.eq(Value.as_signed(self.rvfi_rs1_rdata) >= Value.as_signed(self.rvfi_rs2_rdata)) - next_pc = Signal(32) - m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b101) & (self.insn_opcode == 0b1100011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) - - return m diff --git a/insns/insn_bgeu.py b/insns/insn_bgeu.py deleted file mode 100644 index 049be95..0000000 --- a/insns/insn_bgeu.py +++ /dev/null @@ -1,22 +0,0 @@ -from insn_SB import * - -class rvfi_insn_bgeu(rvfi_insn_SB): - def __init__(self): - super(rvfi_insn_bgeu, self).__init__() - def ports(self): - return super(rvfi_insn_bgeu, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_bgeu, self).elaborate(platform) - - # BGEU instruction - cond = Signal(1) - m.d.comb += cond.eq(self.rvfi_rs1_rdata >= self.rvfi_rs2_rdata) - next_pc = Signal(32) - m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b111) & (self.insn_opcode == 0b1100011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) - - return m diff --git a/insns/insn_blt.py b/insns/insn_blt.py deleted file mode 100644 index 471f032..0000000 --- a/insns/insn_blt.py +++ /dev/null @@ -1,22 +0,0 @@ -from insn_SB import * - -class rvfi_insn_blt(rvfi_insn_SB): - def __init__(self): - super(rvfi_insn_blt, self).__init__() - def ports(self): - return super(rvfi_insn_blt, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_blt, self).elaborate(platform) - - # BLT instruction - cond = Signal(1) - m.d.comb += cond.eq(Value.as_signed(self.rvfi_rs1_rdata) < Value.as_signed(self.rvfi_rs2_rdata)) - next_pc = Signal(32) - m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b100) & (self.insn_opcode == 0b1100011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) - - return m diff --git a/insns/insn_bltu.py b/insns/insn_bltu.py deleted file mode 100644 index 16dd557..0000000 --- a/insns/insn_bltu.py +++ /dev/null @@ -1,22 +0,0 @@ -from insn_SB import * - -class rvfi_insn_bltu(rvfi_insn_SB): - def __init__(self): - super(rvfi_insn_bltu, self).__init__() - def ports(self): - return super(rvfi_insn_bltu, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_bltu, self).elaborate(platform) - - # BLTU instruction - cond = Signal(1) - m.d.comb += cond.eq(self.rvfi_rs1_rdata < self.rvfi_rs2_rdata) - next_pc = Signal(32) - m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b110) & (self.insn_opcode == 0b1100011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) - - return m diff --git a/insns/insn_bne.py b/insns/insn_bne.py deleted file mode 100644 index 6c273f0..0000000 --- a/insns/insn_bne.py +++ /dev/null @@ -1,22 +0,0 @@ -from insn_SB import * - -class rvfi_insn_bne(rvfi_insn_SB): - def __init__(self): - super(rvfi_insn_bne, self).__init__() - def ports(self): - return super(rvfi_insn_bne, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_bne, self).elaborate(platform) - - # BNE instruction - cond = Signal(1) - m.d.comb += cond.eq(self.rvfi_rs1_rdata != self.rvfi_rs2_rdata) - next_pc = Signal(32) - m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b001) & (self.insn_opcode == 0b1100011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) - - return m diff --git a/insns/insn_div.py b/insns/insn_div.py deleted file mode 100644 index 2cd2523..0000000 --- a/insns/insn_div.py +++ /dev/null @@ -1,23 +0,0 @@ -from insn_R import * - -class rvfi_insn_div(rvfi_insn_R): - def __init__(self): - super(rvfi_insn_div, self).__init__() - def ports(self): - return super(rvfi_insn_div, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_div, self).elaborate(platform) - - # DIV instruction - altops_bitmask = Signal(32) - m.d.comb += altops_bitmask.eq(0x29bbf66f7f8529ec) - result = Signal(32) - m.d.comb += result.eq((self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ altops_bitmask) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000001) & (self.insn_funct3 == 0b100) & (self.insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_divu.py b/insns/insn_divu.py deleted file mode 100644 index 454eb00..0000000 --- a/insns/insn_divu.py +++ /dev/null @@ -1,23 +0,0 @@ -from insn_R import * - -class rvfi_insn_divu(rvfi_insn_R): - def __init__(self): - super(rvfi_insn_divu, self).__init__() - def ports(self): - return super(rvfi_insn_divu, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_divu, self).elaborate(platform) - - # DIVU instruction - altops_bitmask = Signal(32) - m.d.comb += altops_bitmask.eq(0x8c629acb10e8fd70) - result = Signal(32) - m.d.comb += result.eq((self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ altops_bitmask) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000001) & (self.insn_funct3 == 0b101) & (self.insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_jal.py b/insns/insn_jal.py deleted file mode 100644 index c95cb14..0000000 --- a/insns/insn_jal.py +++ /dev/null @@ -1,20 +0,0 @@ -from insn_UJ import * - -class rvfi_insn_jal(rvfi_insn_UJ): - def __init__(self): - super(rvfi_insn_jal, self).__init__() - def ports(self): - return super(rvfi_insn_jal, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_jal, self).elaborate(platform) - - # JAL instruction - next_pc = Signal(32) - m.d.comb += next_pc.eq(self.rvfi_pc_rdata + self.insn_imm) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_opcode == 0b1101111)) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_pc_rdata + 4, 0)) - m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) - - return m diff --git a/insns/insn_jalr.py b/insns/insn_jalr.py deleted file mode 100644 index 56dddd0..0000000 --- a/insns/insn_jalr.py +++ /dev/null @@ -1,21 +0,0 @@ -from insn_I import * - -class rvfi_insn_jalr(rvfi_insn_I): - def __init__(self): - super(rvfi_insn_jalr, self).__init__() - def ports(self): - return super(rvfi_insn_jalr, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_jalr, self).elaborate(platform) - - # JALR instruction - next_pc = Signal(32) - m.d.comb += next_pc.eq((self.rvfi_rs1_rdata + self.insn_imm) & ~1) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b1100111)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_pc_rdata + 4, 0)) - m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) - - return m diff --git a/insns/insn_lb.py b/insns/insn_lb.py deleted file mode 100644 index 4c3fba6..0000000 --- a/insns/insn_lb.py +++ /dev/null @@ -1,25 +0,0 @@ -from insn_I import * - -class rvfi_insn_lb(rvfi_insn_I): - def __init__(self): - super(rvfi_insn_lb, self).__init__() - def ports(self): - return super(rvfi_insn_lb, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_lb, self).elaborate(platform) - - # LB instruction - addr = Signal(32) - m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm) - result = Signal(8) - m.d.comb += result.eq(self.rvfi_mem_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b0000011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_mem_addr.eq(addr) - m.d.comb += self.spec_mem_rmask.eq((1 << 1) - 1) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(result), 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - m.d.comb += self.spec_trap.eq(~self.misa_ok) - - return m diff --git a/insns/insn_lbu.py b/insns/insn_lbu.py deleted file mode 100644 index 3961c99..0000000 --- a/insns/insn_lbu.py +++ /dev/null @@ -1,25 +0,0 @@ -from insn_I import * - -class rvfi_insn_lbu(rvfi_insn_I): - def __init__(self): - super(rvfi_insn_lbu, self).__init__() - def ports(self): - return super(rvfi_insn_lbu, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_lbu, self).elaborate(platform) - - # LBU instruction - addr = Signal(32) - m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm) - result = Signal(8) - m.d.comb += result.eq(self.rvfi_mem_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (self.insn_funct3 == 0b100) & (self.insn_opcode == 0b0000011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_mem_addr.eq(addr) - m.d.comb += self.spec_mem_rmask.eq((1 << 1) - 1) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - m.d.comb += self.spec_trap.eq(~self.misa_ok) - - return m diff --git a/insns/insn_lh.py b/insns/insn_lh.py deleted file mode 100644 index 34c7f93..0000000 --- a/insns/insn_lh.py +++ /dev/null @@ -1,25 +0,0 @@ -from insn_I import * - -class rvfi_insn_lh(rvfi_insn_I): - def __init__(self): - super(rvfi_insn_lh, self).__init__() - def ports(self): - return super(rvfi_insn_lh, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_lh, self).elaborate(platform) - - # LH instruction - addr = Signal(32) - m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm) - result = Signal(16) - m.d.comb += result.eq(self.rvfi_mem_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (self.insn_funct3 == 0b001) & (self.insn_opcode == 0b0000011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_mem_addr.eq(addr) - m.d.comb += self.spec_mem_rmask.eq((1 << 2) - 1) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(result), 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - m.d.comb += self.spec_trap.eq(~self.misa_ok) - - return m diff --git a/insns/insn_lhu.py b/insns/insn_lhu.py deleted file mode 100644 index b050668..0000000 --- a/insns/insn_lhu.py +++ /dev/null @@ -1,25 +0,0 @@ -from insn_I import * - -class rvfi_insn_lhu(rvfi_insn_I): - def __init__(self): - super(rvfi_insn_lhu, self).__init__() - def ports(self): - return super(rvfi_insn_lhu, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_lhu, self).elaborate(platform) - - # LHU instruction - addr = Signal(32) - m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm) - result = Signal(16) - m.d.comb += result.eq(self.rvfi_mem_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (self.insn_funct3 == 0b101) & (self.insn_opcode == 0b0000011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_mem_addr.eq(addr) - m.d.comb += self.spec_mem_rmask.eq((1 << 2) - 1) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - m.d.comb += self.spec_trap.eq(~self.misa_ok) - - return m diff --git a/insns/insn_lui.py b/insns/insn_lui.py deleted file mode 100644 index 42aa764..0000000 --- a/insns/insn_lui.py +++ /dev/null @@ -1,17 +0,0 @@ -from insn_U import * - -class rvfi_insn_lui(rvfi_insn_U): - def __init__(self): - super(rvfi_insn_lui, self).__init__() - def ports(self): - return super(rvfi_insn_lui, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_lui, self).elaborate(platform) - - # LUI instruction - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_opcode == 0b0110111)) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.insn_imm, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_lw.py b/insns/insn_lw.py deleted file mode 100644 index 5e956e9..0000000 --- a/insns/insn_lw.py +++ /dev/null @@ -1,25 +0,0 @@ -from insn_I import * - -class rvfi_insn_lw(rvfi_insn_I): - def __init__(self): - super(rvfi_insn_lw, self).__init__() - def ports(self): - return super(rvfi_insn_lw, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_lw, self).elaborate(platform) - - # LW instruction - addr = Signal(32) - m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm) - result = Signal(32) - m.d.comb += result.eq(self.rvfi_mem_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (self.insn_funct3 == 0b010) & (self.insn_opcode == 0b0000011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_mem_addr.eq(addr) - m.d.comb += self.spec_mem_rmask.eq((1 << 4) - 1) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(result), 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - m.d.comb += self.spec_trap.eq(~self.misa_ok) - - return m diff --git a/insns/insn_mul.py b/insns/insn_mul.py deleted file mode 100644 index 5f250b1..0000000 --- a/insns/insn_mul.py +++ /dev/null @@ -1,23 +0,0 @@ -from insn_R import * - -class rvfi_insn_mul(rvfi_insn_R): - def __init__(self): - super(rvfi_insn_mul, self).__init__() - def ports(self): - return super(rvfi_insn_mul, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_mul, self).elaborate(platform) - - # MUL instruction - altops_bitmask = Signal(32) - m.d.comb += altops_bitmask.eq(0x2cdf52a55876063e) - result = Signal(32) - m.d.comb += result.eq((self.rvfi_rs1_rdata + self.rvfi_rs2_rdata) ^ altops_bitmask) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000001) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_mulh.py b/insns/insn_mulh.py deleted file mode 100644 index 81010c2..0000000 --- a/insns/insn_mulh.py +++ /dev/null @@ -1,23 +0,0 @@ -from insn_R import * - -class rvfi_insn_mulh(rvfi_insn_R): - def __init__(self): - super(rvfi_insn_mulh, self).__init__() - def ports(self): - return super(rvfi_insn_mulh, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_mulh, self).elaborate(platform) - - # MULH instruction - altops_bitmask = Signal(32) - m.d.comb += altops_bitmask.eq(0x15d01651f6583fb7) - result = Signal(32) - m.d.comb += result.eq((self.rvfi_rs1_rdata + self.rvfi_rs2_rdata) ^ altops_bitmask) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000001) & (self.insn_funct3 == 0b001) & (self.insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_mulhsu.py b/insns/insn_mulhsu.py deleted file mode 100644 index 18857d8..0000000 --- a/insns/insn_mulhsu.py +++ /dev/null @@ -1,23 +0,0 @@ -from insn_R import * - -class rvfi_insn_mulhsu(rvfi_insn_R): - def __init__(self): - super(rvfi_insn_mulhsu, self).__init__() - def ports(self): - return super(rvfi_insn_mulhsu, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_mulhsu, self).elaborate(platform) - - # MULHSU instruction - altops_bitmask = Signal(32) - m.d.comb += altops_bitmask.eq(0xea3969edecfbe137) - result = Signal(32) - m.d.comb += result.eq((self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ altops_bitmask) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000001) & (self.insn_funct3 == 0b010) & (self.insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_mulhu.py b/insns/insn_mulhu.py deleted file mode 100644 index efeaed4..0000000 --- a/insns/insn_mulhu.py +++ /dev/null @@ -1,23 +0,0 @@ -from insn_R import * - -class rvfi_insn_mulhu(rvfi_insn_R): - def __init__(self): - super(rvfi_insn_mulhu, self).__init__() - def ports(self): - return super(rvfi_insn_mulhu, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_mulhu, self).elaborate(platform) - - # MULHU instruction - altops_bitmask = Signal(32) - m.d.comb += altops_bitmask.eq(0xd13db50d949ce5e8) - result = Signal(32) - m.d.comb += result.eq((self.rvfi_rs1_rdata + self.rvfi_rs2_rdata) ^ altops_bitmask) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000001) & (self.insn_funct3 == 0b011) & (self.insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_or.py b/insns/insn_or.py deleted file mode 100644 index ad09251..0000000 --- a/insns/insn_or.py +++ /dev/null @@ -1,21 +0,0 @@ -from insn_R import * - -class rvfi_insn_or(rvfi_insn_R): - def __init__(self): - super(rvfi_insn_or, self).__init__() - def ports(self): - return super(rvfi_insn_or, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_or, self).elaborate(platform) - - # OR instruction - result = Signal(32) - m.d.comb += result.eq(self.rvfi_rs1_rdata | self.rvfi_rs2_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000000) & (self.insn_funct3 == 0b110) & (self.insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_ori.py b/insns/insn_ori.py deleted file mode 100644 index 3d4bb82..0000000 --- a/insns/insn_ori.py +++ /dev/null @@ -1,20 +0,0 @@ -from insn_I import * - -class rvfi_insn_ori(rvfi_insn_I): - def __init__(self): - super(rvfi_insn_ori, self).__init__() - def ports(self): - return super(rvfi_insn_ori, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_ori, self).elaborate(platform) - - # ORI instruction - result = Signal(32) - m.d.comb += result.eq(self.rvfi_rs1_rdata | self.insn_imm) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b110) & (self.insn_opcode == 0b0010011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_rem.py b/insns/insn_rem.py deleted file mode 100644 index b2efb57..0000000 --- a/insns/insn_rem.py +++ /dev/null @@ -1,23 +0,0 @@ -from insn_R import * - -class rvfi_insn_rem(rvfi_insn_R): - def __init__(self): - super(rvfi_insn_rem, self).__init__() - def ports(self): - return super(rvfi_insn_rem, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_rem, self).elaborate(platform) - - # REM instruction - altops_bitmask = Signal(32) - m.d.comb += altops_bitmask.eq(0xf5b7d8538da68fa5) - result = Signal(32) - m.d.comb += result.eq((self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ altops_bitmask) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000001) & (self.insn_funct3 == 0b110) & (self.insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_remu.py b/insns/insn_remu.py deleted file mode 100644 index eb50e4d..0000000 --- a/insns/insn_remu.py +++ /dev/null @@ -1,23 +0,0 @@ -from insn_R import * - -class rvfi_insn_remu(rvfi_insn_R): - def __init__(self): - super(rvfi_insn_remu, self).__init__() - def ports(self): - return super(rvfi_insn_remu, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_remu, self).elaborate(platform) - - # REMU instruction - altops_bitmask = Signal(32) - m.d.comb += altops_bitmask.eq(0xbc4402413138d0e1) - result = Signal(32) - m.d.comb += result.eq((self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ altops_bitmask) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000001) & (self.insn_funct3 == 0b111) & (self.insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_sb.py b/insns/insn_sb.py deleted file mode 100644 index a423dc4..0000000 --- a/insns/insn_sb.py +++ /dev/null @@ -1,23 +0,0 @@ -from insn_S import * - -class rvfi_insn_sb(rvfi_insn_S): - def __init__(self): - super(rvfi_insn_sb, self).__init__() - def ports(self): - return super(rvfi_insn_sb, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_sb, self).elaborate(platform) - - # SB instruction - addr = Signal(32) - m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b0100011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_mem_addr.eq(addr) - m.d.comb += self.spec_mem_wmask.eq((1 << 1) - 1) - m.d.comb += self.spec_mem_wdata.eq(self.rvfi_rs2_rdata) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - m.d.comb += self.spec_trap.eq(~self.misa_ok) - - return m diff --git a/insns/insn_sh.py b/insns/insn_sh.py deleted file mode 100644 index 1a246c5..0000000 --- a/insns/insn_sh.py +++ /dev/null @@ -1,23 +0,0 @@ -from insn_S import * - -class rvfi_insn_sh(rvfi_insn_S): - def __init__(self): - super(rvfi_insn_sh, self).__init__() - def ports(self): - return super(rvfi_insn_sh, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_sh, self).elaborate(platform) - - # SH instruction - addr = Signal(32) - m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b001) & (self.insn_opcode == 0b0100011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_mem_addr.eq(addr) - m.d.comb += self.spec_mem_wmask.eq((1 << 2) - 1) - m.d.comb += self.spec_mem_wdata.eq(self.rvfi_rs2_rdata) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - m.d.comb += self.spec_trap.eq(~self.misa_ok) - - return m diff --git a/insns/insn_sll.py b/insns/insn_sll.py deleted file mode 100644 index 5158983..0000000 --- a/insns/insn_sll.py +++ /dev/null @@ -1,23 +0,0 @@ -from insn_R import * - -class rvfi_insn_sll(rvfi_insn_R): - def __init__(self): - super(rvfi_insn_sll, self).__init__() - def ports(self): - return super(rvfi_insn_sll, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_sll, self).elaborate(platform) - - # SLL instruction - shamt = Signal(6) - m.d.comb += shamt.eq(self.rvfi_rs2_rdata[:5]) - result = Signal(32) - m.d.comb += result.eq(self.rvfi_rs1_rdata << shamt) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000000) & (self.insn_funct3 == 0b001) & (self.insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_slli.py b/insns/insn_slli.py deleted file mode 100644 index 6d18539..0000000 --- a/insns/insn_slli.py +++ /dev/null @@ -1,20 +0,0 @@ -from insn_I_shift import * - -class rvfi_insn_slli(rvfi_insn_I_shift): - def __init__(self): - super(rvfi_insn_slli, self).__init__() - def ports(self): - return super(rvfi_insn_slli, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_slli, self).elaborate(platform) - - # SLLI instruction - result = Signal(32) - m.d.comb += result.eq(self.rvfi_rs1_rdata << self.insn_shamt) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct6 == 0b000000) & (self.insn_funct3 == 0b001) & (self.insn_opcode == 0b0010011) & (~self.insn_shamt[5])) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_slt.py b/insns/insn_slt.py deleted file mode 100644 index 667255c..0000000 --- a/insns/insn_slt.py +++ /dev/null @@ -1,21 +0,0 @@ -from insn_R import * - -class rvfi_insn_slt(rvfi_insn_R): - def __init__(self): - super(rvfi_insn_slt, self).__init__() - def ports(self): - return super(rvfi_insn_slt, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_slt, self).elaborate(platform) - - # SLT instruction - result = Signal(32) - m.d.comb += result.eq(Value.as_signed(self.rvfi_rs1_rdata) < Value.as_signed(self.rvfi_rs2_rdata)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000000) & (self.insn_funct3 == 0b010) & (self.insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_slti.py b/insns/insn_slti.py deleted file mode 100644 index a84f502..0000000 --- a/insns/insn_slti.py +++ /dev/null @@ -1,20 +0,0 @@ -from insn_I import * - -class rvfi_insn_slti(rvfi_insn_I): - def __init__(self): - super(rvfi_insn_slti, self).__init__() - def ports(self): - return super(rvfi_insn_slti, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_slti, self).elaborate(platform) - - # SLTI instruction - result = Signal(32) - m.d.comb += result.eq(Value.as_signed(self.rvfi_rs1_rdata) < Value.as_signed(self.insn_imm)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b010) & (self.insn_opcode == 0b0010011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_sltiu.py b/insns/insn_sltiu.py deleted file mode 100644 index 717dfef..0000000 --- a/insns/insn_sltiu.py +++ /dev/null @@ -1,20 +0,0 @@ -from insn_I import * - -class rvfi_insn_sltiu(rvfi_insn_I): - def __init__(self): - super(rvfi_insn_sltiu, self).__init__() - def ports(self): - return super(rvfi_insn_sltiu, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_sltiu, self).elaborate(platform) - - # SLTIU instruction - result = Signal(32) - m.d.comb += result.eq(self.rvfi_rs1_rdata < self.insn_imm) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b011) & (self.insn_opcode == 0b0010011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_sltu.py b/insns/insn_sltu.py deleted file mode 100644 index 4f45aa4..0000000 --- a/insns/insn_sltu.py +++ /dev/null @@ -1,21 +0,0 @@ -from insn_R import * - -class rvfi_insn_sltu(rvfi_insn_R): - def __init__(self): - super(rvfi_insn_sltu, self).__init__() - def ports(self): - return super(rvfi_insn_sltu, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_sltu, self).elaborate(platform) - - # SLTU instruction - result = Signal(32) - m.d.comb += result.eq(self.rvfi_rs1_rdata < self.rvfi_rs2_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000000) & (self.insn_funct3 == 0b011) & (self.insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_sra.py b/insns/insn_sra.py deleted file mode 100644 index c3075d9..0000000 --- a/insns/insn_sra.py +++ /dev/null @@ -1,23 +0,0 @@ -from insn_R import * - -class rvfi_insn_sra(rvfi_insn_R): - def __init__(self): - super(rvfi_insn_sra, self).__init__() - def ports(self): - return super(rvfi_insn_sra, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_sra, self).elaborate(platform) - - # SRA instruction - shamt = Signal(6) - m.d.comb += shamt.eq(self.rvfi_rs2_rdata[:5]) - result = Signal(32) - m.d.comb += result.eq((self.rvfi_rs1_rdata >> shamt) | (-(self.rvfi_rs1_rdata < 0) << (32 - shamt))) # https://stackoverflow.com/a/25207042 - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0100000) & (self.insn_funct3 == 0b101) & (self.insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_srai.py b/insns/insn_srai.py deleted file mode 100644 index ad17861..0000000 --- a/insns/insn_srai.py +++ /dev/null @@ -1,20 +0,0 @@ -from insn_I_shift import * - -class rvfi_insn_srai(rvfi_insn_I_shift): - def __init__(self): - super(rvfi_insn_srai, self).__init__() - def ports(self): - return super(rvfi_insn_srai, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_srai, self).elaborate(platform) - - # SRAI instruction - result = Signal(32) - m.d.comb += result.eq((self.rvfi_rs1_rdata >> self.insn_shamt) | (-(self.rvfi_rs1_rdata < 0) << (32 - self.insn_shamt))) # https://stackoverflow.com/a/25207042 - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct6 == 0b010000) & (self.insn_funct3 == 0b101) & (self.insn_opcode == 0b0010011) & (~self.insn_shamt[5])) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_srl.py b/insns/insn_srl.py deleted file mode 100644 index a03f8f1..0000000 --- a/insns/insn_srl.py +++ /dev/null @@ -1,23 +0,0 @@ -from insn_R import * - -class rvfi_insn_srl(rvfi_insn_R): - def __init__(self): - super(rvfi_insn_srl, self).__init__() - def ports(self): - return super(rvfi_insn_srl, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_srl, self).elaborate(platform) - - # SRL instruction - shamt = Signal(6) - m.d.comb += shamt.eq(self.rvfi_rs2_rdata[:5]) - result = Signal(32) - m.d.comb += result.eq(self.rvfi_rs1_rdata >> shamt) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000000) & (self.insn_funct3 == 0b101) & (self.insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_srli.py b/insns/insn_srli.py deleted file mode 100644 index f239860..0000000 --- a/insns/insn_srli.py +++ /dev/null @@ -1,20 +0,0 @@ -from insn_I_shift import * - -class rvfi_insn_srli(rvfi_insn_I_shift): - def __init__(self): - super(rvfi_insn_srli, self).__init__() - def ports(self): - return super(rvfi_insn_srli, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_srli, self).elaborate(platform) - - # SRLI instruction - result = Signal(32) - m.d.comb += result.eq(self.rvfi_rs1_rdata >> self.insn_shamt) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct6 == 0b000000) & (self.insn_funct3 == 0b101) & (self.insn_opcode == 0b0010011) & (~self.insn_shamt[5])) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_sub.py b/insns/insn_sub.py deleted file mode 100644 index 20c394a..0000000 --- a/insns/insn_sub.py +++ /dev/null @@ -1,21 +0,0 @@ -from insn_R import * - -class rvfi_insn_sub(rvfi_insn_R): - def __init__(self): - super(rvfi_insn_sub, self).__init__() - def ports(self): - return super(rvfi_insn_sub, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_sub, self).elaborate(platform) - - # SUB instruction - result = Signal(32) - m.d.comb += result.eq(self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0100000) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_sw.py b/insns/insn_sw.py deleted file mode 100644 index cb02983..0000000 --- a/insns/insn_sw.py +++ /dev/null @@ -1,23 +0,0 @@ -from insn_S import * - -class rvfi_insn_sw(rvfi_insn_S): - def __init__(self): - super(rvfi_insn_sw, self).__init__() - def ports(self): - return super(rvfi_insn_sw, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_sw, self).elaborate(platform) - - # SW instruction - addr = Signal(32) - m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b010) & (self.insn_opcode == 0b0100011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_mem_addr.eq(addr) - m.d.comb += self.spec_mem_wmask.eq((1 << 4) - 1) - m.d.comb += self.spec_mem_wdata.eq(self.rvfi_rs2_rdata) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - m.d.comb += self.spec_trap.eq(~self.misa_ok) - - return m diff --git a/insns/insn_types.md b/insns/insn_types.md deleted file mode 100644 index 5228a1f..0000000 --- a/insns/insn_types.md +++ /dev/null @@ -1,11 +0,0 @@ -# RV32IM Instruction Types - -| Instruction type | Instructions | -| --- | --- | -| U-type | lui, auipc | -| UJ-type | jal | -| I-type | jalr, lb, lh, lw, lbu, lhu, addi, slti, sltiu, xori, ori, andi | -| SB-type | beq, bne, blt, bge, bltu, bgeu | -| S-type | sb, sh, sw | -| I-type (shift variation) | slli, srli, srai | -| R-type | add, sub, sll, slt, sltu, xor, srl, sra, or, and, mul, mulh, mulhsu, mulhu, div, divu, rem, remu | diff --git a/insns/insn_xor.py b/insns/insn_xor.py deleted file mode 100644 index c332429..0000000 --- a/insns/insn_xor.py +++ /dev/null @@ -1,21 +0,0 @@ -from insn_R import * - -class rvfi_insn_xor(rvfi_insn_R): - def __init__(self): - super(rvfi_insn_xor, self).__init__() - def ports(self): - return super(rvfi_insn_xor, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_xor, self).elaborate(platform) - - # XOR instruction - result = Signal(32) - m.d.comb += result.eq(self.rvfi_rs1_rdata ^ self.rvfi_rs2_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000000) & (self.insn_funct3 == 0b100) & (self.insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/insn_xori.py b/insns/insn_xori.py deleted file mode 100644 index 647067d..0000000 --- a/insns/insn_xori.py +++ /dev/null @@ -1,20 +0,0 @@ -from insn_I import * - -class rvfi_insn_xori(rvfi_insn_I): - def __init__(self): - super(rvfi_insn_xori, self).__init__() - def ports(self): - return super(rvfi_insn_xori, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_xori, self).elaborate(platform) - - # XORI instruction - result = Signal(32) - m.d.comb += result.eq(self.rvfi_rs1_rdata ^ self.insn_imm) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b100) & (self.insn_opcode == 0b0010011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - return m diff --git a/insns/isa_rv32i.py b/insns/isa_rv32i.py deleted file mode 100644 index 3ef25e4..0000000 --- a/insns/isa_rv32i.py +++ /dev/null @@ -1,1211 +0,0 @@ -# Generated by isa_rv32i_gen.py -from nmigen import * -from insn_lui import * -from insn_auipc import * -from insn_jal import * -from insn_jalr import * -from insn_beq import * -from insn_bne import * -from insn_blt import * -from insn_bge import * -from insn_bltu import * -from insn_bgeu import * -from insn_lb import * -from insn_lh import * -from insn_lw import * -from insn_lbu import * -from insn_lhu import * -from insn_sb import * -from insn_sh import * -from insn_sw import * -from insn_addi import * -from insn_slti import * -from insn_sltiu import * -from insn_xori import * -from insn_ori import * -from insn_andi import * -from insn_slli import * -from insn_srli import * -from insn_srai import * -from insn_add import * -from insn_sub import * -from insn_sll import * -from insn_slt import * -from insn_sltu import * -from insn_xor import * -from insn_srl import * -from insn_sra import * -from insn_or import * -from insn_and import * - -class rvfi_isa_rv32i(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - spec_insn_lui_valid = Signal(1) - spec_insn_lui_trap = Signal(1) - spec_insn_lui_rs1_addr = Signal(5) - spec_insn_lui_rs2_addr = Signal(5) - spec_insn_lui_rd_addr = Signal(5) - spec_insn_lui_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lui_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lui_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lui_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lui_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lui_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_lui = insn_lui = rvfi_insn_lui() - m.d.comb += insn_lui.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_lui.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_lui.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_lui.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_lui.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_lui.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_lui_valid.eq(insn_lui.spec_valid) - m.d.comb += spec_insn_lui_trap.eq(insn_lui.spec_trap) - m.d.comb += spec_insn_lui_rs1_addr.eq(insn_lui.spec_rs1_addr) - m.d.comb += spec_insn_lui_rs2_addr.eq(insn_lui.spec_rs2_addr) - m.d.comb += spec_insn_lui_rd_addr.eq(insn_lui.spec_rd_addr) - m.d.comb += spec_insn_lui_rd_wdata.eq(insn_lui.spec_rd_wdata) - m.d.comb += spec_insn_lui_pc_wdata.eq(insn_lui.spec_pc_wdata) - m.d.comb += spec_insn_lui_mem_addr.eq(insn_lui.spec_mem_addr) - m.d.comb += spec_insn_lui_mem_rmask.eq(insn_lui.spec_mem_rmask) - m.d.comb += spec_insn_lui_mem_wmask.eq(insn_lui.spec_mem_wmask) - m.d.comb += spec_insn_lui_mem_wdata.eq(insn_lui.spec_mem_wdata) - - spec_insn_auipc_valid = Signal(1) - spec_insn_auipc_trap = Signal(1) - spec_insn_auipc_rs1_addr = Signal(5) - spec_insn_auipc_rs2_addr = Signal(5) - spec_insn_auipc_rd_addr = Signal(5) - spec_insn_auipc_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_auipc_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_auipc_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_auipc_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_auipc_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_auipc_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_auipc = insn_auipc = rvfi_insn_auipc() - m.d.comb += insn_auipc.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_auipc.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_auipc.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_auipc.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_auipc.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_auipc.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_auipc_valid.eq(insn_auipc.spec_valid) - m.d.comb += spec_insn_auipc_trap.eq(insn_auipc.spec_trap) - m.d.comb += spec_insn_auipc_rs1_addr.eq(insn_auipc.spec_rs1_addr) - m.d.comb += spec_insn_auipc_rs2_addr.eq(insn_auipc.spec_rs2_addr) - m.d.comb += spec_insn_auipc_rd_addr.eq(insn_auipc.spec_rd_addr) - m.d.comb += spec_insn_auipc_rd_wdata.eq(insn_auipc.spec_rd_wdata) - m.d.comb += spec_insn_auipc_pc_wdata.eq(insn_auipc.spec_pc_wdata) - m.d.comb += spec_insn_auipc_mem_addr.eq(insn_auipc.spec_mem_addr) - m.d.comb += spec_insn_auipc_mem_rmask.eq(insn_auipc.spec_mem_rmask) - m.d.comb += spec_insn_auipc_mem_wmask.eq(insn_auipc.spec_mem_wmask) - m.d.comb += spec_insn_auipc_mem_wdata.eq(insn_auipc.spec_mem_wdata) - - spec_insn_jal_valid = Signal(1) - spec_insn_jal_trap = Signal(1) - spec_insn_jal_rs1_addr = Signal(5) - spec_insn_jal_rs2_addr = Signal(5) - spec_insn_jal_rd_addr = Signal(5) - spec_insn_jal_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_jal_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_jal_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_jal_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_jal_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_jal_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_jal = insn_jal = rvfi_insn_jal() - m.d.comb += insn_jal.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_jal.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_jal.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_jal.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_jal.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_jal.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_jal_valid.eq(insn_jal.spec_valid) - m.d.comb += spec_insn_jal_trap.eq(insn_jal.spec_trap) - m.d.comb += spec_insn_jal_rs1_addr.eq(insn_jal.spec_rs1_addr) - m.d.comb += spec_insn_jal_rs2_addr.eq(insn_jal.spec_rs2_addr) - m.d.comb += spec_insn_jal_rd_addr.eq(insn_jal.spec_rd_addr) - m.d.comb += spec_insn_jal_rd_wdata.eq(insn_jal.spec_rd_wdata) - m.d.comb += spec_insn_jal_pc_wdata.eq(insn_jal.spec_pc_wdata) - m.d.comb += spec_insn_jal_mem_addr.eq(insn_jal.spec_mem_addr) - m.d.comb += spec_insn_jal_mem_rmask.eq(insn_jal.spec_mem_rmask) - m.d.comb += spec_insn_jal_mem_wmask.eq(insn_jal.spec_mem_wmask) - m.d.comb += spec_insn_jal_mem_wdata.eq(insn_jal.spec_mem_wdata) - - spec_insn_jalr_valid = Signal(1) - spec_insn_jalr_trap = Signal(1) - spec_insn_jalr_rs1_addr = Signal(5) - spec_insn_jalr_rs2_addr = Signal(5) - spec_insn_jalr_rd_addr = Signal(5) - spec_insn_jalr_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_jalr_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_jalr_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_jalr_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_jalr_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_jalr_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_jalr = insn_jalr = rvfi_insn_jalr() - m.d.comb += insn_jalr.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_jalr.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_jalr.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_jalr.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_jalr.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_jalr.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_jalr_valid.eq(insn_jalr.spec_valid) - m.d.comb += spec_insn_jalr_trap.eq(insn_jalr.spec_trap) - m.d.comb += spec_insn_jalr_rs1_addr.eq(insn_jalr.spec_rs1_addr) - m.d.comb += spec_insn_jalr_rs2_addr.eq(insn_jalr.spec_rs2_addr) - m.d.comb += spec_insn_jalr_rd_addr.eq(insn_jalr.spec_rd_addr) - m.d.comb += spec_insn_jalr_rd_wdata.eq(insn_jalr.spec_rd_wdata) - m.d.comb += spec_insn_jalr_pc_wdata.eq(insn_jalr.spec_pc_wdata) - m.d.comb += spec_insn_jalr_mem_addr.eq(insn_jalr.spec_mem_addr) - m.d.comb += spec_insn_jalr_mem_rmask.eq(insn_jalr.spec_mem_rmask) - m.d.comb += spec_insn_jalr_mem_wmask.eq(insn_jalr.spec_mem_wmask) - m.d.comb += spec_insn_jalr_mem_wdata.eq(insn_jalr.spec_mem_wdata) - - spec_insn_beq_valid = Signal(1) - spec_insn_beq_trap = Signal(1) - spec_insn_beq_rs1_addr = Signal(5) - spec_insn_beq_rs2_addr = Signal(5) - spec_insn_beq_rd_addr = Signal(5) - spec_insn_beq_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_beq_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_beq_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_beq_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_beq_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_beq_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_beq = insn_beq = rvfi_insn_beq() - m.d.comb += insn_beq.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_beq.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_beq.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_beq.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_beq.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_beq.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_beq_valid.eq(insn_beq.spec_valid) - m.d.comb += spec_insn_beq_trap.eq(insn_beq.spec_trap) - m.d.comb += spec_insn_beq_rs1_addr.eq(insn_beq.spec_rs1_addr) - m.d.comb += spec_insn_beq_rs2_addr.eq(insn_beq.spec_rs2_addr) - m.d.comb += spec_insn_beq_rd_addr.eq(insn_beq.spec_rd_addr) - m.d.comb += spec_insn_beq_rd_wdata.eq(insn_beq.spec_rd_wdata) - m.d.comb += spec_insn_beq_pc_wdata.eq(insn_beq.spec_pc_wdata) - m.d.comb += spec_insn_beq_mem_addr.eq(insn_beq.spec_mem_addr) - m.d.comb += spec_insn_beq_mem_rmask.eq(insn_beq.spec_mem_rmask) - m.d.comb += spec_insn_beq_mem_wmask.eq(insn_beq.spec_mem_wmask) - m.d.comb += spec_insn_beq_mem_wdata.eq(insn_beq.spec_mem_wdata) - - spec_insn_bne_valid = Signal(1) - spec_insn_bne_trap = Signal(1) - spec_insn_bne_rs1_addr = Signal(5) - spec_insn_bne_rs2_addr = Signal(5) - spec_insn_bne_rd_addr = Signal(5) - spec_insn_bne_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bne_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bne_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bne_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_bne_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_bne_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_bne = insn_bne = rvfi_insn_bne() - m.d.comb += insn_bne.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_bne.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_bne.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_bne.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_bne.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_bne.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_bne_valid.eq(insn_bne.spec_valid) - m.d.comb += spec_insn_bne_trap.eq(insn_bne.spec_trap) - m.d.comb += spec_insn_bne_rs1_addr.eq(insn_bne.spec_rs1_addr) - m.d.comb += spec_insn_bne_rs2_addr.eq(insn_bne.spec_rs2_addr) - m.d.comb += spec_insn_bne_rd_addr.eq(insn_bne.spec_rd_addr) - m.d.comb += spec_insn_bne_rd_wdata.eq(insn_bne.spec_rd_wdata) - m.d.comb += spec_insn_bne_pc_wdata.eq(insn_bne.spec_pc_wdata) - m.d.comb += spec_insn_bne_mem_addr.eq(insn_bne.spec_mem_addr) - m.d.comb += spec_insn_bne_mem_rmask.eq(insn_bne.spec_mem_rmask) - m.d.comb += spec_insn_bne_mem_wmask.eq(insn_bne.spec_mem_wmask) - m.d.comb += spec_insn_bne_mem_wdata.eq(insn_bne.spec_mem_wdata) - - spec_insn_blt_valid = Signal(1) - spec_insn_blt_trap = Signal(1) - spec_insn_blt_rs1_addr = Signal(5) - spec_insn_blt_rs2_addr = Signal(5) - spec_insn_blt_rd_addr = Signal(5) - spec_insn_blt_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_blt_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_blt_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_blt_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_blt_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_blt_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_blt = insn_blt = rvfi_insn_blt() - m.d.comb += insn_blt.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_blt.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_blt.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_blt.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_blt.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_blt.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_blt_valid.eq(insn_blt.spec_valid) - m.d.comb += spec_insn_blt_trap.eq(insn_blt.spec_trap) - m.d.comb += spec_insn_blt_rs1_addr.eq(insn_blt.spec_rs1_addr) - m.d.comb += spec_insn_blt_rs2_addr.eq(insn_blt.spec_rs2_addr) - m.d.comb += spec_insn_blt_rd_addr.eq(insn_blt.spec_rd_addr) - m.d.comb += spec_insn_blt_rd_wdata.eq(insn_blt.spec_rd_wdata) - m.d.comb += spec_insn_blt_pc_wdata.eq(insn_blt.spec_pc_wdata) - m.d.comb += spec_insn_blt_mem_addr.eq(insn_blt.spec_mem_addr) - m.d.comb += spec_insn_blt_mem_rmask.eq(insn_blt.spec_mem_rmask) - m.d.comb += spec_insn_blt_mem_wmask.eq(insn_blt.spec_mem_wmask) - m.d.comb += spec_insn_blt_mem_wdata.eq(insn_blt.spec_mem_wdata) - - spec_insn_bge_valid = Signal(1) - spec_insn_bge_trap = Signal(1) - spec_insn_bge_rs1_addr = Signal(5) - spec_insn_bge_rs2_addr = Signal(5) - spec_insn_bge_rd_addr = Signal(5) - spec_insn_bge_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bge_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bge_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bge_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_bge_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_bge_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_bge = insn_bge = rvfi_insn_bge() - m.d.comb += insn_bge.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_bge.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_bge.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_bge.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_bge.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_bge.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_bge_valid.eq(insn_bge.spec_valid) - m.d.comb += spec_insn_bge_trap.eq(insn_bge.spec_trap) - m.d.comb += spec_insn_bge_rs1_addr.eq(insn_bge.spec_rs1_addr) - m.d.comb += spec_insn_bge_rs2_addr.eq(insn_bge.spec_rs2_addr) - m.d.comb += spec_insn_bge_rd_addr.eq(insn_bge.spec_rd_addr) - m.d.comb += spec_insn_bge_rd_wdata.eq(insn_bge.spec_rd_wdata) - m.d.comb += spec_insn_bge_pc_wdata.eq(insn_bge.spec_pc_wdata) - m.d.comb += spec_insn_bge_mem_addr.eq(insn_bge.spec_mem_addr) - m.d.comb += spec_insn_bge_mem_rmask.eq(insn_bge.spec_mem_rmask) - m.d.comb += spec_insn_bge_mem_wmask.eq(insn_bge.spec_mem_wmask) - m.d.comb += spec_insn_bge_mem_wdata.eq(insn_bge.spec_mem_wdata) - - spec_insn_bltu_valid = Signal(1) - spec_insn_bltu_trap = Signal(1) - spec_insn_bltu_rs1_addr = Signal(5) - spec_insn_bltu_rs2_addr = Signal(5) - spec_insn_bltu_rd_addr = Signal(5) - spec_insn_bltu_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bltu_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bltu_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bltu_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_bltu_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_bltu_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_bltu = insn_bltu = rvfi_insn_bltu() - m.d.comb += insn_bltu.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_bltu.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_bltu.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_bltu.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_bltu.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_bltu.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_bltu_valid.eq(insn_bltu.spec_valid) - m.d.comb += spec_insn_bltu_trap.eq(insn_bltu.spec_trap) - m.d.comb += spec_insn_bltu_rs1_addr.eq(insn_bltu.spec_rs1_addr) - m.d.comb += spec_insn_bltu_rs2_addr.eq(insn_bltu.spec_rs2_addr) - m.d.comb += spec_insn_bltu_rd_addr.eq(insn_bltu.spec_rd_addr) - m.d.comb += spec_insn_bltu_rd_wdata.eq(insn_bltu.spec_rd_wdata) - m.d.comb += spec_insn_bltu_pc_wdata.eq(insn_bltu.spec_pc_wdata) - m.d.comb += spec_insn_bltu_mem_addr.eq(insn_bltu.spec_mem_addr) - m.d.comb += spec_insn_bltu_mem_rmask.eq(insn_bltu.spec_mem_rmask) - m.d.comb += spec_insn_bltu_mem_wmask.eq(insn_bltu.spec_mem_wmask) - m.d.comb += spec_insn_bltu_mem_wdata.eq(insn_bltu.spec_mem_wdata) - - spec_insn_bgeu_valid = Signal(1) - spec_insn_bgeu_trap = Signal(1) - spec_insn_bgeu_rs1_addr = Signal(5) - spec_insn_bgeu_rs2_addr = Signal(5) - spec_insn_bgeu_rd_addr = Signal(5) - spec_insn_bgeu_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bgeu_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bgeu_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bgeu_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_bgeu_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_bgeu_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_bgeu = insn_bgeu = rvfi_insn_bgeu() - m.d.comb += insn_bgeu.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_bgeu.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_bgeu.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_bgeu.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_bgeu.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_bgeu.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_bgeu_valid.eq(insn_bgeu.spec_valid) - m.d.comb += spec_insn_bgeu_trap.eq(insn_bgeu.spec_trap) - m.d.comb += spec_insn_bgeu_rs1_addr.eq(insn_bgeu.spec_rs1_addr) - m.d.comb += spec_insn_bgeu_rs2_addr.eq(insn_bgeu.spec_rs2_addr) - m.d.comb += spec_insn_bgeu_rd_addr.eq(insn_bgeu.spec_rd_addr) - m.d.comb += spec_insn_bgeu_rd_wdata.eq(insn_bgeu.spec_rd_wdata) - m.d.comb += spec_insn_bgeu_pc_wdata.eq(insn_bgeu.spec_pc_wdata) - m.d.comb += spec_insn_bgeu_mem_addr.eq(insn_bgeu.spec_mem_addr) - m.d.comb += spec_insn_bgeu_mem_rmask.eq(insn_bgeu.spec_mem_rmask) - m.d.comb += spec_insn_bgeu_mem_wmask.eq(insn_bgeu.spec_mem_wmask) - m.d.comb += spec_insn_bgeu_mem_wdata.eq(insn_bgeu.spec_mem_wdata) - - spec_insn_lb_valid = Signal(1) - spec_insn_lb_trap = Signal(1) - spec_insn_lb_rs1_addr = Signal(5) - spec_insn_lb_rs2_addr = Signal(5) - spec_insn_lb_rd_addr = Signal(5) - spec_insn_lb_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lb_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lb_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lb_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lb_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lb_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_lb = insn_lb = rvfi_insn_lb() - m.d.comb += insn_lb.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_lb.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_lb.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_lb.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_lb.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_lb.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_lb_valid.eq(insn_lb.spec_valid) - m.d.comb += spec_insn_lb_trap.eq(insn_lb.spec_trap) - m.d.comb += spec_insn_lb_rs1_addr.eq(insn_lb.spec_rs1_addr) - m.d.comb += spec_insn_lb_rs2_addr.eq(insn_lb.spec_rs2_addr) - m.d.comb += spec_insn_lb_rd_addr.eq(insn_lb.spec_rd_addr) - m.d.comb += spec_insn_lb_rd_wdata.eq(insn_lb.spec_rd_wdata) - m.d.comb += spec_insn_lb_pc_wdata.eq(insn_lb.spec_pc_wdata) - m.d.comb += spec_insn_lb_mem_addr.eq(insn_lb.spec_mem_addr) - m.d.comb += spec_insn_lb_mem_rmask.eq(insn_lb.spec_mem_rmask) - m.d.comb += spec_insn_lb_mem_wmask.eq(insn_lb.spec_mem_wmask) - m.d.comb += spec_insn_lb_mem_wdata.eq(insn_lb.spec_mem_wdata) - - spec_insn_lh_valid = Signal(1) - spec_insn_lh_trap = Signal(1) - spec_insn_lh_rs1_addr = Signal(5) - spec_insn_lh_rs2_addr = Signal(5) - spec_insn_lh_rd_addr = Signal(5) - spec_insn_lh_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lh_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lh_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lh_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lh_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lh_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_lh = insn_lh = rvfi_insn_lh() - m.d.comb += insn_lh.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_lh.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_lh.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_lh.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_lh.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_lh.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_lh_valid.eq(insn_lh.spec_valid) - m.d.comb += spec_insn_lh_trap.eq(insn_lh.spec_trap) - m.d.comb += spec_insn_lh_rs1_addr.eq(insn_lh.spec_rs1_addr) - m.d.comb += spec_insn_lh_rs2_addr.eq(insn_lh.spec_rs2_addr) - m.d.comb += spec_insn_lh_rd_addr.eq(insn_lh.spec_rd_addr) - m.d.comb += spec_insn_lh_rd_wdata.eq(insn_lh.spec_rd_wdata) - m.d.comb += spec_insn_lh_pc_wdata.eq(insn_lh.spec_pc_wdata) - m.d.comb += spec_insn_lh_mem_addr.eq(insn_lh.spec_mem_addr) - m.d.comb += spec_insn_lh_mem_rmask.eq(insn_lh.spec_mem_rmask) - m.d.comb += spec_insn_lh_mem_wmask.eq(insn_lh.spec_mem_wmask) - m.d.comb += spec_insn_lh_mem_wdata.eq(insn_lh.spec_mem_wdata) - - spec_insn_lw_valid = Signal(1) - spec_insn_lw_trap = Signal(1) - spec_insn_lw_rs1_addr = Signal(5) - spec_insn_lw_rs2_addr = Signal(5) - spec_insn_lw_rd_addr = Signal(5) - spec_insn_lw_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lw_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lw_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lw_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lw_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lw_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_lw = insn_lw = rvfi_insn_lw() - m.d.comb += insn_lw.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_lw.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_lw.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_lw.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_lw.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_lw.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_lw_valid.eq(insn_lw.spec_valid) - m.d.comb += spec_insn_lw_trap.eq(insn_lw.spec_trap) - m.d.comb += spec_insn_lw_rs1_addr.eq(insn_lw.spec_rs1_addr) - m.d.comb += spec_insn_lw_rs2_addr.eq(insn_lw.spec_rs2_addr) - m.d.comb += spec_insn_lw_rd_addr.eq(insn_lw.spec_rd_addr) - m.d.comb += spec_insn_lw_rd_wdata.eq(insn_lw.spec_rd_wdata) - m.d.comb += spec_insn_lw_pc_wdata.eq(insn_lw.spec_pc_wdata) - m.d.comb += spec_insn_lw_mem_addr.eq(insn_lw.spec_mem_addr) - m.d.comb += spec_insn_lw_mem_rmask.eq(insn_lw.spec_mem_rmask) - m.d.comb += spec_insn_lw_mem_wmask.eq(insn_lw.spec_mem_wmask) - m.d.comb += spec_insn_lw_mem_wdata.eq(insn_lw.spec_mem_wdata) - - spec_insn_lbu_valid = Signal(1) - spec_insn_lbu_trap = Signal(1) - spec_insn_lbu_rs1_addr = Signal(5) - spec_insn_lbu_rs2_addr = Signal(5) - spec_insn_lbu_rd_addr = Signal(5) - spec_insn_lbu_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lbu_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lbu_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lbu_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lbu_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lbu_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_lbu = insn_lbu = rvfi_insn_lbu() - m.d.comb += insn_lbu.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_lbu.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_lbu.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_lbu.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_lbu.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_lbu.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_lbu_valid.eq(insn_lbu.spec_valid) - m.d.comb += spec_insn_lbu_trap.eq(insn_lbu.spec_trap) - m.d.comb += spec_insn_lbu_rs1_addr.eq(insn_lbu.spec_rs1_addr) - m.d.comb += spec_insn_lbu_rs2_addr.eq(insn_lbu.spec_rs2_addr) - m.d.comb += spec_insn_lbu_rd_addr.eq(insn_lbu.spec_rd_addr) - m.d.comb += spec_insn_lbu_rd_wdata.eq(insn_lbu.spec_rd_wdata) - m.d.comb += spec_insn_lbu_pc_wdata.eq(insn_lbu.spec_pc_wdata) - m.d.comb += spec_insn_lbu_mem_addr.eq(insn_lbu.spec_mem_addr) - m.d.comb += spec_insn_lbu_mem_rmask.eq(insn_lbu.spec_mem_rmask) - m.d.comb += spec_insn_lbu_mem_wmask.eq(insn_lbu.spec_mem_wmask) - m.d.comb += spec_insn_lbu_mem_wdata.eq(insn_lbu.spec_mem_wdata) - - spec_insn_lhu_valid = Signal(1) - spec_insn_lhu_trap = Signal(1) - spec_insn_lhu_rs1_addr = Signal(5) - spec_insn_lhu_rs2_addr = Signal(5) - spec_insn_lhu_rd_addr = Signal(5) - spec_insn_lhu_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lhu_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lhu_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lhu_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lhu_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lhu_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_lhu = insn_lhu = rvfi_insn_lhu() - m.d.comb += insn_lhu.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_lhu.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_lhu.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_lhu.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_lhu.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_lhu.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_lhu_valid.eq(insn_lhu.spec_valid) - m.d.comb += spec_insn_lhu_trap.eq(insn_lhu.spec_trap) - m.d.comb += spec_insn_lhu_rs1_addr.eq(insn_lhu.spec_rs1_addr) - m.d.comb += spec_insn_lhu_rs2_addr.eq(insn_lhu.spec_rs2_addr) - m.d.comb += spec_insn_lhu_rd_addr.eq(insn_lhu.spec_rd_addr) - m.d.comb += spec_insn_lhu_rd_wdata.eq(insn_lhu.spec_rd_wdata) - m.d.comb += spec_insn_lhu_pc_wdata.eq(insn_lhu.spec_pc_wdata) - m.d.comb += spec_insn_lhu_mem_addr.eq(insn_lhu.spec_mem_addr) - m.d.comb += spec_insn_lhu_mem_rmask.eq(insn_lhu.spec_mem_rmask) - m.d.comb += spec_insn_lhu_mem_wmask.eq(insn_lhu.spec_mem_wmask) - m.d.comb += spec_insn_lhu_mem_wdata.eq(insn_lhu.spec_mem_wdata) - - spec_insn_sb_valid = Signal(1) - spec_insn_sb_trap = Signal(1) - spec_insn_sb_rs1_addr = Signal(5) - spec_insn_sb_rs2_addr = Signal(5) - spec_insn_sb_rd_addr = Signal(5) - spec_insn_sb_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sb_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sb_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sb_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sb_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sb_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_sb = insn_sb = rvfi_insn_sb() - m.d.comb += insn_sb.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_sb.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_sb.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_sb.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_sb.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_sb.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_sb_valid.eq(insn_sb.spec_valid) - m.d.comb += spec_insn_sb_trap.eq(insn_sb.spec_trap) - m.d.comb += spec_insn_sb_rs1_addr.eq(insn_sb.spec_rs1_addr) - m.d.comb += spec_insn_sb_rs2_addr.eq(insn_sb.spec_rs2_addr) - m.d.comb += spec_insn_sb_rd_addr.eq(insn_sb.spec_rd_addr) - m.d.comb += spec_insn_sb_rd_wdata.eq(insn_sb.spec_rd_wdata) - m.d.comb += spec_insn_sb_pc_wdata.eq(insn_sb.spec_pc_wdata) - m.d.comb += spec_insn_sb_mem_addr.eq(insn_sb.spec_mem_addr) - m.d.comb += spec_insn_sb_mem_rmask.eq(insn_sb.spec_mem_rmask) - m.d.comb += spec_insn_sb_mem_wmask.eq(insn_sb.spec_mem_wmask) - m.d.comb += spec_insn_sb_mem_wdata.eq(insn_sb.spec_mem_wdata) - - spec_insn_sh_valid = Signal(1) - spec_insn_sh_trap = Signal(1) - spec_insn_sh_rs1_addr = Signal(5) - spec_insn_sh_rs2_addr = Signal(5) - spec_insn_sh_rd_addr = Signal(5) - spec_insn_sh_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sh_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sh_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sh_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sh_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sh_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_sh = insn_sh = rvfi_insn_sh() - m.d.comb += insn_sh.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_sh.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_sh.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_sh.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_sh.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_sh.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_sh_valid.eq(insn_sh.spec_valid) - m.d.comb += spec_insn_sh_trap.eq(insn_sh.spec_trap) - m.d.comb += spec_insn_sh_rs1_addr.eq(insn_sh.spec_rs1_addr) - m.d.comb += spec_insn_sh_rs2_addr.eq(insn_sh.spec_rs2_addr) - m.d.comb += spec_insn_sh_rd_addr.eq(insn_sh.spec_rd_addr) - m.d.comb += spec_insn_sh_rd_wdata.eq(insn_sh.spec_rd_wdata) - m.d.comb += spec_insn_sh_pc_wdata.eq(insn_sh.spec_pc_wdata) - m.d.comb += spec_insn_sh_mem_addr.eq(insn_sh.spec_mem_addr) - m.d.comb += spec_insn_sh_mem_rmask.eq(insn_sh.spec_mem_rmask) - m.d.comb += spec_insn_sh_mem_wmask.eq(insn_sh.spec_mem_wmask) - m.d.comb += spec_insn_sh_mem_wdata.eq(insn_sh.spec_mem_wdata) - - spec_insn_sw_valid = Signal(1) - spec_insn_sw_trap = Signal(1) - spec_insn_sw_rs1_addr = Signal(5) - spec_insn_sw_rs2_addr = Signal(5) - spec_insn_sw_rd_addr = Signal(5) - spec_insn_sw_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sw_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sw_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sw_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sw_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sw_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_sw = insn_sw = rvfi_insn_sw() - m.d.comb += insn_sw.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_sw.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_sw.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_sw.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_sw.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_sw.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_sw_valid.eq(insn_sw.spec_valid) - m.d.comb += spec_insn_sw_trap.eq(insn_sw.spec_trap) - m.d.comb += spec_insn_sw_rs1_addr.eq(insn_sw.spec_rs1_addr) - m.d.comb += spec_insn_sw_rs2_addr.eq(insn_sw.spec_rs2_addr) - m.d.comb += spec_insn_sw_rd_addr.eq(insn_sw.spec_rd_addr) - m.d.comb += spec_insn_sw_rd_wdata.eq(insn_sw.spec_rd_wdata) - m.d.comb += spec_insn_sw_pc_wdata.eq(insn_sw.spec_pc_wdata) - m.d.comb += spec_insn_sw_mem_addr.eq(insn_sw.spec_mem_addr) - m.d.comb += spec_insn_sw_mem_rmask.eq(insn_sw.spec_mem_rmask) - m.d.comb += spec_insn_sw_mem_wmask.eq(insn_sw.spec_mem_wmask) - m.d.comb += spec_insn_sw_mem_wdata.eq(insn_sw.spec_mem_wdata) - - spec_insn_addi_valid = Signal(1) - spec_insn_addi_trap = Signal(1) - spec_insn_addi_rs1_addr = Signal(5) - spec_insn_addi_rs2_addr = Signal(5) - spec_insn_addi_rd_addr = Signal(5) - spec_insn_addi_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_addi_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_addi_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_addi_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_addi_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_addi_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_addi = insn_addi = rvfi_insn_addi() - m.d.comb += insn_addi.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_addi.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_addi.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_addi.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_addi.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_addi.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_addi_valid.eq(insn_addi.spec_valid) - m.d.comb += spec_insn_addi_trap.eq(insn_addi.spec_trap) - m.d.comb += spec_insn_addi_rs1_addr.eq(insn_addi.spec_rs1_addr) - m.d.comb += spec_insn_addi_rs2_addr.eq(insn_addi.spec_rs2_addr) - m.d.comb += spec_insn_addi_rd_addr.eq(insn_addi.spec_rd_addr) - m.d.comb += spec_insn_addi_rd_wdata.eq(insn_addi.spec_rd_wdata) - m.d.comb += spec_insn_addi_pc_wdata.eq(insn_addi.spec_pc_wdata) - m.d.comb += spec_insn_addi_mem_addr.eq(insn_addi.spec_mem_addr) - m.d.comb += spec_insn_addi_mem_rmask.eq(insn_addi.spec_mem_rmask) - m.d.comb += spec_insn_addi_mem_wmask.eq(insn_addi.spec_mem_wmask) - m.d.comb += spec_insn_addi_mem_wdata.eq(insn_addi.spec_mem_wdata) - - spec_insn_slti_valid = Signal(1) - spec_insn_slti_trap = Signal(1) - spec_insn_slti_rs1_addr = Signal(5) - spec_insn_slti_rs2_addr = Signal(5) - spec_insn_slti_rd_addr = Signal(5) - spec_insn_slti_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_slti_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_slti_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_slti_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_slti_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_slti_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_slti = insn_slti = rvfi_insn_slti() - m.d.comb += insn_slti.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_slti.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_slti.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_slti.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_slti.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_slti.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_slti_valid.eq(insn_slti.spec_valid) - m.d.comb += spec_insn_slti_trap.eq(insn_slti.spec_trap) - m.d.comb += spec_insn_slti_rs1_addr.eq(insn_slti.spec_rs1_addr) - m.d.comb += spec_insn_slti_rs2_addr.eq(insn_slti.spec_rs2_addr) - m.d.comb += spec_insn_slti_rd_addr.eq(insn_slti.spec_rd_addr) - m.d.comb += spec_insn_slti_rd_wdata.eq(insn_slti.spec_rd_wdata) - m.d.comb += spec_insn_slti_pc_wdata.eq(insn_slti.spec_pc_wdata) - m.d.comb += spec_insn_slti_mem_addr.eq(insn_slti.spec_mem_addr) - m.d.comb += spec_insn_slti_mem_rmask.eq(insn_slti.spec_mem_rmask) - m.d.comb += spec_insn_slti_mem_wmask.eq(insn_slti.spec_mem_wmask) - m.d.comb += spec_insn_slti_mem_wdata.eq(insn_slti.spec_mem_wdata) - - spec_insn_sltiu_valid = Signal(1) - spec_insn_sltiu_trap = Signal(1) - spec_insn_sltiu_rs1_addr = Signal(5) - spec_insn_sltiu_rs2_addr = Signal(5) - spec_insn_sltiu_rd_addr = Signal(5) - spec_insn_sltiu_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sltiu_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sltiu_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sltiu_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sltiu_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sltiu_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_sltiu = insn_sltiu = rvfi_insn_sltiu() - m.d.comb += insn_sltiu.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_sltiu.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_sltiu.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_sltiu.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_sltiu.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_sltiu.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_sltiu_valid.eq(insn_sltiu.spec_valid) - m.d.comb += spec_insn_sltiu_trap.eq(insn_sltiu.spec_trap) - m.d.comb += spec_insn_sltiu_rs1_addr.eq(insn_sltiu.spec_rs1_addr) - m.d.comb += spec_insn_sltiu_rs2_addr.eq(insn_sltiu.spec_rs2_addr) - m.d.comb += spec_insn_sltiu_rd_addr.eq(insn_sltiu.spec_rd_addr) - m.d.comb += spec_insn_sltiu_rd_wdata.eq(insn_sltiu.spec_rd_wdata) - m.d.comb += spec_insn_sltiu_pc_wdata.eq(insn_sltiu.spec_pc_wdata) - m.d.comb += spec_insn_sltiu_mem_addr.eq(insn_sltiu.spec_mem_addr) - m.d.comb += spec_insn_sltiu_mem_rmask.eq(insn_sltiu.spec_mem_rmask) - m.d.comb += spec_insn_sltiu_mem_wmask.eq(insn_sltiu.spec_mem_wmask) - m.d.comb += spec_insn_sltiu_mem_wdata.eq(insn_sltiu.spec_mem_wdata) - - spec_insn_xori_valid = Signal(1) - spec_insn_xori_trap = Signal(1) - spec_insn_xori_rs1_addr = Signal(5) - spec_insn_xori_rs2_addr = Signal(5) - spec_insn_xori_rd_addr = Signal(5) - spec_insn_xori_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_xori_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_xori_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_xori_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_xori_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_xori_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_xori = insn_xori = rvfi_insn_xori() - m.d.comb += insn_xori.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_xori.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_xori.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_xori.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_xori.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_xori.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_xori_valid.eq(insn_xori.spec_valid) - m.d.comb += spec_insn_xori_trap.eq(insn_xori.spec_trap) - m.d.comb += spec_insn_xori_rs1_addr.eq(insn_xori.spec_rs1_addr) - m.d.comb += spec_insn_xori_rs2_addr.eq(insn_xori.spec_rs2_addr) - m.d.comb += spec_insn_xori_rd_addr.eq(insn_xori.spec_rd_addr) - m.d.comb += spec_insn_xori_rd_wdata.eq(insn_xori.spec_rd_wdata) - m.d.comb += spec_insn_xori_pc_wdata.eq(insn_xori.spec_pc_wdata) - m.d.comb += spec_insn_xori_mem_addr.eq(insn_xori.spec_mem_addr) - m.d.comb += spec_insn_xori_mem_rmask.eq(insn_xori.spec_mem_rmask) - m.d.comb += spec_insn_xori_mem_wmask.eq(insn_xori.spec_mem_wmask) - m.d.comb += spec_insn_xori_mem_wdata.eq(insn_xori.spec_mem_wdata) - - spec_insn_ori_valid = Signal(1) - spec_insn_ori_trap = Signal(1) - spec_insn_ori_rs1_addr = Signal(5) - spec_insn_ori_rs2_addr = Signal(5) - spec_insn_ori_rd_addr = Signal(5) - spec_insn_ori_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_ori_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_ori_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_ori_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_ori_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_ori_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_ori = insn_ori = rvfi_insn_ori() - m.d.comb += insn_ori.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_ori.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_ori.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_ori.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_ori.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_ori.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_ori_valid.eq(insn_ori.spec_valid) - m.d.comb += spec_insn_ori_trap.eq(insn_ori.spec_trap) - m.d.comb += spec_insn_ori_rs1_addr.eq(insn_ori.spec_rs1_addr) - m.d.comb += spec_insn_ori_rs2_addr.eq(insn_ori.spec_rs2_addr) - m.d.comb += spec_insn_ori_rd_addr.eq(insn_ori.spec_rd_addr) - m.d.comb += spec_insn_ori_rd_wdata.eq(insn_ori.spec_rd_wdata) - m.d.comb += spec_insn_ori_pc_wdata.eq(insn_ori.spec_pc_wdata) - m.d.comb += spec_insn_ori_mem_addr.eq(insn_ori.spec_mem_addr) - m.d.comb += spec_insn_ori_mem_rmask.eq(insn_ori.spec_mem_rmask) - m.d.comb += spec_insn_ori_mem_wmask.eq(insn_ori.spec_mem_wmask) - m.d.comb += spec_insn_ori_mem_wdata.eq(insn_ori.spec_mem_wdata) - - spec_insn_andi_valid = Signal(1) - spec_insn_andi_trap = Signal(1) - spec_insn_andi_rs1_addr = Signal(5) - spec_insn_andi_rs2_addr = Signal(5) - spec_insn_andi_rd_addr = Signal(5) - spec_insn_andi_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_andi_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_andi_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_andi_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_andi_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_andi_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_andi = insn_andi = rvfi_insn_andi() - m.d.comb += insn_andi.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_andi.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_andi.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_andi.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_andi.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_andi.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_andi_valid.eq(insn_andi.spec_valid) - m.d.comb += spec_insn_andi_trap.eq(insn_andi.spec_trap) - m.d.comb += spec_insn_andi_rs1_addr.eq(insn_andi.spec_rs1_addr) - m.d.comb += spec_insn_andi_rs2_addr.eq(insn_andi.spec_rs2_addr) - m.d.comb += spec_insn_andi_rd_addr.eq(insn_andi.spec_rd_addr) - m.d.comb += spec_insn_andi_rd_wdata.eq(insn_andi.spec_rd_wdata) - m.d.comb += spec_insn_andi_pc_wdata.eq(insn_andi.spec_pc_wdata) - m.d.comb += spec_insn_andi_mem_addr.eq(insn_andi.spec_mem_addr) - m.d.comb += spec_insn_andi_mem_rmask.eq(insn_andi.spec_mem_rmask) - m.d.comb += spec_insn_andi_mem_wmask.eq(insn_andi.spec_mem_wmask) - m.d.comb += spec_insn_andi_mem_wdata.eq(insn_andi.spec_mem_wdata) - - spec_insn_slli_valid = Signal(1) - spec_insn_slli_trap = Signal(1) - spec_insn_slli_rs1_addr = Signal(5) - spec_insn_slli_rs2_addr = Signal(5) - spec_insn_slli_rd_addr = Signal(5) - spec_insn_slli_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_slli_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_slli_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_slli_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_slli_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_slli_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_slli = insn_slli = rvfi_insn_slli() - m.d.comb += insn_slli.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_slli.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_slli.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_slli.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_slli.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_slli.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_slli_valid.eq(insn_slli.spec_valid) - m.d.comb += spec_insn_slli_trap.eq(insn_slli.spec_trap) - m.d.comb += spec_insn_slli_rs1_addr.eq(insn_slli.spec_rs1_addr) - m.d.comb += spec_insn_slli_rs2_addr.eq(insn_slli.spec_rs2_addr) - m.d.comb += spec_insn_slli_rd_addr.eq(insn_slli.spec_rd_addr) - m.d.comb += spec_insn_slli_rd_wdata.eq(insn_slli.spec_rd_wdata) - m.d.comb += spec_insn_slli_pc_wdata.eq(insn_slli.spec_pc_wdata) - m.d.comb += spec_insn_slli_mem_addr.eq(insn_slli.spec_mem_addr) - m.d.comb += spec_insn_slli_mem_rmask.eq(insn_slli.spec_mem_rmask) - m.d.comb += spec_insn_slli_mem_wmask.eq(insn_slli.spec_mem_wmask) - m.d.comb += spec_insn_slli_mem_wdata.eq(insn_slli.spec_mem_wdata) - - spec_insn_srli_valid = Signal(1) - spec_insn_srli_trap = Signal(1) - spec_insn_srli_rs1_addr = Signal(5) - spec_insn_srli_rs2_addr = Signal(5) - spec_insn_srli_rd_addr = Signal(5) - spec_insn_srli_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_srli_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_srli_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_srli_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_srli_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_srli_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_srli = insn_srli = rvfi_insn_srli() - m.d.comb += insn_srli.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_srli.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_srli.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_srli.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_srli.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_srli.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_srli_valid.eq(insn_srli.spec_valid) - m.d.comb += spec_insn_srli_trap.eq(insn_srli.spec_trap) - m.d.comb += spec_insn_srli_rs1_addr.eq(insn_srli.spec_rs1_addr) - m.d.comb += spec_insn_srli_rs2_addr.eq(insn_srli.spec_rs2_addr) - m.d.comb += spec_insn_srli_rd_addr.eq(insn_srli.spec_rd_addr) - m.d.comb += spec_insn_srli_rd_wdata.eq(insn_srli.spec_rd_wdata) - m.d.comb += spec_insn_srli_pc_wdata.eq(insn_srli.spec_pc_wdata) - m.d.comb += spec_insn_srli_mem_addr.eq(insn_srli.spec_mem_addr) - m.d.comb += spec_insn_srli_mem_rmask.eq(insn_srli.spec_mem_rmask) - m.d.comb += spec_insn_srli_mem_wmask.eq(insn_srli.spec_mem_wmask) - m.d.comb += spec_insn_srli_mem_wdata.eq(insn_srli.spec_mem_wdata) - - spec_insn_srai_valid = Signal(1) - spec_insn_srai_trap = Signal(1) - spec_insn_srai_rs1_addr = Signal(5) - spec_insn_srai_rs2_addr = Signal(5) - spec_insn_srai_rd_addr = Signal(5) - spec_insn_srai_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_srai_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_srai_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_srai_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_srai_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_srai_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_srai = insn_srai = rvfi_insn_srai() - m.d.comb += insn_srai.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_srai.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_srai.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_srai.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_srai.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_srai.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_srai_valid.eq(insn_srai.spec_valid) - m.d.comb += spec_insn_srai_trap.eq(insn_srai.spec_trap) - m.d.comb += spec_insn_srai_rs1_addr.eq(insn_srai.spec_rs1_addr) - m.d.comb += spec_insn_srai_rs2_addr.eq(insn_srai.spec_rs2_addr) - m.d.comb += spec_insn_srai_rd_addr.eq(insn_srai.spec_rd_addr) - m.d.comb += spec_insn_srai_rd_wdata.eq(insn_srai.spec_rd_wdata) - m.d.comb += spec_insn_srai_pc_wdata.eq(insn_srai.spec_pc_wdata) - m.d.comb += spec_insn_srai_mem_addr.eq(insn_srai.spec_mem_addr) - m.d.comb += spec_insn_srai_mem_rmask.eq(insn_srai.spec_mem_rmask) - m.d.comb += spec_insn_srai_mem_wmask.eq(insn_srai.spec_mem_wmask) - m.d.comb += spec_insn_srai_mem_wdata.eq(insn_srai.spec_mem_wdata) - - spec_insn_add_valid = Signal(1) - spec_insn_add_trap = Signal(1) - spec_insn_add_rs1_addr = Signal(5) - spec_insn_add_rs2_addr = Signal(5) - spec_insn_add_rd_addr = Signal(5) - spec_insn_add_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_add_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_add_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_add_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_add_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_add_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_add = insn_add = rvfi_insn_add() - m.d.comb += insn_add.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_add.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_add.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_add.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_add.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_add.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_add_valid.eq(insn_add.spec_valid) - m.d.comb += spec_insn_add_trap.eq(insn_add.spec_trap) - m.d.comb += spec_insn_add_rs1_addr.eq(insn_add.spec_rs1_addr) - m.d.comb += spec_insn_add_rs2_addr.eq(insn_add.spec_rs2_addr) - m.d.comb += spec_insn_add_rd_addr.eq(insn_add.spec_rd_addr) - m.d.comb += spec_insn_add_rd_wdata.eq(insn_add.spec_rd_wdata) - m.d.comb += spec_insn_add_pc_wdata.eq(insn_add.spec_pc_wdata) - m.d.comb += spec_insn_add_mem_addr.eq(insn_add.spec_mem_addr) - m.d.comb += spec_insn_add_mem_rmask.eq(insn_add.spec_mem_rmask) - m.d.comb += spec_insn_add_mem_wmask.eq(insn_add.spec_mem_wmask) - m.d.comb += spec_insn_add_mem_wdata.eq(insn_add.spec_mem_wdata) - - spec_insn_sub_valid = Signal(1) - spec_insn_sub_trap = Signal(1) - spec_insn_sub_rs1_addr = Signal(5) - spec_insn_sub_rs2_addr = Signal(5) - spec_insn_sub_rd_addr = Signal(5) - spec_insn_sub_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sub_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sub_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sub_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sub_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sub_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_sub = insn_sub = rvfi_insn_sub() - m.d.comb += insn_sub.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_sub.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_sub.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_sub.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_sub.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_sub.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_sub_valid.eq(insn_sub.spec_valid) - m.d.comb += spec_insn_sub_trap.eq(insn_sub.spec_trap) - m.d.comb += spec_insn_sub_rs1_addr.eq(insn_sub.spec_rs1_addr) - m.d.comb += spec_insn_sub_rs2_addr.eq(insn_sub.spec_rs2_addr) - m.d.comb += spec_insn_sub_rd_addr.eq(insn_sub.spec_rd_addr) - m.d.comb += spec_insn_sub_rd_wdata.eq(insn_sub.spec_rd_wdata) - m.d.comb += spec_insn_sub_pc_wdata.eq(insn_sub.spec_pc_wdata) - m.d.comb += spec_insn_sub_mem_addr.eq(insn_sub.spec_mem_addr) - m.d.comb += spec_insn_sub_mem_rmask.eq(insn_sub.spec_mem_rmask) - m.d.comb += spec_insn_sub_mem_wmask.eq(insn_sub.spec_mem_wmask) - m.d.comb += spec_insn_sub_mem_wdata.eq(insn_sub.spec_mem_wdata) - - spec_insn_sll_valid = Signal(1) - spec_insn_sll_trap = Signal(1) - spec_insn_sll_rs1_addr = Signal(5) - spec_insn_sll_rs2_addr = Signal(5) - spec_insn_sll_rd_addr = Signal(5) - spec_insn_sll_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sll_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sll_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sll_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sll_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sll_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_sll = insn_sll = rvfi_insn_sll() - m.d.comb += insn_sll.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_sll.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_sll.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_sll.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_sll.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_sll.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_sll_valid.eq(insn_sll.spec_valid) - m.d.comb += spec_insn_sll_trap.eq(insn_sll.spec_trap) - m.d.comb += spec_insn_sll_rs1_addr.eq(insn_sll.spec_rs1_addr) - m.d.comb += spec_insn_sll_rs2_addr.eq(insn_sll.spec_rs2_addr) - m.d.comb += spec_insn_sll_rd_addr.eq(insn_sll.spec_rd_addr) - m.d.comb += spec_insn_sll_rd_wdata.eq(insn_sll.spec_rd_wdata) - m.d.comb += spec_insn_sll_pc_wdata.eq(insn_sll.spec_pc_wdata) - m.d.comb += spec_insn_sll_mem_addr.eq(insn_sll.spec_mem_addr) - m.d.comb += spec_insn_sll_mem_rmask.eq(insn_sll.spec_mem_rmask) - m.d.comb += spec_insn_sll_mem_wmask.eq(insn_sll.spec_mem_wmask) - m.d.comb += spec_insn_sll_mem_wdata.eq(insn_sll.spec_mem_wdata) - - spec_insn_slt_valid = Signal(1) - spec_insn_slt_trap = Signal(1) - spec_insn_slt_rs1_addr = Signal(5) - spec_insn_slt_rs2_addr = Signal(5) - spec_insn_slt_rd_addr = Signal(5) - spec_insn_slt_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_slt_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_slt_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_slt_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_slt_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_slt_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_slt = insn_slt = rvfi_insn_slt() - m.d.comb += insn_slt.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_slt.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_slt.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_slt.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_slt.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_slt.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_slt_valid.eq(insn_slt.spec_valid) - m.d.comb += spec_insn_slt_trap.eq(insn_slt.spec_trap) - m.d.comb += spec_insn_slt_rs1_addr.eq(insn_slt.spec_rs1_addr) - m.d.comb += spec_insn_slt_rs2_addr.eq(insn_slt.spec_rs2_addr) - m.d.comb += spec_insn_slt_rd_addr.eq(insn_slt.spec_rd_addr) - m.d.comb += spec_insn_slt_rd_wdata.eq(insn_slt.spec_rd_wdata) - m.d.comb += spec_insn_slt_pc_wdata.eq(insn_slt.spec_pc_wdata) - m.d.comb += spec_insn_slt_mem_addr.eq(insn_slt.spec_mem_addr) - m.d.comb += spec_insn_slt_mem_rmask.eq(insn_slt.spec_mem_rmask) - m.d.comb += spec_insn_slt_mem_wmask.eq(insn_slt.spec_mem_wmask) - m.d.comb += spec_insn_slt_mem_wdata.eq(insn_slt.spec_mem_wdata) - - spec_insn_sltu_valid = Signal(1) - spec_insn_sltu_trap = Signal(1) - spec_insn_sltu_rs1_addr = Signal(5) - spec_insn_sltu_rs2_addr = Signal(5) - spec_insn_sltu_rd_addr = Signal(5) - spec_insn_sltu_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sltu_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sltu_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sltu_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sltu_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sltu_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_sltu = insn_sltu = rvfi_insn_sltu() - m.d.comb += insn_sltu.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_sltu.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_sltu.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_sltu.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_sltu.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_sltu.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_sltu_valid.eq(insn_sltu.spec_valid) - m.d.comb += spec_insn_sltu_trap.eq(insn_sltu.spec_trap) - m.d.comb += spec_insn_sltu_rs1_addr.eq(insn_sltu.spec_rs1_addr) - m.d.comb += spec_insn_sltu_rs2_addr.eq(insn_sltu.spec_rs2_addr) - m.d.comb += spec_insn_sltu_rd_addr.eq(insn_sltu.spec_rd_addr) - m.d.comb += spec_insn_sltu_rd_wdata.eq(insn_sltu.spec_rd_wdata) - m.d.comb += spec_insn_sltu_pc_wdata.eq(insn_sltu.spec_pc_wdata) - m.d.comb += spec_insn_sltu_mem_addr.eq(insn_sltu.spec_mem_addr) - m.d.comb += spec_insn_sltu_mem_rmask.eq(insn_sltu.spec_mem_rmask) - m.d.comb += spec_insn_sltu_mem_wmask.eq(insn_sltu.spec_mem_wmask) - m.d.comb += spec_insn_sltu_mem_wdata.eq(insn_sltu.spec_mem_wdata) - - spec_insn_xor_valid = Signal(1) - spec_insn_xor_trap = Signal(1) - spec_insn_xor_rs1_addr = Signal(5) - spec_insn_xor_rs2_addr = Signal(5) - spec_insn_xor_rd_addr = Signal(5) - spec_insn_xor_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_xor_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_xor_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_xor_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_xor_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_xor_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_xor = insn_xor = rvfi_insn_xor() - m.d.comb += insn_xor.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_xor.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_xor.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_xor.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_xor.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_xor.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_xor_valid.eq(insn_xor.spec_valid) - m.d.comb += spec_insn_xor_trap.eq(insn_xor.spec_trap) - m.d.comb += spec_insn_xor_rs1_addr.eq(insn_xor.spec_rs1_addr) - m.d.comb += spec_insn_xor_rs2_addr.eq(insn_xor.spec_rs2_addr) - m.d.comb += spec_insn_xor_rd_addr.eq(insn_xor.spec_rd_addr) - m.d.comb += spec_insn_xor_rd_wdata.eq(insn_xor.spec_rd_wdata) - m.d.comb += spec_insn_xor_pc_wdata.eq(insn_xor.spec_pc_wdata) - m.d.comb += spec_insn_xor_mem_addr.eq(insn_xor.spec_mem_addr) - m.d.comb += spec_insn_xor_mem_rmask.eq(insn_xor.spec_mem_rmask) - m.d.comb += spec_insn_xor_mem_wmask.eq(insn_xor.spec_mem_wmask) - m.d.comb += spec_insn_xor_mem_wdata.eq(insn_xor.spec_mem_wdata) - - spec_insn_srl_valid = Signal(1) - spec_insn_srl_trap = Signal(1) - spec_insn_srl_rs1_addr = Signal(5) - spec_insn_srl_rs2_addr = Signal(5) - spec_insn_srl_rd_addr = Signal(5) - spec_insn_srl_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_srl_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_srl_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_srl_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_srl_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_srl_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_srl = insn_srl = rvfi_insn_srl() - m.d.comb += insn_srl.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_srl.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_srl.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_srl.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_srl.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_srl.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_srl_valid.eq(insn_srl.spec_valid) - m.d.comb += spec_insn_srl_trap.eq(insn_srl.spec_trap) - m.d.comb += spec_insn_srl_rs1_addr.eq(insn_srl.spec_rs1_addr) - m.d.comb += spec_insn_srl_rs2_addr.eq(insn_srl.spec_rs2_addr) - m.d.comb += spec_insn_srl_rd_addr.eq(insn_srl.spec_rd_addr) - m.d.comb += spec_insn_srl_rd_wdata.eq(insn_srl.spec_rd_wdata) - m.d.comb += spec_insn_srl_pc_wdata.eq(insn_srl.spec_pc_wdata) - m.d.comb += spec_insn_srl_mem_addr.eq(insn_srl.spec_mem_addr) - m.d.comb += spec_insn_srl_mem_rmask.eq(insn_srl.spec_mem_rmask) - m.d.comb += spec_insn_srl_mem_wmask.eq(insn_srl.spec_mem_wmask) - m.d.comb += spec_insn_srl_mem_wdata.eq(insn_srl.spec_mem_wdata) - - spec_insn_sra_valid = Signal(1) - spec_insn_sra_trap = Signal(1) - spec_insn_sra_rs1_addr = Signal(5) - spec_insn_sra_rs2_addr = Signal(5) - spec_insn_sra_rd_addr = Signal(5) - spec_insn_sra_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sra_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sra_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sra_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sra_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sra_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_sra = insn_sra = rvfi_insn_sra() - m.d.comb += insn_sra.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_sra.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_sra.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_sra.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_sra.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_sra.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_sra_valid.eq(insn_sra.spec_valid) - m.d.comb += spec_insn_sra_trap.eq(insn_sra.spec_trap) - m.d.comb += spec_insn_sra_rs1_addr.eq(insn_sra.spec_rs1_addr) - m.d.comb += spec_insn_sra_rs2_addr.eq(insn_sra.spec_rs2_addr) - m.d.comb += spec_insn_sra_rd_addr.eq(insn_sra.spec_rd_addr) - m.d.comb += spec_insn_sra_rd_wdata.eq(insn_sra.spec_rd_wdata) - m.d.comb += spec_insn_sra_pc_wdata.eq(insn_sra.spec_pc_wdata) - m.d.comb += spec_insn_sra_mem_addr.eq(insn_sra.spec_mem_addr) - m.d.comb += spec_insn_sra_mem_rmask.eq(insn_sra.spec_mem_rmask) - m.d.comb += spec_insn_sra_mem_wmask.eq(insn_sra.spec_mem_wmask) - m.d.comb += spec_insn_sra_mem_wdata.eq(insn_sra.spec_mem_wdata) - - spec_insn_or_valid = Signal(1) - spec_insn_or_trap = Signal(1) - spec_insn_or_rs1_addr = Signal(5) - spec_insn_or_rs2_addr = Signal(5) - spec_insn_or_rd_addr = Signal(5) - spec_insn_or_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_or_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_or_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_or_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_or_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_or_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_or = insn_or = rvfi_insn_or() - m.d.comb += insn_or.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_or.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_or.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_or.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_or.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_or.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_or_valid.eq(insn_or.spec_valid) - m.d.comb += spec_insn_or_trap.eq(insn_or.spec_trap) - m.d.comb += spec_insn_or_rs1_addr.eq(insn_or.spec_rs1_addr) - m.d.comb += spec_insn_or_rs2_addr.eq(insn_or.spec_rs2_addr) - m.d.comb += spec_insn_or_rd_addr.eq(insn_or.spec_rd_addr) - m.d.comb += spec_insn_or_rd_wdata.eq(insn_or.spec_rd_wdata) - m.d.comb += spec_insn_or_pc_wdata.eq(insn_or.spec_pc_wdata) - m.d.comb += spec_insn_or_mem_addr.eq(insn_or.spec_mem_addr) - m.d.comb += spec_insn_or_mem_rmask.eq(insn_or.spec_mem_rmask) - m.d.comb += spec_insn_or_mem_wmask.eq(insn_or.spec_mem_wmask) - m.d.comb += spec_insn_or_mem_wdata.eq(insn_or.spec_mem_wdata) - - spec_insn_and_valid = Signal(1) - spec_insn_and_trap = Signal(1) - spec_insn_and_rs1_addr = Signal(5) - spec_insn_and_rs2_addr = Signal(5) - spec_insn_and_rd_addr = Signal(5) - spec_insn_and_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_and_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_and_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_and_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_and_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_and_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_and = insn_and = rvfi_insn_and() - m.d.comb += insn_and.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_and.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_and.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_and.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_and.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_and.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_and_valid.eq(insn_and.spec_valid) - m.d.comb += spec_insn_and_trap.eq(insn_and.spec_trap) - m.d.comb += spec_insn_and_rs1_addr.eq(insn_and.spec_rs1_addr) - m.d.comb += spec_insn_and_rs2_addr.eq(insn_and.spec_rs2_addr) - m.d.comb += spec_insn_and_rd_addr.eq(insn_and.spec_rd_addr) - m.d.comb += spec_insn_and_rd_wdata.eq(insn_and.spec_rd_wdata) - m.d.comb += spec_insn_and_pc_wdata.eq(insn_and.spec_pc_wdata) - m.d.comb += spec_insn_and_mem_addr.eq(insn_and.spec_mem_addr) - m.d.comb += spec_insn_and_mem_rmask.eq(insn_and.spec_mem_rmask) - m.d.comb += spec_insn_and_mem_wmask.eq(insn_and.spec_mem_wmask) - m.d.comb += spec_insn_and_mem_wdata.eq(insn_and.spec_mem_wdata) - - m.d.comb += self.spec_valid.eq(Mux(spec_insn_and_valid, spec_insn_and_valid, Mux(spec_insn_or_valid, spec_insn_or_valid, Mux(spec_insn_sra_valid, spec_insn_sra_valid, Mux(spec_insn_srl_valid, spec_insn_srl_valid, Mux(spec_insn_xor_valid, spec_insn_xor_valid, Mux(spec_insn_sltu_valid, spec_insn_sltu_valid, Mux(spec_insn_slt_valid, spec_insn_slt_valid, Mux(spec_insn_sll_valid, spec_insn_sll_valid, Mux(spec_insn_sub_valid, spec_insn_sub_valid, Mux(spec_insn_add_valid, spec_insn_add_valid, Mux(spec_insn_srai_valid, spec_insn_srai_valid, Mux(spec_insn_srli_valid, spec_insn_srli_valid, Mux(spec_insn_slli_valid, spec_insn_slli_valid, Mux(spec_insn_andi_valid, spec_insn_andi_valid, Mux(spec_insn_ori_valid, spec_insn_ori_valid, Mux(spec_insn_xori_valid, spec_insn_xori_valid, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_valid, Mux(spec_insn_slti_valid, spec_insn_slti_valid, Mux(spec_insn_addi_valid, spec_insn_addi_valid, Mux(spec_insn_sw_valid, spec_insn_sw_valid, Mux(spec_insn_sh_valid, spec_insn_sh_valid, Mux(spec_insn_sb_valid, spec_insn_sb_valid, Mux(spec_insn_lhu_valid, spec_insn_lhu_valid, Mux(spec_insn_lbu_valid, spec_insn_lbu_valid, Mux(spec_insn_lw_valid, spec_insn_lw_valid, Mux(spec_insn_lh_valid, spec_insn_lh_valid, Mux(spec_insn_lb_valid, spec_insn_lb_valid, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_valid, Mux(spec_insn_bltu_valid, spec_insn_bltu_valid, Mux(spec_insn_bge_valid, spec_insn_bge_valid, Mux(spec_insn_blt_valid, spec_insn_blt_valid, Mux(spec_insn_bne_valid, spec_insn_bne_valid, Mux(spec_insn_beq_valid, spec_insn_beq_valid, Mux(spec_insn_jalr_valid, spec_insn_jalr_valid, Mux(spec_insn_jal_valid, spec_insn_jal_valid, Mux(spec_insn_auipc_valid, spec_insn_auipc_valid, Mux(spec_insn_lui_valid, spec_insn_lui_valid, 0)))))))))))))))))))))))))))))))))))))) - m.d.comb += self.spec_trap.eq(Mux(spec_insn_and_valid, spec_insn_and_trap, Mux(spec_insn_or_valid, spec_insn_or_trap, Mux(spec_insn_sra_valid, spec_insn_sra_trap, Mux(spec_insn_srl_valid, spec_insn_srl_trap, Mux(spec_insn_xor_valid, spec_insn_xor_trap, Mux(spec_insn_sltu_valid, spec_insn_sltu_trap, Mux(spec_insn_slt_valid, spec_insn_slt_trap, Mux(spec_insn_sll_valid, spec_insn_sll_trap, Mux(spec_insn_sub_valid, spec_insn_sub_trap, Mux(spec_insn_add_valid, spec_insn_add_trap, Mux(spec_insn_srai_valid, spec_insn_srai_trap, Mux(spec_insn_srli_valid, spec_insn_srli_trap, Mux(spec_insn_slli_valid, spec_insn_slli_trap, Mux(spec_insn_andi_valid, spec_insn_andi_trap, Mux(spec_insn_ori_valid, spec_insn_ori_trap, Mux(spec_insn_xori_valid, spec_insn_xori_trap, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_trap, Mux(spec_insn_slti_valid, spec_insn_slti_trap, Mux(spec_insn_addi_valid, spec_insn_addi_trap, Mux(spec_insn_sw_valid, spec_insn_sw_trap, Mux(spec_insn_sh_valid, spec_insn_sh_trap, Mux(spec_insn_sb_valid, spec_insn_sb_trap, Mux(spec_insn_lhu_valid, spec_insn_lhu_trap, Mux(spec_insn_lbu_valid, spec_insn_lbu_trap, Mux(spec_insn_lw_valid, spec_insn_lw_trap, Mux(spec_insn_lh_valid, spec_insn_lh_trap, Mux(spec_insn_lb_valid, spec_insn_lb_trap, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_trap, Mux(spec_insn_bltu_valid, spec_insn_bltu_trap, Mux(spec_insn_bge_valid, spec_insn_bge_trap, Mux(spec_insn_blt_valid, spec_insn_blt_trap, Mux(spec_insn_bne_valid, spec_insn_bne_trap, Mux(spec_insn_beq_valid, spec_insn_beq_trap, Mux(spec_insn_jalr_valid, spec_insn_jalr_trap, Mux(spec_insn_jal_valid, spec_insn_jal_trap, Mux(spec_insn_auipc_valid, spec_insn_auipc_trap, Mux(spec_insn_lui_valid, spec_insn_lui_trap, 0)))))))))))))))))))))))))))))))))))))) - m.d.comb += self.spec_rs1_addr.eq(Mux(spec_insn_and_valid, spec_insn_and_rs1_addr, Mux(spec_insn_or_valid, spec_insn_or_rs1_addr, Mux(spec_insn_sra_valid, spec_insn_sra_rs1_addr, Mux(spec_insn_srl_valid, spec_insn_srl_rs1_addr, Mux(spec_insn_xor_valid, spec_insn_xor_rs1_addr, Mux(spec_insn_sltu_valid, spec_insn_sltu_rs1_addr, Mux(spec_insn_slt_valid, spec_insn_slt_rs1_addr, Mux(spec_insn_sll_valid, spec_insn_sll_rs1_addr, Mux(spec_insn_sub_valid, spec_insn_sub_rs1_addr, Mux(spec_insn_add_valid, spec_insn_add_rs1_addr, Mux(spec_insn_srai_valid, spec_insn_srai_rs1_addr, Mux(spec_insn_srli_valid, spec_insn_srli_rs1_addr, Mux(spec_insn_slli_valid, spec_insn_slli_rs1_addr, Mux(spec_insn_andi_valid, spec_insn_andi_rs1_addr, Mux(spec_insn_ori_valid, spec_insn_ori_rs1_addr, Mux(spec_insn_xori_valid, spec_insn_xori_rs1_addr, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_rs1_addr, Mux(spec_insn_slti_valid, spec_insn_slti_rs1_addr, Mux(spec_insn_addi_valid, spec_insn_addi_rs1_addr, Mux(spec_insn_sw_valid, spec_insn_sw_rs1_addr, Mux(spec_insn_sh_valid, spec_insn_sh_rs1_addr, Mux(spec_insn_sb_valid, spec_insn_sb_rs1_addr, Mux(spec_insn_lhu_valid, spec_insn_lhu_rs1_addr, Mux(spec_insn_lbu_valid, spec_insn_lbu_rs1_addr, Mux(spec_insn_lw_valid, spec_insn_lw_rs1_addr, Mux(spec_insn_lh_valid, spec_insn_lh_rs1_addr, Mux(spec_insn_lb_valid, spec_insn_lb_rs1_addr, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_rs1_addr, Mux(spec_insn_bltu_valid, spec_insn_bltu_rs1_addr, Mux(spec_insn_bge_valid, spec_insn_bge_rs1_addr, Mux(spec_insn_blt_valid, spec_insn_blt_rs1_addr, Mux(spec_insn_bne_valid, spec_insn_bne_rs1_addr, Mux(spec_insn_beq_valid, spec_insn_beq_rs1_addr, Mux(spec_insn_jalr_valid, spec_insn_jalr_rs1_addr, Mux(spec_insn_jal_valid, spec_insn_jal_rs1_addr, Mux(spec_insn_auipc_valid, spec_insn_auipc_rs1_addr, Mux(spec_insn_lui_valid, spec_insn_lui_rs1_addr, 0)))))))))))))))))))))))))))))))))))))) - m.d.comb += self.spec_rs2_addr.eq(Mux(spec_insn_and_valid, spec_insn_and_rs2_addr, Mux(spec_insn_or_valid, spec_insn_or_rs2_addr, Mux(spec_insn_sra_valid, spec_insn_sra_rs2_addr, Mux(spec_insn_srl_valid, spec_insn_srl_rs2_addr, Mux(spec_insn_xor_valid, spec_insn_xor_rs2_addr, Mux(spec_insn_sltu_valid, spec_insn_sltu_rs2_addr, Mux(spec_insn_slt_valid, spec_insn_slt_rs2_addr, Mux(spec_insn_sll_valid, spec_insn_sll_rs2_addr, Mux(spec_insn_sub_valid, spec_insn_sub_rs2_addr, Mux(spec_insn_add_valid, spec_insn_add_rs2_addr, Mux(spec_insn_srai_valid, spec_insn_srai_rs2_addr, Mux(spec_insn_srli_valid, spec_insn_srli_rs2_addr, Mux(spec_insn_slli_valid, spec_insn_slli_rs2_addr, Mux(spec_insn_andi_valid, spec_insn_andi_rs2_addr, Mux(spec_insn_ori_valid, spec_insn_ori_rs2_addr, Mux(spec_insn_xori_valid, spec_insn_xori_rs2_addr, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_rs2_addr, Mux(spec_insn_slti_valid, spec_insn_slti_rs2_addr, Mux(spec_insn_addi_valid, spec_insn_addi_rs2_addr, Mux(spec_insn_sw_valid, spec_insn_sw_rs2_addr, Mux(spec_insn_sh_valid, spec_insn_sh_rs2_addr, Mux(spec_insn_sb_valid, spec_insn_sb_rs2_addr, Mux(spec_insn_lhu_valid, spec_insn_lhu_rs2_addr, Mux(spec_insn_lbu_valid, spec_insn_lbu_rs2_addr, Mux(spec_insn_lw_valid, spec_insn_lw_rs2_addr, Mux(spec_insn_lh_valid, spec_insn_lh_rs2_addr, Mux(spec_insn_lb_valid, spec_insn_lb_rs2_addr, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_rs2_addr, Mux(spec_insn_bltu_valid, spec_insn_bltu_rs2_addr, Mux(spec_insn_bge_valid, spec_insn_bge_rs2_addr, Mux(spec_insn_blt_valid, spec_insn_blt_rs2_addr, Mux(spec_insn_bne_valid, spec_insn_bne_rs2_addr, Mux(spec_insn_beq_valid, spec_insn_beq_rs2_addr, Mux(spec_insn_jalr_valid, spec_insn_jalr_rs2_addr, Mux(spec_insn_jal_valid, spec_insn_jal_rs2_addr, Mux(spec_insn_auipc_valid, spec_insn_auipc_rs2_addr, Mux(spec_insn_lui_valid, spec_insn_lui_rs2_addr, 0)))))))))))))))))))))))))))))))))))))) - m.d.comb += self.spec_rd_addr.eq(Mux(spec_insn_and_valid, spec_insn_and_rd_addr, Mux(spec_insn_or_valid, spec_insn_or_rd_addr, Mux(spec_insn_sra_valid, spec_insn_sra_rd_addr, Mux(spec_insn_srl_valid, spec_insn_srl_rd_addr, Mux(spec_insn_xor_valid, spec_insn_xor_rd_addr, Mux(spec_insn_sltu_valid, spec_insn_sltu_rd_addr, Mux(spec_insn_slt_valid, spec_insn_slt_rd_addr, Mux(spec_insn_sll_valid, spec_insn_sll_rd_addr, Mux(spec_insn_sub_valid, spec_insn_sub_rd_addr, Mux(spec_insn_add_valid, spec_insn_add_rd_addr, Mux(spec_insn_srai_valid, spec_insn_srai_rd_addr, Mux(spec_insn_srli_valid, spec_insn_srli_rd_addr, Mux(spec_insn_slli_valid, spec_insn_slli_rd_addr, Mux(spec_insn_andi_valid, spec_insn_andi_rd_addr, Mux(spec_insn_ori_valid, spec_insn_ori_rd_addr, Mux(spec_insn_xori_valid, spec_insn_xori_rd_addr, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_rd_addr, Mux(spec_insn_slti_valid, spec_insn_slti_rd_addr, Mux(spec_insn_addi_valid, spec_insn_addi_rd_addr, Mux(spec_insn_sw_valid, spec_insn_sw_rd_addr, Mux(spec_insn_sh_valid, spec_insn_sh_rd_addr, Mux(spec_insn_sb_valid, spec_insn_sb_rd_addr, Mux(spec_insn_lhu_valid, spec_insn_lhu_rd_addr, Mux(spec_insn_lbu_valid, spec_insn_lbu_rd_addr, Mux(spec_insn_lw_valid, spec_insn_lw_rd_addr, Mux(spec_insn_lh_valid, spec_insn_lh_rd_addr, Mux(spec_insn_lb_valid, spec_insn_lb_rd_addr, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_rd_addr, Mux(spec_insn_bltu_valid, spec_insn_bltu_rd_addr, Mux(spec_insn_bge_valid, spec_insn_bge_rd_addr, Mux(spec_insn_blt_valid, spec_insn_blt_rd_addr, Mux(spec_insn_bne_valid, spec_insn_bne_rd_addr, Mux(spec_insn_beq_valid, spec_insn_beq_rd_addr, Mux(spec_insn_jalr_valid, spec_insn_jalr_rd_addr, Mux(spec_insn_jal_valid, spec_insn_jal_rd_addr, Mux(spec_insn_auipc_valid, spec_insn_auipc_rd_addr, Mux(spec_insn_lui_valid, spec_insn_lui_rd_addr, 0)))))))))))))))))))))))))))))))))))))) - m.d.comb += self.spec_rd_wdata.eq(Mux(spec_insn_and_valid, spec_insn_and_rd_wdata, Mux(spec_insn_or_valid, spec_insn_or_rd_wdata, Mux(spec_insn_sra_valid, spec_insn_sra_rd_wdata, Mux(spec_insn_srl_valid, spec_insn_srl_rd_wdata, Mux(spec_insn_xor_valid, spec_insn_xor_rd_wdata, Mux(spec_insn_sltu_valid, spec_insn_sltu_rd_wdata, Mux(spec_insn_slt_valid, spec_insn_slt_rd_wdata, Mux(spec_insn_sll_valid, spec_insn_sll_rd_wdata, Mux(spec_insn_sub_valid, spec_insn_sub_rd_wdata, Mux(spec_insn_add_valid, spec_insn_add_rd_wdata, Mux(spec_insn_srai_valid, spec_insn_srai_rd_wdata, Mux(spec_insn_srli_valid, spec_insn_srli_rd_wdata, Mux(spec_insn_slli_valid, spec_insn_slli_rd_wdata, Mux(spec_insn_andi_valid, spec_insn_andi_rd_wdata, Mux(spec_insn_ori_valid, spec_insn_ori_rd_wdata, Mux(spec_insn_xori_valid, spec_insn_xori_rd_wdata, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_rd_wdata, Mux(spec_insn_slti_valid, spec_insn_slti_rd_wdata, Mux(spec_insn_addi_valid, spec_insn_addi_rd_wdata, Mux(spec_insn_sw_valid, spec_insn_sw_rd_wdata, Mux(spec_insn_sh_valid, spec_insn_sh_rd_wdata, Mux(spec_insn_sb_valid, spec_insn_sb_rd_wdata, Mux(spec_insn_lhu_valid, spec_insn_lhu_rd_wdata, Mux(spec_insn_lbu_valid, spec_insn_lbu_rd_wdata, Mux(spec_insn_lw_valid, spec_insn_lw_rd_wdata, Mux(spec_insn_lh_valid, spec_insn_lh_rd_wdata, Mux(spec_insn_lb_valid, spec_insn_lb_rd_wdata, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_rd_wdata, Mux(spec_insn_bltu_valid, spec_insn_bltu_rd_wdata, Mux(spec_insn_bge_valid, spec_insn_bge_rd_wdata, Mux(spec_insn_blt_valid, spec_insn_blt_rd_wdata, Mux(spec_insn_bne_valid, spec_insn_bne_rd_wdata, Mux(spec_insn_beq_valid, spec_insn_beq_rd_wdata, Mux(spec_insn_jalr_valid, spec_insn_jalr_rd_wdata, Mux(spec_insn_jal_valid, spec_insn_jal_rd_wdata, Mux(spec_insn_auipc_valid, spec_insn_auipc_rd_wdata, Mux(spec_insn_lui_valid, spec_insn_lui_rd_wdata, 0)))))))))))))))))))))))))))))))))))))) - m.d.comb += self.spec_pc_wdata.eq(Mux(spec_insn_and_valid, spec_insn_and_pc_wdata, Mux(spec_insn_or_valid, spec_insn_or_pc_wdata, Mux(spec_insn_sra_valid, spec_insn_sra_pc_wdata, Mux(spec_insn_srl_valid, spec_insn_srl_pc_wdata, Mux(spec_insn_xor_valid, spec_insn_xor_pc_wdata, Mux(spec_insn_sltu_valid, spec_insn_sltu_pc_wdata, Mux(spec_insn_slt_valid, spec_insn_slt_pc_wdata, Mux(spec_insn_sll_valid, spec_insn_sll_pc_wdata, Mux(spec_insn_sub_valid, spec_insn_sub_pc_wdata, Mux(spec_insn_add_valid, spec_insn_add_pc_wdata, Mux(spec_insn_srai_valid, spec_insn_srai_pc_wdata, Mux(spec_insn_srli_valid, spec_insn_srli_pc_wdata, Mux(spec_insn_slli_valid, spec_insn_slli_pc_wdata, Mux(spec_insn_andi_valid, spec_insn_andi_pc_wdata, Mux(spec_insn_ori_valid, spec_insn_ori_pc_wdata, Mux(spec_insn_xori_valid, spec_insn_xori_pc_wdata, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_pc_wdata, Mux(spec_insn_slti_valid, spec_insn_slti_pc_wdata, Mux(spec_insn_addi_valid, spec_insn_addi_pc_wdata, Mux(spec_insn_sw_valid, spec_insn_sw_pc_wdata, Mux(spec_insn_sh_valid, spec_insn_sh_pc_wdata, Mux(spec_insn_sb_valid, spec_insn_sb_pc_wdata, Mux(spec_insn_lhu_valid, spec_insn_lhu_pc_wdata, Mux(spec_insn_lbu_valid, spec_insn_lbu_pc_wdata, Mux(spec_insn_lw_valid, spec_insn_lw_pc_wdata, Mux(spec_insn_lh_valid, spec_insn_lh_pc_wdata, Mux(spec_insn_lb_valid, spec_insn_lb_pc_wdata, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_pc_wdata, Mux(spec_insn_bltu_valid, spec_insn_bltu_pc_wdata, Mux(spec_insn_bge_valid, spec_insn_bge_pc_wdata, Mux(spec_insn_blt_valid, spec_insn_blt_pc_wdata, Mux(spec_insn_bne_valid, spec_insn_bne_pc_wdata, Mux(spec_insn_beq_valid, spec_insn_beq_pc_wdata, Mux(spec_insn_jalr_valid, spec_insn_jalr_pc_wdata, Mux(spec_insn_jal_valid, spec_insn_jal_pc_wdata, Mux(spec_insn_auipc_valid, spec_insn_auipc_pc_wdata, Mux(spec_insn_lui_valid, spec_insn_lui_pc_wdata, 0)))))))))))))))))))))))))))))))))))))) - m.d.comb += self.spec_mem_addr.eq(Mux(spec_insn_and_valid, spec_insn_and_mem_addr, Mux(spec_insn_or_valid, spec_insn_or_mem_addr, Mux(spec_insn_sra_valid, spec_insn_sra_mem_addr, Mux(spec_insn_srl_valid, spec_insn_srl_mem_addr, Mux(spec_insn_xor_valid, spec_insn_xor_mem_addr, Mux(spec_insn_sltu_valid, spec_insn_sltu_mem_addr, Mux(spec_insn_slt_valid, spec_insn_slt_mem_addr, Mux(spec_insn_sll_valid, spec_insn_sll_mem_addr, Mux(spec_insn_sub_valid, spec_insn_sub_mem_addr, Mux(spec_insn_add_valid, spec_insn_add_mem_addr, Mux(spec_insn_srai_valid, spec_insn_srai_mem_addr, Mux(spec_insn_srli_valid, spec_insn_srli_mem_addr, Mux(spec_insn_slli_valid, spec_insn_slli_mem_addr, Mux(spec_insn_andi_valid, spec_insn_andi_mem_addr, Mux(spec_insn_ori_valid, spec_insn_ori_mem_addr, Mux(spec_insn_xori_valid, spec_insn_xori_mem_addr, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_mem_addr, Mux(spec_insn_slti_valid, spec_insn_slti_mem_addr, Mux(spec_insn_addi_valid, spec_insn_addi_mem_addr, Mux(spec_insn_sw_valid, spec_insn_sw_mem_addr, Mux(spec_insn_sh_valid, spec_insn_sh_mem_addr, Mux(spec_insn_sb_valid, spec_insn_sb_mem_addr, Mux(spec_insn_lhu_valid, spec_insn_lhu_mem_addr, Mux(spec_insn_lbu_valid, spec_insn_lbu_mem_addr, Mux(spec_insn_lw_valid, spec_insn_lw_mem_addr, Mux(spec_insn_lh_valid, spec_insn_lh_mem_addr, Mux(spec_insn_lb_valid, spec_insn_lb_mem_addr, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_mem_addr, Mux(spec_insn_bltu_valid, spec_insn_bltu_mem_addr, Mux(spec_insn_bge_valid, spec_insn_bge_mem_addr, Mux(spec_insn_blt_valid, spec_insn_blt_mem_addr, Mux(spec_insn_bne_valid, spec_insn_bne_mem_addr, Mux(spec_insn_beq_valid, spec_insn_beq_mem_addr, Mux(spec_insn_jalr_valid, spec_insn_jalr_mem_addr, Mux(spec_insn_jal_valid, spec_insn_jal_mem_addr, Mux(spec_insn_auipc_valid, spec_insn_auipc_mem_addr, Mux(spec_insn_lui_valid, spec_insn_lui_mem_addr, 0)))))))))))))))))))))))))))))))))))))) - m.d.comb += self.spec_mem_rmask.eq(Mux(spec_insn_and_valid, spec_insn_and_mem_rmask, Mux(spec_insn_or_valid, spec_insn_or_mem_rmask, Mux(spec_insn_sra_valid, spec_insn_sra_mem_rmask, Mux(spec_insn_srl_valid, spec_insn_srl_mem_rmask, Mux(spec_insn_xor_valid, spec_insn_xor_mem_rmask, Mux(spec_insn_sltu_valid, spec_insn_sltu_mem_rmask, Mux(spec_insn_slt_valid, spec_insn_slt_mem_rmask, Mux(spec_insn_sll_valid, spec_insn_sll_mem_rmask, Mux(spec_insn_sub_valid, spec_insn_sub_mem_rmask, Mux(spec_insn_add_valid, spec_insn_add_mem_rmask, Mux(spec_insn_srai_valid, spec_insn_srai_mem_rmask, Mux(spec_insn_srli_valid, spec_insn_srli_mem_rmask, Mux(spec_insn_slli_valid, spec_insn_slli_mem_rmask, Mux(spec_insn_andi_valid, spec_insn_andi_mem_rmask, Mux(spec_insn_ori_valid, spec_insn_ori_mem_rmask, Mux(spec_insn_xori_valid, spec_insn_xori_mem_rmask, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_mem_rmask, Mux(spec_insn_slti_valid, spec_insn_slti_mem_rmask, Mux(spec_insn_addi_valid, spec_insn_addi_mem_rmask, Mux(spec_insn_sw_valid, spec_insn_sw_mem_rmask, Mux(spec_insn_sh_valid, spec_insn_sh_mem_rmask, Mux(spec_insn_sb_valid, spec_insn_sb_mem_rmask, Mux(spec_insn_lhu_valid, spec_insn_lhu_mem_rmask, Mux(spec_insn_lbu_valid, spec_insn_lbu_mem_rmask, Mux(spec_insn_lw_valid, spec_insn_lw_mem_rmask, Mux(spec_insn_lh_valid, spec_insn_lh_mem_rmask, Mux(spec_insn_lb_valid, spec_insn_lb_mem_rmask, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_mem_rmask, Mux(spec_insn_bltu_valid, spec_insn_bltu_mem_rmask, Mux(spec_insn_bge_valid, spec_insn_bge_mem_rmask, Mux(spec_insn_blt_valid, spec_insn_blt_mem_rmask, Mux(spec_insn_bne_valid, spec_insn_bne_mem_rmask, Mux(spec_insn_beq_valid, spec_insn_beq_mem_rmask, Mux(spec_insn_jalr_valid, spec_insn_jalr_mem_rmask, Mux(spec_insn_jal_valid, spec_insn_jal_mem_rmask, Mux(spec_insn_auipc_valid, spec_insn_auipc_mem_rmask, Mux(spec_insn_lui_valid, spec_insn_lui_mem_rmask, 0)))))))))))))))))))))))))))))))))))))) - m.d.comb += self.spec_mem_wmask.eq(Mux(spec_insn_and_valid, spec_insn_and_mem_wmask, Mux(spec_insn_or_valid, spec_insn_or_mem_wmask, Mux(spec_insn_sra_valid, spec_insn_sra_mem_wmask, Mux(spec_insn_srl_valid, spec_insn_srl_mem_wmask, Mux(spec_insn_xor_valid, spec_insn_xor_mem_wmask, Mux(spec_insn_sltu_valid, spec_insn_sltu_mem_wmask, Mux(spec_insn_slt_valid, spec_insn_slt_mem_wmask, Mux(spec_insn_sll_valid, spec_insn_sll_mem_wmask, Mux(spec_insn_sub_valid, spec_insn_sub_mem_wmask, Mux(spec_insn_add_valid, spec_insn_add_mem_wmask, Mux(spec_insn_srai_valid, spec_insn_srai_mem_wmask, Mux(spec_insn_srli_valid, spec_insn_srli_mem_wmask, Mux(spec_insn_slli_valid, spec_insn_slli_mem_wmask, Mux(spec_insn_andi_valid, spec_insn_andi_mem_wmask, Mux(spec_insn_ori_valid, spec_insn_ori_mem_wmask, Mux(spec_insn_xori_valid, spec_insn_xori_mem_wmask, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_mem_wmask, Mux(spec_insn_slti_valid, spec_insn_slti_mem_wmask, Mux(spec_insn_addi_valid, spec_insn_addi_mem_wmask, Mux(spec_insn_sw_valid, spec_insn_sw_mem_wmask, Mux(spec_insn_sh_valid, spec_insn_sh_mem_wmask, Mux(spec_insn_sb_valid, spec_insn_sb_mem_wmask, Mux(spec_insn_lhu_valid, spec_insn_lhu_mem_wmask, Mux(spec_insn_lbu_valid, spec_insn_lbu_mem_wmask, Mux(spec_insn_lw_valid, spec_insn_lw_mem_wmask, Mux(spec_insn_lh_valid, spec_insn_lh_mem_wmask, Mux(spec_insn_lb_valid, spec_insn_lb_mem_wmask, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_mem_wmask, Mux(spec_insn_bltu_valid, spec_insn_bltu_mem_wmask, Mux(spec_insn_bge_valid, spec_insn_bge_mem_wmask, Mux(spec_insn_blt_valid, spec_insn_blt_mem_wmask, Mux(spec_insn_bne_valid, spec_insn_bne_mem_wmask, Mux(spec_insn_beq_valid, spec_insn_beq_mem_wmask, Mux(spec_insn_jalr_valid, spec_insn_jalr_mem_wmask, Mux(spec_insn_jal_valid, spec_insn_jal_mem_wmask, Mux(spec_insn_auipc_valid, spec_insn_auipc_mem_wmask, Mux(spec_insn_lui_valid, spec_insn_lui_mem_wmask, 0)))))))))))))))))))))))))))))))))))))) - m.d.comb += self.spec_mem_wdata.eq(Mux(spec_insn_and_valid, spec_insn_and_mem_wdata, Mux(spec_insn_or_valid, spec_insn_or_mem_wdata, Mux(spec_insn_sra_valid, spec_insn_sra_mem_wdata, Mux(spec_insn_srl_valid, spec_insn_srl_mem_wdata, Mux(spec_insn_xor_valid, spec_insn_xor_mem_wdata, Mux(spec_insn_sltu_valid, spec_insn_sltu_mem_wdata, Mux(spec_insn_slt_valid, spec_insn_slt_mem_wdata, Mux(spec_insn_sll_valid, spec_insn_sll_mem_wdata, Mux(spec_insn_sub_valid, spec_insn_sub_mem_wdata, Mux(spec_insn_add_valid, spec_insn_add_mem_wdata, Mux(spec_insn_srai_valid, spec_insn_srai_mem_wdata, Mux(spec_insn_srli_valid, spec_insn_srli_mem_wdata, Mux(spec_insn_slli_valid, spec_insn_slli_mem_wdata, Mux(spec_insn_andi_valid, spec_insn_andi_mem_wdata, Mux(spec_insn_ori_valid, spec_insn_ori_mem_wdata, Mux(spec_insn_xori_valid, spec_insn_xori_mem_wdata, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_mem_wdata, Mux(spec_insn_slti_valid, spec_insn_slti_mem_wdata, Mux(spec_insn_addi_valid, spec_insn_addi_mem_wdata, Mux(spec_insn_sw_valid, spec_insn_sw_mem_wdata, Mux(spec_insn_sh_valid, spec_insn_sh_mem_wdata, Mux(spec_insn_sb_valid, spec_insn_sb_mem_wdata, Mux(spec_insn_lhu_valid, spec_insn_lhu_mem_wdata, Mux(spec_insn_lbu_valid, spec_insn_lbu_mem_wdata, Mux(spec_insn_lw_valid, spec_insn_lw_mem_wdata, Mux(spec_insn_lh_valid, spec_insn_lh_mem_wdata, Mux(spec_insn_lb_valid, spec_insn_lb_mem_wdata, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_mem_wdata, Mux(spec_insn_bltu_valid, spec_insn_bltu_mem_wdata, Mux(spec_insn_bge_valid, spec_insn_bge_mem_wdata, Mux(spec_insn_blt_valid, spec_insn_blt_mem_wdata, Mux(spec_insn_bne_valid, spec_insn_bne_mem_wdata, Mux(spec_insn_beq_valid, spec_insn_beq_mem_wdata, Mux(spec_insn_jalr_valid, spec_insn_jalr_mem_wdata, Mux(spec_insn_jal_valid, spec_insn_jal_mem_wdata, Mux(spec_insn_auipc_valid, spec_insn_auipc_mem_wdata, Mux(spec_insn_lui_valid, spec_insn_lui_mem_wdata, 0)))))))))))))))))))))))))))))))))))))) - - return m diff --git a/insns/isa_rv32i.txt b/insns/isa_rv32i.txt deleted file mode 100644 index ad4c10b..0000000 --- a/insns/isa_rv32i.txt +++ /dev/null @@ -1,37 +0,0 @@ -lui -auipc -jal -jalr -beq -bne -blt -bge -bltu -bgeu -lb -lh -lw -lbu -lhu -sb -sh -sw -addi -slti -sltiu -xori -ori -andi -slli -srli -srai -add -sub -sll -slt -sltu -xor -srl -sra -or -and diff --git a/insns/isa_rv32i_gen.py b/insns/isa_rv32i_gen.py deleted file mode 100644 index 8c692b1..0000000 --- a/insns/isa_rv32i_gen.py +++ /dev/null @@ -1,107 +0,0 @@ -with open('isa_rv32i.py', 'w') as isa_rv32i: - def fprint(strng): - print(strng, file=isa_rv32i) - fprint("# Generated by isa_rv32i_gen.py") - fprint("from nmigen import *") - with open('isa_rv32i.txt', 'r') as isa_rv32i_txt_file: - isa_rv32i_insns = isa_rv32i_txt_file.read().split('\n')[:-1] - for isa_rv32i_insn in isa_rv32i_insns: - fprint("from insn_%s import *" % isa_rv32i_insn) - fprint("") - fprint("class rvfi_isa_rv32i(Elaboratable):") - fprint(" def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):") - fprint(" self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN") - fprint(" self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN") - fprint(" self.rvfi_valid = Signal(1)") - fprint(" self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)") - fprint(" self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)") - fprint(" self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)") - fprint(" self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)") - fprint(" self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)") - fprint("") - fprint(" self.spec_valid = Signal(1)") - fprint(" self.spec_trap = Signal(1)") - fprint(" self.spec_rs1_addr = Signal(5)") - fprint(" self.spec_rs2_addr = Signal(5)") - fprint(" self.spec_rd_addr = Signal(5)") - fprint(" self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)") - fprint(" self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)") - fprint(" self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)") - fprint(" self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))") - fprint(" self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))") - fprint(" self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)") - fprint(" def ports(self):") - fprint(" input_ports = [") - fprint(" self.rvfi_valid,") - fprint(" self.rvfi_insn,") - fprint(" self.rvfi_pc_rdata,") - fprint(" self.rvfi_rs1_rdata,") - fprint(" self.rvfi_rs2_rdata,") - fprint(" self.rvfi_mem_rdata") - fprint(" ]") - fprint(" output_ports = [") - fprint(" self.spec_valid,") - fprint(" self.spec_trap,") - fprint(" self.spec_rs1_addr,") - fprint(" self.spec_rs2_addr,") - fprint(" self.spec_rd_addr,") - fprint(" self.spec_rd_wdata,") - fprint(" self.spec_pc_wdata,") - fprint(" self.spec_mem_addr,") - fprint(" self.spec_mem_rmask,") - fprint(" self.spec_mem_wmask,") - fprint(" self.spec_mem_wdata") - fprint(" ]") - fprint(" return input_ports + output_ports") - fprint(" def elaborate(self, platform):") - fprint(" m = Module()") - fprint("") - for isa_rv32i_insn in isa_rv32i_insns: - fprint(" spec_insn_%s_valid = Signal(1)" % isa_rv32i_insn) - fprint(" spec_insn_%s_trap = Signal(1)" % isa_rv32i_insn) - fprint(" spec_insn_%s_rs1_addr = Signal(5)" % isa_rv32i_insn) - fprint(" spec_insn_%s_rs2_addr = Signal(5)" % isa_rv32i_insn) - fprint(" spec_insn_%s_rd_addr = Signal(5)" % isa_rv32i_insn) - fprint(" spec_insn_%s_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)" % isa_rv32i_insn) - fprint(" spec_insn_%s_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)" % isa_rv32i_insn) - fprint(" spec_insn_%s_mem_addr = Signal(self.RISCV_FORMAL_XLEN)" % isa_rv32i_insn) - fprint(" spec_insn_%s_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))" % isa_rv32i_insn) - fprint(" spec_insn_%s_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))" % isa_rv32i_insn) - fprint(" spec_insn_%s_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)" % isa_rv32i_insn) - fprint(" m.submodules.insn_%s = insn_%s = rvfi_insn_%s()" % (isa_rv32i_insn, isa_rv32i_insn, isa_rv32i_insn)) - fprint(" m.d.comb += insn_%s.rvfi_valid.eq(self.rvfi_valid)" % isa_rv32i_insn) - fprint(" m.d.comb += insn_%s.rvfi_insn.eq(self.rvfi_insn)" % isa_rv32i_insn) - fprint(" m.d.comb += insn_%s.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)" % isa_rv32i_insn) - fprint(" m.d.comb += insn_%s.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)" % isa_rv32i_insn) - fprint(" m.d.comb += insn_%s.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)" % isa_rv32i_insn) - fprint(" m.d.comb += insn_%s.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)" % isa_rv32i_insn) - fprint(" m.d.comb += spec_insn_%s_valid.eq(insn_%s.spec_valid)" % (isa_rv32i_insn, isa_rv32i_insn)) - fprint(" m.d.comb += spec_insn_%s_trap.eq(insn_%s.spec_trap)" % (isa_rv32i_insn, isa_rv32i_insn)) - fprint(" m.d.comb += spec_insn_%s_rs1_addr.eq(insn_%s.spec_rs1_addr)" % (isa_rv32i_insn, isa_rv32i_insn)) - fprint(" m.d.comb += spec_insn_%s_rs2_addr.eq(insn_%s.spec_rs2_addr)" % (isa_rv32i_insn, isa_rv32i_insn)) - fprint(" m.d.comb += spec_insn_%s_rd_addr.eq(insn_%s.spec_rd_addr)" % (isa_rv32i_insn, isa_rv32i_insn)) - fprint(" m.d.comb += spec_insn_%s_rd_wdata.eq(insn_%s.spec_rd_wdata)" % (isa_rv32i_insn, isa_rv32i_insn)) - fprint(" m.d.comb += spec_insn_%s_pc_wdata.eq(insn_%s.spec_pc_wdata)" % (isa_rv32i_insn, isa_rv32i_insn)) - fprint(" m.d.comb += spec_insn_%s_mem_addr.eq(insn_%s.spec_mem_addr)" % (isa_rv32i_insn, isa_rv32i_insn)) - fprint(" m.d.comb += spec_insn_%s_mem_rmask.eq(insn_%s.spec_mem_rmask)" % (isa_rv32i_insn, isa_rv32i_insn)) - fprint(" m.d.comb += spec_insn_%s_mem_wmask.eq(insn_%s.spec_mem_wmask)" % (isa_rv32i_insn, isa_rv32i_insn)) - fprint(" m.d.comb += spec_insn_%s_mem_wdata.eq(insn_%s.spec_mem_wdata)" % (isa_rv32i_insn, isa_rv32i_insn)) - fprint("") - def gen_spec(strng): - result = "0" - for isa_rv32i_insn in isa_rv32i_insns: - result = "Mux(spec_insn_%s_valid, spec_insn_%s_%s, %s)" % (isa_rv32i_insn, isa_rv32i_insn, strng, result) - fprint(" m.d.comb += self.spec_%s.eq(%s)" % (strng, result)) - gen_spec("valid") - gen_spec("trap") - gen_spec("rs1_addr") - gen_spec("rs2_addr") - gen_spec("rd_addr") - gen_spec("rd_wdata") - gen_spec("pc_wdata") - gen_spec("mem_addr") - gen_spec("mem_rmask") - gen_spec("mem_wmask") - gen_spec("mem_wdata") - fprint("") - fprint(" return m") diff --git a/insns/isa_rv32im.py b/insns/isa_rv32im.py deleted file mode 100644 index 40fba37..0000000 --- a/insns/isa_rv32im.py +++ /dev/null @@ -1,1459 +0,0 @@ -# Generated by isa_rv32im_gen.py -from nmigen import * -from insn_lui import * -from insn_auipc import * -from insn_jal import * -from insn_jalr import * -from insn_beq import * -from insn_bne import * -from insn_blt import * -from insn_bge import * -from insn_bltu import * -from insn_bgeu import * -from insn_lb import * -from insn_lh import * -from insn_lw import * -from insn_lbu import * -from insn_lhu import * -from insn_sb import * -from insn_sh import * -from insn_sw import * -from insn_addi import * -from insn_slti import * -from insn_sltiu import * -from insn_xori import * -from insn_ori import * -from insn_andi import * -from insn_slli import * -from insn_srli import * -from insn_srai import * -from insn_add import * -from insn_sub import * -from insn_sll import * -from insn_slt import * -from insn_sltu import * -from insn_xor import * -from insn_srl import * -from insn_sra import * -from insn_or import * -from insn_and import * -from insn_mul import * -from insn_mulh import * -from insn_mulhsu import * -from insn_mulhu import * -from insn_div import * -from insn_divu import * -from insn_rem import * -from insn_remu import * - -class rvfi_isa_rv32im(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - spec_insn_lui_valid = Signal(1) - spec_insn_lui_trap = Signal(1) - spec_insn_lui_rs1_addr = Signal(5) - spec_insn_lui_rs2_addr = Signal(5) - spec_insn_lui_rd_addr = Signal(5) - spec_insn_lui_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lui_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lui_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lui_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lui_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lui_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_lui = insn_lui = rvfi_insn_lui() - m.d.comb += insn_lui.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_lui.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_lui.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_lui.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_lui.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_lui.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_lui_valid.eq(insn_lui.spec_valid) - m.d.comb += spec_insn_lui_trap.eq(insn_lui.spec_trap) - m.d.comb += spec_insn_lui_rs1_addr.eq(insn_lui.spec_rs1_addr) - m.d.comb += spec_insn_lui_rs2_addr.eq(insn_lui.spec_rs2_addr) - m.d.comb += spec_insn_lui_rd_addr.eq(insn_lui.spec_rd_addr) - m.d.comb += spec_insn_lui_rd_wdata.eq(insn_lui.spec_rd_wdata) - m.d.comb += spec_insn_lui_pc_wdata.eq(insn_lui.spec_pc_wdata) - m.d.comb += spec_insn_lui_mem_addr.eq(insn_lui.spec_mem_addr) - m.d.comb += spec_insn_lui_mem_rmask.eq(insn_lui.spec_mem_rmask) - m.d.comb += spec_insn_lui_mem_wmask.eq(insn_lui.spec_mem_wmask) - m.d.comb += spec_insn_lui_mem_wdata.eq(insn_lui.spec_mem_wdata) - - spec_insn_auipc_valid = Signal(1) - spec_insn_auipc_trap = Signal(1) - spec_insn_auipc_rs1_addr = Signal(5) - spec_insn_auipc_rs2_addr = Signal(5) - spec_insn_auipc_rd_addr = Signal(5) - spec_insn_auipc_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_auipc_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_auipc_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_auipc_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_auipc_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_auipc_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_auipc = insn_auipc = rvfi_insn_auipc() - m.d.comb += insn_auipc.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_auipc.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_auipc.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_auipc.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_auipc.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_auipc.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_auipc_valid.eq(insn_auipc.spec_valid) - m.d.comb += spec_insn_auipc_trap.eq(insn_auipc.spec_trap) - m.d.comb += spec_insn_auipc_rs1_addr.eq(insn_auipc.spec_rs1_addr) - m.d.comb += spec_insn_auipc_rs2_addr.eq(insn_auipc.spec_rs2_addr) - m.d.comb += spec_insn_auipc_rd_addr.eq(insn_auipc.spec_rd_addr) - m.d.comb += spec_insn_auipc_rd_wdata.eq(insn_auipc.spec_rd_wdata) - m.d.comb += spec_insn_auipc_pc_wdata.eq(insn_auipc.spec_pc_wdata) - m.d.comb += spec_insn_auipc_mem_addr.eq(insn_auipc.spec_mem_addr) - m.d.comb += spec_insn_auipc_mem_rmask.eq(insn_auipc.spec_mem_rmask) - m.d.comb += spec_insn_auipc_mem_wmask.eq(insn_auipc.spec_mem_wmask) - m.d.comb += spec_insn_auipc_mem_wdata.eq(insn_auipc.spec_mem_wdata) - - spec_insn_jal_valid = Signal(1) - spec_insn_jal_trap = Signal(1) - spec_insn_jal_rs1_addr = Signal(5) - spec_insn_jal_rs2_addr = Signal(5) - spec_insn_jal_rd_addr = Signal(5) - spec_insn_jal_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_jal_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_jal_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_jal_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_jal_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_jal_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_jal = insn_jal = rvfi_insn_jal() - m.d.comb += insn_jal.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_jal.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_jal.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_jal.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_jal.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_jal.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_jal_valid.eq(insn_jal.spec_valid) - m.d.comb += spec_insn_jal_trap.eq(insn_jal.spec_trap) - m.d.comb += spec_insn_jal_rs1_addr.eq(insn_jal.spec_rs1_addr) - m.d.comb += spec_insn_jal_rs2_addr.eq(insn_jal.spec_rs2_addr) - m.d.comb += spec_insn_jal_rd_addr.eq(insn_jal.spec_rd_addr) - m.d.comb += spec_insn_jal_rd_wdata.eq(insn_jal.spec_rd_wdata) - m.d.comb += spec_insn_jal_pc_wdata.eq(insn_jal.spec_pc_wdata) - m.d.comb += spec_insn_jal_mem_addr.eq(insn_jal.spec_mem_addr) - m.d.comb += spec_insn_jal_mem_rmask.eq(insn_jal.spec_mem_rmask) - m.d.comb += spec_insn_jal_mem_wmask.eq(insn_jal.spec_mem_wmask) - m.d.comb += spec_insn_jal_mem_wdata.eq(insn_jal.spec_mem_wdata) - - spec_insn_jalr_valid = Signal(1) - spec_insn_jalr_trap = Signal(1) - spec_insn_jalr_rs1_addr = Signal(5) - spec_insn_jalr_rs2_addr = Signal(5) - spec_insn_jalr_rd_addr = Signal(5) - spec_insn_jalr_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_jalr_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_jalr_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_jalr_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_jalr_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_jalr_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_jalr = insn_jalr = rvfi_insn_jalr() - m.d.comb += insn_jalr.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_jalr.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_jalr.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_jalr.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_jalr.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_jalr.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_jalr_valid.eq(insn_jalr.spec_valid) - m.d.comb += spec_insn_jalr_trap.eq(insn_jalr.spec_trap) - m.d.comb += spec_insn_jalr_rs1_addr.eq(insn_jalr.spec_rs1_addr) - m.d.comb += spec_insn_jalr_rs2_addr.eq(insn_jalr.spec_rs2_addr) - m.d.comb += spec_insn_jalr_rd_addr.eq(insn_jalr.spec_rd_addr) - m.d.comb += spec_insn_jalr_rd_wdata.eq(insn_jalr.spec_rd_wdata) - m.d.comb += spec_insn_jalr_pc_wdata.eq(insn_jalr.spec_pc_wdata) - m.d.comb += spec_insn_jalr_mem_addr.eq(insn_jalr.spec_mem_addr) - m.d.comb += spec_insn_jalr_mem_rmask.eq(insn_jalr.spec_mem_rmask) - m.d.comb += spec_insn_jalr_mem_wmask.eq(insn_jalr.spec_mem_wmask) - m.d.comb += spec_insn_jalr_mem_wdata.eq(insn_jalr.spec_mem_wdata) - - spec_insn_beq_valid = Signal(1) - spec_insn_beq_trap = Signal(1) - spec_insn_beq_rs1_addr = Signal(5) - spec_insn_beq_rs2_addr = Signal(5) - spec_insn_beq_rd_addr = Signal(5) - spec_insn_beq_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_beq_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_beq_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_beq_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_beq_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_beq_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_beq = insn_beq = rvfi_insn_beq() - m.d.comb += insn_beq.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_beq.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_beq.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_beq.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_beq.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_beq.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_beq_valid.eq(insn_beq.spec_valid) - m.d.comb += spec_insn_beq_trap.eq(insn_beq.spec_trap) - m.d.comb += spec_insn_beq_rs1_addr.eq(insn_beq.spec_rs1_addr) - m.d.comb += spec_insn_beq_rs2_addr.eq(insn_beq.spec_rs2_addr) - m.d.comb += spec_insn_beq_rd_addr.eq(insn_beq.spec_rd_addr) - m.d.comb += spec_insn_beq_rd_wdata.eq(insn_beq.spec_rd_wdata) - m.d.comb += spec_insn_beq_pc_wdata.eq(insn_beq.spec_pc_wdata) - m.d.comb += spec_insn_beq_mem_addr.eq(insn_beq.spec_mem_addr) - m.d.comb += spec_insn_beq_mem_rmask.eq(insn_beq.spec_mem_rmask) - m.d.comb += spec_insn_beq_mem_wmask.eq(insn_beq.spec_mem_wmask) - m.d.comb += spec_insn_beq_mem_wdata.eq(insn_beq.spec_mem_wdata) - - spec_insn_bne_valid = Signal(1) - spec_insn_bne_trap = Signal(1) - spec_insn_bne_rs1_addr = Signal(5) - spec_insn_bne_rs2_addr = Signal(5) - spec_insn_bne_rd_addr = Signal(5) - spec_insn_bne_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bne_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bne_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bne_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_bne_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_bne_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_bne = insn_bne = rvfi_insn_bne() - m.d.comb += insn_bne.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_bne.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_bne.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_bne.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_bne.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_bne.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_bne_valid.eq(insn_bne.spec_valid) - m.d.comb += spec_insn_bne_trap.eq(insn_bne.spec_trap) - m.d.comb += spec_insn_bne_rs1_addr.eq(insn_bne.spec_rs1_addr) - m.d.comb += spec_insn_bne_rs2_addr.eq(insn_bne.spec_rs2_addr) - m.d.comb += spec_insn_bne_rd_addr.eq(insn_bne.spec_rd_addr) - m.d.comb += spec_insn_bne_rd_wdata.eq(insn_bne.spec_rd_wdata) - m.d.comb += spec_insn_bne_pc_wdata.eq(insn_bne.spec_pc_wdata) - m.d.comb += spec_insn_bne_mem_addr.eq(insn_bne.spec_mem_addr) - m.d.comb += spec_insn_bne_mem_rmask.eq(insn_bne.spec_mem_rmask) - m.d.comb += spec_insn_bne_mem_wmask.eq(insn_bne.spec_mem_wmask) - m.d.comb += spec_insn_bne_mem_wdata.eq(insn_bne.spec_mem_wdata) - - spec_insn_blt_valid = Signal(1) - spec_insn_blt_trap = Signal(1) - spec_insn_blt_rs1_addr = Signal(5) - spec_insn_blt_rs2_addr = Signal(5) - spec_insn_blt_rd_addr = Signal(5) - spec_insn_blt_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_blt_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_blt_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_blt_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_blt_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_blt_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_blt = insn_blt = rvfi_insn_blt() - m.d.comb += insn_blt.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_blt.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_blt.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_blt.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_blt.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_blt.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_blt_valid.eq(insn_blt.spec_valid) - m.d.comb += spec_insn_blt_trap.eq(insn_blt.spec_trap) - m.d.comb += spec_insn_blt_rs1_addr.eq(insn_blt.spec_rs1_addr) - m.d.comb += spec_insn_blt_rs2_addr.eq(insn_blt.spec_rs2_addr) - m.d.comb += spec_insn_blt_rd_addr.eq(insn_blt.spec_rd_addr) - m.d.comb += spec_insn_blt_rd_wdata.eq(insn_blt.spec_rd_wdata) - m.d.comb += spec_insn_blt_pc_wdata.eq(insn_blt.spec_pc_wdata) - m.d.comb += spec_insn_blt_mem_addr.eq(insn_blt.spec_mem_addr) - m.d.comb += spec_insn_blt_mem_rmask.eq(insn_blt.spec_mem_rmask) - m.d.comb += spec_insn_blt_mem_wmask.eq(insn_blt.spec_mem_wmask) - m.d.comb += spec_insn_blt_mem_wdata.eq(insn_blt.spec_mem_wdata) - - spec_insn_bge_valid = Signal(1) - spec_insn_bge_trap = Signal(1) - spec_insn_bge_rs1_addr = Signal(5) - spec_insn_bge_rs2_addr = Signal(5) - spec_insn_bge_rd_addr = Signal(5) - spec_insn_bge_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bge_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bge_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bge_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_bge_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_bge_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_bge = insn_bge = rvfi_insn_bge() - m.d.comb += insn_bge.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_bge.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_bge.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_bge.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_bge.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_bge.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_bge_valid.eq(insn_bge.spec_valid) - m.d.comb += spec_insn_bge_trap.eq(insn_bge.spec_trap) - m.d.comb += spec_insn_bge_rs1_addr.eq(insn_bge.spec_rs1_addr) - m.d.comb += spec_insn_bge_rs2_addr.eq(insn_bge.spec_rs2_addr) - m.d.comb += spec_insn_bge_rd_addr.eq(insn_bge.spec_rd_addr) - m.d.comb += spec_insn_bge_rd_wdata.eq(insn_bge.spec_rd_wdata) - m.d.comb += spec_insn_bge_pc_wdata.eq(insn_bge.spec_pc_wdata) - m.d.comb += spec_insn_bge_mem_addr.eq(insn_bge.spec_mem_addr) - m.d.comb += spec_insn_bge_mem_rmask.eq(insn_bge.spec_mem_rmask) - m.d.comb += spec_insn_bge_mem_wmask.eq(insn_bge.spec_mem_wmask) - m.d.comb += spec_insn_bge_mem_wdata.eq(insn_bge.spec_mem_wdata) - - spec_insn_bltu_valid = Signal(1) - spec_insn_bltu_trap = Signal(1) - spec_insn_bltu_rs1_addr = Signal(5) - spec_insn_bltu_rs2_addr = Signal(5) - spec_insn_bltu_rd_addr = Signal(5) - spec_insn_bltu_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bltu_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bltu_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bltu_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_bltu_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_bltu_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_bltu = insn_bltu = rvfi_insn_bltu() - m.d.comb += insn_bltu.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_bltu.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_bltu.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_bltu.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_bltu.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_bltu.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_bltu_valid.eq(insn_bltu.spec_valid) - m.d.comb += spec_insn_bltu_trap.eq(insn_bltu.spec_trap) - m.d.comb += spec_insn_bltu_rs1_addr.eq(insn_bltu.spec_rs1_addr) - m.d.comb += spec_insn_bltu_rs2_addr.eq(insn_bltu.spec_rs2_addr) - m.d.comb += spec_insn_bltu_rd_addr.eq(insn_bltu.spec_rd_addr) - m.d.comb += spec_insn_bltu_rd_wdata.eq(insn_bltu.spec_rd_wdata) - m.d.comb += spec_insn_bltu_pc_wdata.eq(insn_bltu.spec_pc_wdata) - m.d.comb += spec_insn_bltu_mem_addr.eq(insn_bltu.spec_mem_addr) - m.d.comb += spec_insn_bltu_mem_rmask.eq(insn_bltu.spec_mem_rmask) - m.d.comb += spec_insn_bltu_mem_wmask.eq(insn_bltu.spec_mem_wmask) - m.d.comb += spec_insn_bltu_mem_wdata.eq(insn_bltu.spec_mem_wdata) - - spec_insn_bgeu_valid = Signal(1) - spec_insn_bgeu_trap = Signal(1) - spec_insn_bgeu_rs1_addr = Signal(5) - spec_insn_bgeu_rs2_addr = Signal(5) - spec_insn_bgeu_rd_addr = Signal(5) - spec_insn_bgeu_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bgeu_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bgeu_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_bgeu_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_bgeu_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_bgeu_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_bgeu = insn_bgeu = rvfi_insn_bgeu() - m.d.comb += insn_bgeu.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_bgeu.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_bgeu.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_bgeu.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_bgeu.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_bgeu.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_bgeu_valid.eq(insn_bgeu.spec_valid) - m.d.comb += spec_insn_bgeu_trap.eq(insn_bgeu.spec_trap) - m.d.comb += spec_insn_bgeu_rs1_addr.eq(insn_bgeu.spec_rs1_addr) - m.d.comb += spec_insn_bgeu_rs2_addr.eq(insn_bgeu.spec_rs2_addr) - m.d.comb += spec_insn_bgeu_rd_addr.eq(insn_bgeu.spec_rd_addr) - m.d.comb += spec_insn_bgeu_rd_wdata.eq(insn_bgeu.spec_rd_wdata) - m.d.comb += spec_insn_bgeu_pc_wdata.eq(insn_bgeu.spec_pc_wdata) - m.d.comb += spec_insn_bgeu_mem_addr.eq(insn_bgeu.spec_mem_addr) - m.d.comb += spec_insn_bgeu_mem_rmask.eq(insn_bgeu.spec_mem_rmask) - m.d.comb += spec_insn_bgeu_mem_wmask.eq(insn_bgeu.spec_mem_wmask) - m.d.comb += spec_insn_bgeu_mem_wdata.eq(insn_bgeu.spec_mem_wdata) - - spec_insn_lb_valid = Signal(1) - spec_insn_lb_trap = Signal(1) - spec_insn_lb_rs1_addr = Signal(5) - spec_insn_lb_rs2_addr = Signal(5) - spec_insn_lb_rd_addr = Signal(5) - spec_insn_lb_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lb_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lb_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lb_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lb_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lb_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_lb = insn_lb = rvfi_insn_lb() - m.d.comb += insn_lb.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_lb.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_lb.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_lb.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_lb.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_lb.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_lb_valid.eq(insn_lb.spec_valid) - m.d.comb += spec_insn_lb_trap.eq(insn_lb.spec_trap) - m.d.comb += spec_insn_lb_rs1_addr.eq(insn_lb.spec_rs1_addr) - m.d.comb += spec_insn_lb_rs2_addr.eq(insn_lb.spec_rs2_addr) - m.d.comb += spec_insn_lb_rd_addr.eq(insn_lb.spec_rd_addr) - m.d.comb += spec_insn_lb_rd_wdata.eq(insn_lb.spec_rd_wdata) - m.d.comb += spec_insn_lb_pc_wdata.eq(insn_lb.spec_pc_wdata) - m.d.comb += spec_insn_lb_mem_addr.eq(insn_lb.spec_mem_addr) - m.d.comb += spec_insn_lb_mem_rmask.eq(insn_lb.spec_mem_rmask) - m.d.comb += spec_insn_lb_mem_wmask.eq(insn_lb.spec_mem_wmask) - m.d.comb += spec_insn_lb_mem_wdata.eq(insn_lb.spec_mem_wdata) - - spec_insn_lh_valid = Signal(1) - spec_insn_lh_trap = Signal(1) - spec_insn_lh_rs1_addr = Signal(5) - spec_insn_lh_rs2_addr = Signal(5) - spec_insn_lh_rd_addr = Signal(5) - spec_insn_lh_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lh_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lh_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lh_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lh_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lh_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_lh = insn_lh = rvfi_insn_lh() - m.d.comb += insn_lh.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_lh.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_lh.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_lh.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_lh.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_lh.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_lh_valid.eq(insn_lh.spec_valid) - m.d.comb += spec_insn_lh_trap.eq(insn_lh.spec_trap) - m.d.comb += spec_insn_lh_rs1_addr.eq(insn_lh.spec_rs1_addr) - m.d.comb += spec_insn_lh_rs2_addr.eq(insn_lh.spec_rs2_addr) - m.d.comb += spec_insn_lh_rd_addr.eq(insn_lh.spec_rd_addr) - m.d.comb += spec_insn_lh_rd_wdata.eq(insn_lh.spec_rd_wdata) - m.d.comb += spec_insn_lh_pc_wdata.eq(insn_lh.spec_pc_wdata) - m.d.comb += spec_insn_lh_mem_addr.eq(insn_lh.spec_mem_addr) - m.d.comb += spec_insn_lh_mem_rmask.eq(insn_lh.spec_mem_rmask) - m.d.comb += spec_insn_lh_mem_wmask.eq(insn_lh.spec_mem_wmask) - m.d.comb += spec_insn_lh_mem_wdata.eq(insn_lh.spec_mem_wdata) - - spec_insn_lw_valid = Signal(1) - spec_insn_lw_trap = Signal(1) - spec_insn_lw_rs1_addr = Signal(5) - spec_insn_lw_rs2_addr = Signal(5) - spec_insn_lw_rd_addr = Signal(5) - spec_insn_lw_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lw_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lw_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lw_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lw_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lw_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_lw = insn_lw = rvfi_insn_lw() - m.d.comb += insn_lw.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_lw.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_lw.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_lw.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_lw.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_lw.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_lw_valid.eq(insn_lw.spec_valid) - m.d.comb += spec_insn_lw_trap.eq(insn_lw.spec_trap) - m.d.comb += spec_insn_lw_rs1_addr.eq(insn_lw.spec_rs1_addr) - m.d.comb += spec_insn_lw_rs2_addr.eq(insn_lw.spec_rs2_addr) - m.d.comb += spec_insn_lw_rd_addr.eq(insn_lw.spec_rd_addr) - m.d.comb += spec_insn_lw_rd_wdata.eq(insn_lw.spec_rd_wdata) - m.d.comb += spec_insn_lw_pc_wdata.eq(insn_lw.spec_pc_wdata) - m.d.comb += spec_insn_lw_mem_addr.eq(insn_lw.spec_mem_addr) - m.d.comb += spec_insn_lw_mem_rmask.eq(insn_lw.spec_mem_rmask) - m.d.comb += spec_insn_lw_mem_wmask.eq(insn_lw.spec_mem_wmask) - m.d.comb += spec_insn_lw_mem_wdata.eq(insn_lw.spec_mem_wdata) - - spec_insn_lbu_valid = Signal(1) - spec_insn_lbu_trap = Signal(1) - spec_insn_lbu_rs1_addr = Signal(5) - spec_insn_lbu_rs2_addr = Signal(5) - spec_insn_lbu_rd_addr = Signal(5) - spec_insn_lbu_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lbu_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lbu_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lbu_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lbu_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lbu_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_lbu = insn_lbu = rvfi_insn_lbu() - m.d.comb += insn_lbu.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_lbu.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_lbu.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_lbu.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_lbu.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_lbu.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_lbu_valid.eq(insn_lbu.spec_valid) - m.d.comb += spec_insn_lbu_trap.eq(insn_lbu.spec_trap) - m.d.comb += spec_insn_lbu_rs1_addr.eq(insn_lbu.spec_rs1_addr) - m.d.comb += spec_insn_lbu_rs2_addr.eq(insn_lbu.spec_rs2_addr) - m.d.comb += spec_insn_lbu_rd_addr.eq(insn_lbu.spec_rd_addr) - m.d.comb += spec_insn_lbu_rd_wdata.eq(insn_lbu.spec_rd_wdata) - m.d.comb += spec_insn_lbu_pc_wdata.eq(insn_lbu.spec_pc_wdata) - m.d.comb += spec_insn_lbu_mem_addr.eq(insn_lbu.spec_mem_addr) - m.d.comb += spec_insn_lbu_mem_rmask.eq(insn_lbu.spec_mem_rmask) - m.d.comb += spec_insn_lbu_mem_wmask.eq(insn_lbu.spec_mem_wmask) - m.d.comb += spec_insn_lbu_mem_wdata.eq(insn_lbu.spec_mem_wdata) - - spec_insn_lhu_valid = Signal(1) - spec_insn_lhu_trap = Signal(1) - spec_insn_lhu_rs1_addr = Signal(5) - spec_insn_lhu_rs2_addr = Signal(5) - spec_insn_lhu_rd_addr = Signal(5) - spec_insn_lhu_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lhu_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lhu_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_lhu_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lhu_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_lhu_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_lhu = insn_lhu = rvfi_insn_lhu() - m.d.comb += insn_lhu.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_lhu.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_lhu.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_lhu.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_lhu.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_lhu.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_lhu_valid.eq(insn_lhu.spec_valid) - m.d.comb += spec_insn_lhu_trap.eq(insn_lhu.spec_trap) - m.d.comb += spec_insn_lhu_rs1_addr.eq(insn_lhu.spec_rs1_addr) - m.d.comb += spec_insn_lhu_rs2_addr.eq(insn_lhu.spec_rs2_addr) - m.d.comb += spec_insn_lhu_rd_addr.eq(insn_lhu.spec_rd_addr) - m.d.comb += spec_insn_lhu_rd_wdata.eq(insn_lhu.spec_rd_wdata) - m.d.comb += spec_insn_lhu_pc_wdata.eq(insn_lhu.spec_pc_wdata) - m.d.comb += spec_insn_lhu_mem_addr.eq(insn_lhu.spec_mem_addr) - m.d.comb += spec_insn_lhu_mem_rmask.eq(insn_lhu.spec_mem_rmask) - m.d.comb += spec_insn_lhu_mem_wmask.eq(insn_lhu.spec_mem_wmask) - m.d.comb += spec_insn_lhu_mem_wdata.eq(insn_lhu.spec_mem_wdata) - - spec_insn_sb_valid = Signal(1) - spec_insn_sb_trap = Signal(1) - spec_insn_sb_rs1_addr = Signal(5) - spec_insn_sb_rs2_addr = Signal(5) - spec_insn_sb_rd_addr = Signal(5) - spec_insn_sb_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sb_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sb_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sb_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sb_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sb_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_sb = insn_sb = rvfi_insn_sb() - m.d.comb += insn_sb.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_sb.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_sb.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_sb.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_sb.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_sb.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_sb_valid.eq(insn_sb.spec_valid) - m.d.comb += spec_insn_sb_trap.eq(insn_sb.spec_trap) - m.d.comb += spec_insn_sb_rs1_addr.eq(insn_sb.spec_rs1_addr) - m.d.comb += spec_insn_sb_rs2_addr.eq(insn_sb.spec_rs2_addr) - m.d.comb += spec_insn_sb_rd_addr.eq(insn_sb.spec_rd_addr) - m.d.comb += spec_insn_sb_rd_wdata.eq(insn_sb.spec_rd_wdata) - m.d.comb += spec_insn_sb_pc_wdata.eq(insn_sb.spec_pc_wdata) - m.d.comb += spec_insn_sb_mem_addr.eq(insn_sb.spec_mem_addr) - m.d.comb += spec_insn_sb_mem_rmask.eq(insn_sb.spec_mem_rmask) - m.d.comb += spec_insn_sb_mem_wmask.eq(insn_sb.spec_mem_wmask) - m.d.comb += spec_insn_sb_mem_wdata.eq(insn_sb.spec_mem_wdata) - - spec_insn_sh_valid = Signal(1) - spec_insn_sh_trap = Signal(1) - spec_insn_sh_rs1_addr = Signal(5) - spec_insn_sh_rs2_addr = Signal(5) - spec_insn_sh_rd_addr = Signal(5) - spec_insn_sh_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sh_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sh_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sh_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sh_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sh_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_sh = insn_sh = rvfi_insn_sh() - m.d.comb += insn_sh.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_sh.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_sh.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_sh.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_sh.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_sh.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_sh_valid.eq(insn_sh.spec_valid) - m.d.comb += spec_insn_sh_trap.eq(insn_sh.spec_trap) - m.d.comb += spec_insn_sh_rs1_addr.eq(insn_sh.spec_rs1_addr) - m.d.comb += spec_insn_sh_rs2_addr.eq(insn_sh.spec_rs2_addr) - m.d.comb += spec_insn_sh_rd_addr.eq(insn_sh.spec_rd_addr) - m.d.comb += spec_insn_sh_rd_wdata.eq(insn_sh.spec_rd_wdata) - m.d.comb += spec_insn_sh_pc_wdata.eq(insn_sh.spec_pc_wdata) - m.d.comb += spec_insn_sh_mem_addr.eq(insn_sh.spec_mem_addr) - m.d.comb += spec_insn_sh_mem_rmask.eq(insn_sh.spec_mem_rmask) - m.d.comb += spec_insn_sh_mem_wmask.eq(insn_sh.spec_mem_wmask) - m.d.comb += spec_insn_sh_mem_wdata.eq(insn_sh.spec_mem_wdata) - - spec_insn_sw_valid = Signal(1) - spec_insn_sw_trap = Signal(1) - spec_insn_sw_rs1_addr = Signal(5) - spec_insn_sw_rs2_addr = Signal(5) - spec_insn_sw_rd_addr = Signal(5) - spec_insn_sw_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sw_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sw_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sw_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sw_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sw_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_sw = insn_sw = rvfi_insn_sw() - m.d.comb += insn_sw.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_sw.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_sw.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_sw.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_sw.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_sw.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_sw_valid.eq(insn_sw.spec_valid) - m.d.comb += spec_insn_sw_trap.eq(insn_sw.spec_trap) - m.d.comb += spec_insn_sw_rs1_addr.eq(insn_sw.spec_rs1_addr) - m.d.comb += spec_insn_sw_rs2_addr.eq(insn_sw.spec_rs2_addr) - m.d.comb += spec_insn_sw_rd_addr.eq(insn_sw.spec_rd_addr) - m.d.comb += spec_insn_sw_rd_wdata.eq(insn_sw.spec_rd_wdata) - m.d.comb += spec_insn_sw_pc_wdata.eq(insn_sw.spec_pc_wdata) - m.d.comb += spec_insn_sw_mem_addr.eq(insn_sw.spec_mem_addr) - m.d.comb += spec_insn_sw_mem_rmask.eq(insn_sw.spec_mem_rmask) - m.d.comb += spec_insn_sw_mem_wmask.eq(insn_sw.spec_mem_wmask) - m.d.comb += spec_insn_sw_mem_wdata.eq(insn_sw.spec_mem_wdata) - - spec_insn_addi_valid = Signal(1) - spec_insn_addi_trap = Signal(1) - spec_insn_addi_rs1_addr = Signal(5) - spec_insn_addi_rs2_addr = Signal(5) - spec_insn_addi_rd_addr = Signal(5) - spec_insn_addi_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_addi_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_addi_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_addi_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_addi_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_addi_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_addi = insn_addi = rvfi_insn_addi() - m.d.comb += insn_addi.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_addi.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_addi.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_addi.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_addi.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_addi.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_addi_valid.eq(insn_addi.spec_valid) - m.d.comb += spec_insn_addi_trap.eq(insn_addi.spec_trap) - m.d.comb += spec_insn_addi_rs1_addr.eq(insn_addi.spec_rs1_addr) - m.d.comb += spec_insn_addi_rs2_addr.eq(insn_addi.spec_rs2_addr) - m.d.comb += spec_insn_addi_rd_addr.eq(insn_addi.spec_rd_addr) - m.d.comb += spec_insn_addi_rd_wdata.eq(insn_addi.spec_rd_wdata) - m.d.comb += spec_insn_addi_pc_wdata.eq(insn_addi.spec_pc_wdata) - m.d.comb += spec_insn_addi_mem_addr.eq(insn_addi.spec_mem_addr) - m.d.comb += spec_insn_addi_mem_rmask.eq(insn_addi.spec_mem_rmask) - m.d.comb += spec_insn_addi_mem_wmask.eq(insn_addi.spec_mem_wmask) - m.d.comb += spec_insn_addi_mem_wdata.eq(insn_addi.spec_mem_wdata) - - spec_insn_slti_valid = Signal(1) - spec_insn_slti_trap = Signal(1) - spec_insn_slti_rs1_addr = Signal(5) - spec_insn_slti_rs2_addr = Signal(5) - spec_insn_slti_rd_addr = Signal(5) - spec_insn_slti_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_slti_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_slti_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_slti_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_slti_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_slti_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_slti = insn_slti = rvfi_insn_slti() - m.d.comb += insn_slti.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_slti.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_slti.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_slti.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_slti.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_slti.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_slti_valid.eq(insn_slti.spec_valid) - m.d.comb += spec_insn_slti_trap.eq(insn_slti.spec_trap) - m.d.comb += spec_insn_slti_rs1_addr.eq(insn_slti.spec_rs1_addr) - m.d.comb += spec_insn_slti_rs2_addr.eq(insn_slti.spec_rs2_addr) - m.d.comb += spec_insn_slti_rd_addr.eq(insn_slti.spec_rd_addr) - m.d.comb += spec_insn_slti_rd_wdata.eq(insn_slti.spec_rd_wdata) - m.d.comb += spec_insn_slti_pc_wdata.eq(insn_slti.spec_pc_wdata) - m.d.comb += spec_insn_slti_mem_addr.eq(insn_slti.spec_mem_addr) - m.d.comb += spec_insn_slti_mem_rmask.eq(insn_slti.spec_mem_rmask) - m.d.comb += spec_insn_slti_mem_wmask.eq(insn_slti.spec_mem_wmask) - m.d.comb += spec_insn_slti_mem_wdata.eq(insn_slti.spec_mem_wdata) - - spec_insn_sltiu_valid = Signal(1) - spec_insn_sltiu_trap = Signal(1) - spec_insn_sltiu_rs1_addr = Signal(5) - spec_insn_sltiu_rs2_addr = Signal(5) - spec_insn_sltiu_rd_addr = Signal(5) - spec_insn_sltiu_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sltiu_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sltiu_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sltiu_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sltiu_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sltiu_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_sltiu = insn_sltiu = rvfi_insn_sltiu() - m.d.comb += insn_sltiu.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_sltiu.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_sltiu.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_sltiu.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_sltiu.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_sltiu.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_sltiu_valid.eq(insn_sltiu.spec_valid) - m.d.comb += spec_insn_sltiu_trap.eq(insn_sltiu.spec_trap) - m.d.comb += spec_insn_sltiu_rs1_addr.eq(insn_sltiu.spec_rs1_addr) - m.d.comb += spec_insn_sltiu_rs2_addr.eq(insn_sltiu.spec_rs2_addr) - m.d.comb += spec_insn_sltiu_rd_addr.eq(insn_sltiu.spec_rd_addr) - m.d.comb += spec_insn_sltiu_rd_wdata.eq(insn_sltiu.spec_rd_wdata) - m.d.comb += spec_insn_sltiu_pc_wdata.eq(insn_sltiu.spec_pc_wdata) - m.d.comb += spec_insn_sltiu_mem_addr.eq(insn_sltiu.spec_mem_addr) - m.d.comb += spec_insn_sltiu_mem_rmask.eq(insn_sltiu.spec_mem_rmask) - m.d.comb += spec_insn_sltiu_mem_wmask.eq(insn_sltiu.spec_mem_wmask) - m.d.comb += spec_insn_sltiu_mem_wdata.eq(insn_sltiu.spec_mem_wdata) - - spec_insn_xori_valid = Signal(1) - spec_insn_xori_trap = Signal(1) - spec_insn_xori_rs1_addr = Signal(5) - spec_insn_xori_rs2_addr = Signal(5) - spec_insn_xori_rd_addr = Signal(5) - spec_insn_xori_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_xori_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_xori_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_xori_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_xori_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_xori_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_xori = insn_xori = rvfi_insn_xori() - m.d.comb += insn_xori.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_xori.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_xori.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_xori.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_xori.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_xori.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_xori_valid.eq(insn_xori.spec_valid) - m.d.comb += spec_insn_xori_trap.eq(insn_xori.spec_trap) - m.d.comb += spec_insn_xori_rs1_addr.eq(insn_xori.spec_rs1_addr) - m.d.comb += spec_insn_xori_rs2_addr.eq(insn_xori.spec_rs2_addr) - m.d.comb += spec_insn_xori_rd_addr.eq(insn_xori.spec_rd_addr) - m.d.comb += spec_insn_xori_rd_wdata.eq(insn_xori.spec_rd_wdata) - m.d.comb += spec_insn_xori_pc_wdata.eq(insn_xori.spec_pc_wdata) - m.d.comb += spec_insn_xori_mem_addr.eq(insn_xori.spec_mem_addr) - m.d.comb += spec_insn_xori_mem_rmask.eq(insn_xori.spec_mem_rmask) - m.d.comb += spec_insn_xori_mem_wmask.eq(insn_xori.spec_mem_wmask) - m.d.comb += spec_insn_xori_mem_wdata.eq(insn_xori.spec_mem_wdata) - - spec_insn_ori_valid = Signal(1) - spec_insn_ori_trap = Signal(1) - spec_insn_ori_rs1_addr = Signal(5) - spec_insn_ori_rs2_addr = Signal(5) - spec_insn_ori_rd_addr = Signal(5) - spec_insn_ori_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_ori_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_ori_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_ori_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_ori_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_ori_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_ori = insn_ori = rvfi_insn_ori() - m.d.comb += insn_ori.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_ori.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_ori.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_ori.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_ori.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_ori.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_ori_valid.eq(insn_ori.spec_valid) - m.d.comb += spec_insn_ori_trap.eq(insn_ori.spec_trap) - m.d.comb += spec_insn_ori_rs1_addr.eq(insn_ori.spec_rs1_addr) - m.d.comb += spec_insn_ori_rs2_addr.eq(insn_ori.spec_rs2_addr) - m.d.comb += spec_insn_ori_rd_addr.eq(insn_ori.spec_rd_addr) - m.d.comb += spec_insn_ori_rd_wdata.eq(insn_ori.spec_rd_wdata) - m.d.comb += spec_insn_ori_pc_wdata.eq(insn_ori.spec_pc_wdata) - m.d.comb += spec_insn_ori_mem_addr.eq(insn_ori.spec_mem_addr) - m.d.comb += spec_insn_ori_mem_rmask.eq(insn_ori.spec_mem_rmask) - m.d.comb += spec_insn_ori_mem_wmask.eq(insn_ori.spec_mem_wmask) - m.d.comb += spec_insn_ori_mem_wdata.eq(insn_ori.spec_mem_wdata) - - spec_insn_andi_valid = Signal(1) - spec_insn_andi_trap = Signal(1) - spec_insn_andi_rs1_addr = Signal(5) - spec_insn_andi_rs2_addr = Signal(5) - spec_insn_andi_rd_addr = Signal(5) - spec_insn_andi_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_andi_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_andi_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_andi_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_andi_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_andi_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_andi = insn_andi = rvfi_insn_andi() - m.d.comb += insn_andi.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_andi.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_andi.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_andi.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_andi.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_andi.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_andi_valid.eq(insn_andi.spec_valid) - m.d.comb += spec_insn_andi_trap.eq(insn_andi.spec_trap) - m.d.comb += spec_insn_andi_rs1_addr.eq(insn_andi.spec_rs1_addr) - m.d.comb += spec_insn_andi_rs2_addr.eq(insn_andi.spec_rs2_addr) - m.d.comb += spec_insn_andi_rd_addr.eq(insn_andi.spec_rd_addr) - m.d.comb += spec_insn_andi_rd_wdata.eq(insn_andi.spec_rd_wdata) - m.d.comb += spec_insn_andi_pc_wdata.eq(insn_andi.spec_pc_wdata) - m.d.comb += spec_insn_andi_mem_addr.eq(insn_andi.spec_mem_addr) - m.d.comb += spec_insn_andi_mem_rmask.eq(insn_andi.spec_mem_rmask) - m.d.comb += spec_insn_andi_mem_wmask.eq(insn_andi.spec_mem_wmask) - m.d.comb += spec_insn_andi_mem_wdata.eq(insn_andi.spec_mem_wdata) - - spec_insn_slli_valid = Signal(1) - spec_insn_slli_trap = Signal(1) - spec_insn_slli_rs1_addr = Signal(5) - spec_insn_slli_rs2_addr = Signal(5) - spec_insn_slli_rd_addr = Signal(5) - spec_insn_slli_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_slli_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_slli_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_slli_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_slli_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_slli_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_slli = insn_slli = rvfi_insn_slli() - m.d.comb += insn_slli.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_slli.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_slli.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_slli.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_slli.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_slli.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_slli_valid.eq(insn_slli.spec_valid) - m.d.comb += spec_insn_slli_trap.eq(insn_slli.spec_trap) - m.d.comb += spec_insn_slli_rs1_addr.eq(insn_slli.spec_rs1_addr) - m.d.comb += spec_insn_slli_rs2_addr.eq(insn_slli.spec_rs2_addr) - m.d.comb += spec_insn_slli_rd_addr.eq(insn_slli.spec_rd_addr) - m.d.comb += spec_insn_slli_rd_wdata.eq(insn_slli.spec_rd_wdata) - m.d.comb += spec_insn_slli_pc_wdata.eq(insn_slli.spec_pc_wdata) - m.d.comb += spec_insn_slli_mem_addr.eq(insn_slli.spec_mem_addr) - m.d.comb += spec_insn_slli_mem_rmask.eq(insn_slli.spec_mem_rmask) - m.d.comb += spec_insn_slli_mem_wmask.eq(insn_slli.spec_mem_wmask) - m.d.comb += spec_insn_slli_mem_wdata.eq(insn_slli.spec_mem_wdata) - - spec_insn_srli_valid = Signal(1) - spec_insn_srli_trap = Signal(1) - spec_insn_srli_rs1_addr = Signal(5) - spec_insn_srli_rs2_addr = Signal(5) - spec_insn_srli_rd_addr = Signal(5) - spec_insn_srli_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_srli_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_srli_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_srli_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_srli_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_srli_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_srli = insn_srli = rvfi_insn_srli() - m.d.comb += insn_srli.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_srli.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_srli.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_srli.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_srli.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_srli.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_srli_valid.eq(insn_srli.spec_valid) - m.d.comb += spec_insn_srli_trap.eq(insn_srli.spec_trap) - m.d.comb += spec_insn_srli_rs1_addr.eq(insn_srli.spec_rs1_addr) - m.d.comb += spec_insn_srli_rs2_addr.eq(insn_srli.spec_rs2_addr) - m.d.comb += spec_insn_srli_rd_addr.eq(insn_srli.spec_rd_addr) - m.d.comb += spec_insn_srli_rd_wdata.eq(insn_srli.spec_rd_wdata) - m.d.comb += spec_insn_srli_pc_wdata.eq(insn_srli.spec_pc_wdata) - m.d.comb += spec_insn_srli_mem_addr.eq(insn_srli.spec_mem_addr) - m.d.comb += spec_insn_srli_mem_rmask.eq(insn_srli.spec_mem_rmask) - m.d.comb += spec_insn_srli_mem_wmask.eq(insn_srli.spec_mem_wmask) - m.d.comb += spec_insn_srli_mem_wdata.eq(insn_srli.spec_mem_wdata) - - spec_insn_srai_valid = Signal(1) - spec_insn_srai_trap = Signal(1) - spec_insn_srai_rs1_addr = Signal(5) - spec_insn_srai_rs2_addr = Signal(5) - spec_insn_srai_rd_addr = Signal(5) - spec_insn_srai_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_srai_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_srai_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_srai_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_srai_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_srai_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_srai = insn_srai = rvfi_insn_srai() - m.d.comb += insn_srai.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_srai.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_srai.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_srai.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_srai.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_srai.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_srai_valid.eq(insn_srai.spec_valid) - m.d.comb += spec_insn_srai_trap.eq(insn_srai.spec_trap) - m.d.comb += spec_insn_srai_rs1_addr.eq(insn_srai.spec_rs1_addr) - m.d.comb += spec_insn_srai_rs2_addr.eq(insn_srai.spec_rs2_addr) - m.d.comb += spec_insn_srai_rd_addr.eq(insn_srai.spec_rd_addr) - m.d.comb += spec_insn_srai_rd_wdata.eq(insn_srai.spec_rd_wdata) - m.d.comb += spec_insn_srai_pc_wdata.eq(insn_srai.spec_pc_wdata) - m.d.comb += spec_insn_srai_mem_addr.eq(insn_srai.spec_mem_addr) - m.d.comb += spec_insn_srai_mem_rmask.eq(insn_srai.spec_mem_rmask) - m.d.comb += spec_insn_srai_mem_wmask.eq(insn_srai.spec_mem_wmask) - m.d.comb += spec_insn_srai_mem_wdata.eq(insn_srai.spec_mem_wdata) - - spec_insn_add_valid = Signal(1) - spec_insn_add_trap = Signal(1) - spec_insn_add_rs1_addr = Signal(5) - spec_insn_add_rs2_addr = Signal(5) - spec_insn_add_rd_addr = Signal(5) - spec_insn_add_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_add_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_add_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_add_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_add_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_add_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_add = insn_add = rvfi_insn_add() - m.d.comb += insn_add.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_add.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_add.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_add.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_add.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_add.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_add_valid.eq(insn_add.spec_valid) - m.d.comb += spec_insn_add_trap.eq(insn_add.spec_trap) - m.d.comb += spec_insn_add_rs1_addr.eq(insn_add.spec_rs1_addr) - m.d.comb += spec_insn_add_rs2_addr.eq(insn_add.spec_rs2_addr) - m.d.comb += spec_insn_add_rd_addr.eq(insn_add.spec_rd_addr) - m.d.comb += spec_insn_add_rd_wdata.eq(insn_add.spec_rd_wdata) - m.d.comb += spec_insn_add_pc_wdata.eq(insn_add.spec_pc_wdata) - m.d.comb += spec_insn_add_mem_addr.eq(insn_add.spec_mem_addr) - m.d.comb += spec_insn_add_mem_rmask.eq(insn_add.spec_mem_rmask) - m.d.comb += spec_insn_add_mem_wmask.eq(insn_add.spec_mem_wmask) - m.d.comb += spec_insn_add_mem_wdata.eq(insn_add.spec_mem_wdata) - - spec_insn_sub_valid = Signal(1) - spec_insn_sub_trap = Signal(1) - spec_insn_sub_rs1_addr = Signal(5) - spec_insn_sub_rs2_addr = Signal(5) - spec_insn_sub_rd_addr = Signal(5) - spec_insn_sub_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sub_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sub_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sub_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sub_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sub_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_sub = insn_sub = rvfi_insn_sub() - m.d.comb += insn_sub.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_sub.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_sub.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_sub.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_sub.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_sub.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_sub_valid.eq(insn_sub.spec_valid) - m.d.comb += spec_insn_sub_trap.eq(insn_sub.spec_trap) - m.d.comb += spec_insn_sub_rs1_addr.eq(insn_sub.spec_rs1_addr) - m.d.comb += spec_insn_sub_rs2_addr.eq(insn_sub.spec_rs2_addr) - m.d.comb += spec_insn_sub_rd_addr.eq(insn_sub.spec_rd_addr) - m.d.comb += spec_insn_sub_rd_wdata.eq(insn_sub.spec_rd_wdata) - m.d.comb += spec_insn_sub_pc_wdata.eq(insn_sub.spec_pc_wdata) - m.d.comb += spec_insn_sub_mem_addr.eq(insn_sub.spec_mem_addr) - m.d.comb += spec_insn_sub_mem_rmask.eq(insn_sub.spec_mem_rmask) - m.d.comb += spec_insn_sub_mem_wmask.eq(insn_sub.spec_mem_wmask) - m.d.comb += spec_insn_sub_mem_wdata.eq(insn_sub.spec_mem_wdata) - - spec_insn_sll_valid = Signal(1) - spec_insn_sll_trap = Signal(1) - spec_insn_sll_rs1_addr = Signal(5) - spec_insn_sll_rs2_addr = Signal(5) - spec_insn_sll_rd_addr = Signal(5) - spec_insn_sll_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sll_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sll_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sll_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sll_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sll_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_sll = insn_sll = rvfi_insn_sll() - m.d.comb += insn_sll.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_sll.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_sll.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_sll.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_sll.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_sll.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_sll_valid.eq(insn_sll.spec_valid) - m.d.comb += spec_insn_sll_trap.eq(insn_sll.spec_trap) - m.d.comb += spec_insn_sll_rs1_addr.eq(insn_sll.spec_rs1_addr) - m.d.comb += spec_insn_sll_rs2_addr.eq(insn_sll.spec_rs2_addr) - m.d.comb += spec_insn_sll_rd_addr.eq(insn_sll.spec_rd_addr) - m.d.comb += spec_insn_sll_rd_wdata.eq(insn_sll.spec_rd_wdata) - m.d.comb += spec_insn_sll_pc_wdata.eq(insn_sll.spec_pc_wdata) - m.d.comb += spec_insn_sll_mem_addr.eq(insn_sll.spec_mem_addr) - m.d.comb += spec_insn_sll_mem_rmask.eq(insn_sll.spec_mem_rmask) - m.d.comb += spec_insn_sll_mem_wmask.eq(insn_sll.spec_mem_wmask) - m.d.comb += spec_insn_sll_mem_wdata.eq(insn_sll.spec_mem_wdata) - - spec_insn_slt_valid = Signal(1) - spec_insn_slt_trap = Signal(1) - spec_insn_slt_rs1_addr = Signal(5) - spec_insn_slt_rs2_addr = Signal(5) - spec_insn_slt_rd_addr = Signal(5) - spec_insn_slt_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_slt_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_slt_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_slt_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_slt_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_slt_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_slt = insn_slt = rvfi_insn_slt() - m.d.comb += insn_slt.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_slt.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_slt.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_slt.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_slt.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_slt.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_slt_valid.eq(insn_slt.spec_valid) - m.d.comb += spec_insn_slt_trap.eq(insn_slt.spec_trap) - m.d.comb += spec_insn_slt_rs1_addr.eq(insn_slt.spec_rs1_addr) - m.d.comb += spec_insn_slt_rs2_addr.eq(insn_slt.spec_rs2_addr) - m.d.comb += spec_insn_slt_rd_addr.eq(insn_slt.spec_rd_addr) - m.d.comb += spec_insn_slt_rd_wdata.eq(insn_slt.spec_rd_wdata) - m.d.comb += spec_insn_slt_pc_wdata.eq(insn_slt.spec_pc_wdata) - m.d.comb += spec_insn_slt_mem_addr.eq(insn_slt.spec_mem_addr) - m.d.comb += spec_insn_slt_mem_rmask.eq(insn_slt.spec_mem_rmask) - m.d.comb += spec_insn_slt_mem_wmask.eq(insn_slt.spec_mem_wmask) - m.d.comb += spec_insn_slt_mem_wdata.eq(insn_slt.spec_mem_wdata) - - spec_insn_sltu_valid = Signal(1) - spec_insn_sltu_trap = Signal(1) - spec_insn_sltu_rs1_addr = Signal(5) - spec_insn_sltu_rs2_addr = Signal(5) - spec_insn_sltu_rd_addr = Signal(5) - spec_insn_sltu_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sltu_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sltu_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sltu_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sltu_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sltu_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_sltu = insn_sltu = rvfi_insn_sltu() - m.d.comb += insn_sltu.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_sltu.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_sltu.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_sltu.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_sltu.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_sltu.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_sltu_valid.eq(insn_sltu.spec_valid) - m.d.comb += spec_insn_sltu_trap.eq(insn_sltu.spec_trap) - m.d.comb += spec_insn_sltu_rs1_addr.eq(insn_sltu.spec_rs1_addr) - m.d.comb += spec_insn_sltu_rs2_addr.eq(insn_sltu.spec_rs2_addr) - m.d.comb += spec_insn_sltu_rd_addr.eq(insn_sltu.spec_rd_addr) - m.d.comb += spec_insn_sltu_rd_wdata.eq(insn_sltu.spec_rd_wdata) - m.d.comb += spec_insn_sltu_pc_wdata.eq(insn_sltu.spec_pc_wdata) - m.d.comb += spec_insn_sltu_mem_addr.eq(insn_sltu.spec_mem_addr) - m.d.comb += spec_insn_sltu_mem_rmask.eq(insn_sltu.spec_mem_rmask) - m.d.comb += spec_insn_sltu_mem_wmask.eq(insn_sltu.spec_mem_wmask) - m.d.comb += spec_insn_sltu_mem_wdata.eq(insn_sltu.spec_mem_wdata) - - spec_insn_xor_valid = Signal(1) - spec_insn_xor_trap = Signal(1) - spec_insn_xor_rs1_addr = Signal(5) - spec_insn_xor_rs2_addr = Signal(5) - spec_insn_xor_rd_addr = Signal(5) - spec_insn_xor_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_xor_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_xor_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_xor_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_xor_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_xor_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_xor = insn_xor = rvfi_insn_xor() - m.d.comb += insn_xor.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_xor.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_xor.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_xor.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_xor.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_xor.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_xor_valid.eq(insn_xor.spec_valid) - m.d.comb += spec_insn_xor_trap.eq(insn_xor.spec_trap) - m.d.comb += spec_insn_xor_rs1_addr.eq(insn_xor.spec_rs1_addr) - m.d.comb += spec_insn_xor_rs2_addr.eq(insn_xor.spec_rs2_addr) - m.d.comb += spec_insn_xor_rd_addr.eq(insn_xor.spec_rd_addr) - m.d.comb += spec_insn_xor_rd_wdata.eq(insn_xor.spec_rd_wdata) - m.d.comb += spec_insn_xor_pc_wdata.eq(insn_xor.spec_pc_wdata) - m.d.comb += spec_insn_xor_mem_addr.eq(insn_xor.spec_mem_addr) - m.d.comb += spec_insn_xor_mem_rmask.eq(insn_xor.spec_mem_rmask) - m.d.comb += spec_insn_xor_mem_wmask.eq(insn_xor.spec_mem_wmask) - m.d.comb += spec_insn_xor_mem_wdata.eq(insn_xor.spec_mem_wdata) - - spec_insn_srl_valid = Signal(1) - spec_insn_srl_trap = Signal(1) - spec_insn_srl_rs1_addr = Signal(5) - spec_insn_srl_rs2_addr = Signal(5) - spec_insn_srl_rd_addr = Signal(5) - spec_insn_srl_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_srl_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_srl_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_srl_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_srl_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_srl_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_srl = insn_srl = rvfi_insn_srl() - m.d.comb += insn_srl.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_srl.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_srl.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_srl.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_srl.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_srl.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_srl_valid.eq(insn_srl.spec_valid) - m.d.comb += spec_insn_srl_trap.eq(insn_srl.spec_trap) - m.d.comb += spec_insn_srl_rs1_addr.eq(insn_srl.spec_rs1_addr) - m.d.comb += spec_insn_srl_rs2_addr.eq(insn_srl.spec_rs2_addr) - m.d.comb += spec_insn_srl_rd_addr.eq(insn_srl.spec_rd_addr) - m.d.comb += spec_insn_srl_rd_wdata.eq(insn_srl.spec_rd_wdata) - m.d.comb += spec_insn_srl_pc_wdata.eq(insn_srl.spec_pc_wdata) - m.d.comb += spec_insn_srl_mem_addr.eq(insn_srl.spec_mem_addr) - m.d.comb += spec_insn_srl_mem_rmask.eq(insn_srl.spec_mem_rmask) - m.d.comb += spec_insn_srl_mem_wmask.eq(insn_srl.spec_mem_wmask) - m.d.comb += spec_insn_srl_mem_wdata.eq(insn_srl.spec_mem_wdata) - - spec_insn_sra_valid = Signal(1) - spec_insn_sra_trap = Signal(1) - spec_insn_sra_rs1_addr = Signal(5) - spec_insn_sra_rs2_addr = Signal(5) - spec_insn_sra_rd_addr = Signal(5) - spec_insn_sra_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sra_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sra_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_sra_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sra_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_sra_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_sra = insn_sra = rvfi_insn_sra() - m.d.comb += insn_sra.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_sra.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_sra.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_sra.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_sra.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_sra.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_sra_valid.eq(insn_sra.spec_valid) - m.d.comb += spec_insn_sra_trap.eq(insn_sra.spec_trap) - m.d.comb += spec_insn_sra_rs1_addr.eq(insn_sra.spec_rs1_addr) - m.d.comb += spec_insn_sra_rs2_addr.eq(insn_sra.spec_rs2_addr) - m.d.comb += spec_insn_sra_rd_addr.eq(insn_sra.spec_rd_addr) - m.d.comb += spec_insn_sra_rd_wdata.eq(insn_sra.spec_rd_wdata) - m.d.comb += spec_insn_sra_pc_wdata.eq(insn_sra.spec_pc_wdata) - m.d.comb += spec_insn_sra_mem_addr.eq(insn_sra.spec_mem_addr) - m.d.comb += spec_insn_sra_mem_rmask.eq(insn_sra.spec_mem_rmask) - m.d.comb += spec_insn_sra_mem_wmask.eq(insn_sra.spec_mem_wmask) - m.d.comb += spec_insn_sra_mem_wdata.eq(insn_sra.spec_mem_wdata) - - spec_insn_or_valid = Signal(1) - spec_insn_or_trap = Signal(1) - spec_insn_or_rs1_addr = Signal(5) - spec_insn_or_rs2_addr = Signal(5) - spec_insn_or_rd_addr = Signal(5) - spec_insn_or_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_or_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_or_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_or_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_or_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_or_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_or = insn_or = rvfi_insn_or() - m.d.comb += insn_or.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_or.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_or.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_or.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_or.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_or.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_or_valid.eq(insn_or.spec_valid) - m.d.comb += spec_insn_or_trap.eq(insn_or.spec_trap) - m.d.comb += spec_insn_or_rs1_addr.eq(insn_or.spec_rs1_addr) - m.d.comb += spec_insn_or_rs2_addr.eq(insn_or.spec_rs2_addr) - m.d.comb += spec_insn_or_rd_addr.eq(insn_or.spec_rd_addr) - m.d.comb += spec_insn_or_rd_wdata.eq(insn_or.spec_rd_wdata) - m.d.comb += spec_insn_or_pc_wdata.eq(insn_or.spec_pc_wdata) - m.d.comb += spec_insn_or_mem_addr.eq(insn_or.spec_mem_addr) - m.d.comb += spec_insn_or_mem_rmask.eq(insn_or.spec_mem_rmask) - m.d.comb += spec_insn_or_mem_wmask.eq(insn_or.spec_mem_wmask) - m.d.comb += spec_insn_or_mem_wdata.eq(insn_or.spec_mem_wdata) - - spec_insn_and_valid = Signal(1) - spec_insn_and_trap = Signal(1) - spec_insn_and_rs1_addr = Signal(5) - spec_insn_and_rs2_addr = Signal(5) - spec_insn_and_rd_addr = Signal(5) - spec_insn_and_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_and_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_and_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_and_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_and_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_and_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_and = insn_and = rvfi_insn_and() - m.d.comb += insn_and.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_and.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_and.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_and.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_and.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_and.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_and_valid.eq(insn_and.spec_valid) - m.d.comb += spec_insn_and_trap.eq(insn_and.spec_trap) - m.d.comb += spec_insn_and_rs1_addr.eq(insn_and.spec_rs1_addr) - m.d.comb += spec_insn_and_rs2_addr.eq(insn_and.spec_rs2_addr) - m.d.comb += spec_insn_and_rd_addr.eq(insn_and.spec_rd_addr) - m.d.comb += spec_insn_and_rd_wdata.eq(insn_and.spec_rd_wdata) - m.d.comb += spec_insn_and_pc_wdata.eq(insn_and.spec_pc_wdata) - m.d.comb += spec_insn_and_mem_addr.eq(insn_and.spec_mem_addr) - m.d.comb += spec_insn_and_mem_rmask.eq(insn_and.spec_mem_rmask) - m.d.comb += spec_insn_and_mem_wmask.eq(insn_and.spec_mem_wmask) - m.d.comb += spec_insn_and_mem_wdata.eq(insn_and.spec_mem_wdata) - - spec_insn_mul_valid = Signal(1) - spec_insn_mul_trap = Signal(1) - spec_insn_mul_rs1_addr = Signal(5) - spec_insn_mul_rs2_addr = Signal(5) - spec_insn_mul_rd_addr = Signal(5) - spec_insn_mul_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_mul_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_mul_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_mul_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_mul_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_mul_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_mul = insn_mul = rvfi_insn_mul() - m.d.comb += insn_mul.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_mul.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_mul.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_mul.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_mul.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_mul.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_mul_valid.eq(insn_mul.spec_valid) - m.d.comb += spec_insn_mul_trap.eq(insn_mul.spec_trap) - m.d.comb += spec_insn_mul_rs1_addr.eq(insn_mul.spec_rs1_addr) - m.d.comb += spec_insn_mul_rs2_addr.eq(insn_mul.spec_rs2_addr) - m.d.comb += spec_insn_mul_rd_addr.eq(insn_mul.spec_rd_addr) - m.d.comb += spec_insn_mul_rd_wdata.eq(insn_mul.spec_rd_wdata) - m.d.comb += spec_insn_mul_pc_wdata.eq(insn_mul.spec_pc_wdata) - m.d.comb += spec_insn_mul_mem_addr.eq(insn_mul.spec_mem_addr) - m.d.comb += spec_insn_mul_mem_rmask.eq(insn_mul.spec_mem_rmask) - m.d.comb += spec_insn_mul_mem_wmask.eq(insn_mul.spec_mem_wmask) - m.d.comb += spec_insn_mul_mem_wdata.eq(insn_mul.spec_mem_wdata) - - spec_insn_mulh_valid = Signal(1) - spec_insn_mulh_trap = Signal(1) - spec_insn_mulh_rs1_addr = Signal(5) - spec_insn_mulh_rs2_addr = Signal(5) - spec_insn_mulh_rd_addr = Signal(5) - spec_insn_mulh_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_mulh_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_mulh_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_mulh_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_mulh_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_mulh_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_mulh = insn_mulh = rvfi_insn_mulh() - m.d.comb += insn_mulh.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_mulh.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_mulh.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_mulh.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_mulh.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_mulh.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_mulh_valid.eq(insn_mulh.spec_valid) - m.d.comb += spec_insn_mulh_trap.eq(insn_mulh.spec_trap) - m.d.comb += spec_insn_mulh_rs1_addr.eq(insn_mulh.spec_rs1_addr) - m.d.comb += spec_insn_mulh_rs2_addr.eq(insn_mulh.spec_rs2_addr) - m.d.comb += spec_insn_mulh_rd_addr.eq(insn_mulh.spec_rd_addr) - m.d.comb += spec_insn_mulh_rd_wdata.eq(insn_mulh.spec_rd_wdata) - m.d.comb += spec_insn_mulh_pc_wdata.eq(insn_mulh.spec_pc_wdata) - m.d.comb += spec_insn_mulh_mem_addr.eq(insn_mulh.spec_mem_addr) - m.d.comb += spec_insn_mulh_mem_rmask.eq(insn_mulh.spec_mem_rmask) - m.d.comb += spec_insn_mulh_mem_wmask.eq(insn_mulh.spec_mem_wmask) - m.d.comb += spec_insn_mulh_mem_wdata.eq(insn_mulh.spec_mem_wdata) - - spec_insn_mulhsu_valid = Signal(1) - spec_insn_mulhsu_trap = Signal(1) - spec_insn_mulhsu_rs1_addr = Signal(5) - spec_insn_mulhsu_rs2_addr = Signal(5) - spec_insn_mulhsu_rd_addr = Signal(5) - spec_insn_mulhsu_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_mulhsu_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_mulhsu_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_mulhsu_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_mulhsu_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_mulhsu_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_mulhsu = insn_mulhsu = rvfi_insn_mulhsu() - m.d.comb += insn_mulhsu.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_mulhsu.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_mulhsu.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_mulhsu.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_mulhsu.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_mulhsu.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_mulhsu_valid.eq(insn_mulhsu.spec_valid) - m.d.comb += spec_insn_mulhsu_trap.eq(insn_mulhsu.spec_trap) - m.d.comb += spec_insn_mulhsu_rs1_addr.eq(insn_mulhsu.spec_rs1_addr) - m.d.comb += spec_insn_mulhsu_rs2_addr.eq(insn_mulhsu.spec_rs2_addr) - m.d.comb += spec_insn_mulhsu_rd_addr.eq(insn_mulhsu.spec_rd_addr) - m.d.comb += spec_insn_mulhsu_rd_wdata.eq(insn_mulhsu.spec_rd_wdata) - m.d.comb += spec_insn_mulhsu_pc_wdata.eq(insn_mulhsu.spec_pc_wdata) - m.d.comb += spec_insn_mulhsu_mem_addr.eq(insn_mulhsu.spec_mem_addr) - m.d.comb += spec_insn_mulhsu_mem_rmask.eq(insn_mulhsu.spec_mem_rmask) - m.d.comb += spec_insn_mulhsu_mem_wmask.eq(insn_mulhsu.spec_mem_wmask) - m.d.comb += spec_insn_mulhsu_mem_wdata.eq(insn_mulhsu.spec_mem_wdata) - - spec_insn_mulhu_valid = Signal(1) - spec_insn_mulhu_trap = Signal(1) - spec_insn_mulhu_rs1_addr = Signal(5) - spec_insn_mulhu_rs2_addr = Signal(5) - spec_insn_mulhu_rd_addr = Signal(5) - spec_insn_mulhu_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_mulhu_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_mulhu_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_mulhu_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_mulhu_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_mulhu_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_mulhu = insn_mulhu = rvfi_insn_mulhu() - m.d.comb += insn_mulhu.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_mulhu.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_mulhu.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_mulhu.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_mulhu.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_mulhu.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_mulhu_valid.eq(insn_mulhu.spec_valid) - m.d.comb += spec_insn_mulhu_trap.eq(insn_mulhu.spec_trap) - m.d.comb += spec_insn_mulhu_rs1_addr.eq(insn_mulhu.spec_rs1_addr) - m.d.comb += spec_insn_mulhu_rs2_addr.eq(insn_mulhu.spec_rs2_addr) - m.d.comb += spec_insn_mulhu_rd_addr.eq(insn_mulhu.spec_rd_addr) - m.d.comb += spec_insn_mulhu_rd_wdata.eq(insn_mulhu.spec_rd_wdata) - m.d.comb += spec_insn_mulhu_pc_wdata.eq(insn_mulhu.spec_pc_wdata) - m.d.comb += spec_insn_mulhu_mem_addr.eq(insn_mulhu.spec_mem_addr) - m.d.comb += spec_insn_mulhu_mem_rmask.eq(insn_mulhu.spec_mem_rmask) - m.d.comb += spec_insn_mulhu_mem_wmask.eq(insn_mulhu.spec_mem_wmask) - m.d.comb += spec_insn_mulhu_mem_wdata.eq(insn_mulhu.spec_mem_wdata) - - spec_insn_div_valid = Signal(1) - spec_insn_div_trap = Signal(1) - spec_insn_div_rs1_addr = Signal(5) - spec_insn_div_rs2_addr = Signal(5) - spec_insn_div_rd_addr = Signal(5) - spec_insn_div_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_div_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_div_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_div_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_div_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_div_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_div = insn_div = rvfi_insn_div() - m.d.comb += insn_div.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_div.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_div.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_div.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_div.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_div.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_div_valid.eq(insn_div.spec_valid) - m.d.comb += spec_insn_div_trap.eq(insn_div.spec_trap) - m.d.comb += spec_insn_div_rs1_addr.eq(insn_div.spec_rs1_addr) - m.d.comb += spec_insn_div_rs2_addr.eq(insn_div.spec_rs2_addr) - m.d.comb += spec_insn_div_rd_addr.eq(insn_div.spec_rd_addr) - m.d.comb += spec_insn_div_rd_wdata.eq(insn_div.spec_rd_wdata) - m.d.comb += spec_insn_div_pc_wdata.eq(insn_div.spec_pc_wdata) - m.d.comb += spec_insn_div_mem_addr.eq(insn_div.spec_mem_addr) - m.d.comb += spec_insn_div_mem_rmask.eq(insn_div.spec_mem_rmask) - m.d.comb += spec_insn_div_mem_wmask.eq(insn_div.spec_mem_wmask) - m.d.comb += spec_insn_div_mem_wdata.eq(insn_div.spec_mem_wdata) - - spec_insn_divu_valid = Signal(1) - spec_insn_divu_trap = Signal(1) - spec_insn_divu_rs1_addr = Signal(5) - spec_insn_divu_rs2_addr = Signal(5) - spec_insn_divu_rd_addr = Signal(5) - spec_insn_divu_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_divu_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_divu_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_divu_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_divu_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_divu_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_divu = insn_divu = rvfi_insn_divu() - m.d.comb += insn_divu.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_divu.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_divu.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_divu.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_divu.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_divu.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_divu_valid.eq(insn_divu.spec_valid) - m.d.comb += spec_insn_divu_trap.eq(insn_divu.spec_trap) - m.d.comb += spec_insn_divu_rs1_addr.eq(insn_divu.spec_rs1_addr) - m.d.comb += spec_insn_divu_rs2_addr.eq(insn_divu.spec_rs2_addr) - m.d.comb += spec_insn_divu_rd_addr.eq(insn_divu.spec_rd_addr) - m.d.comb += spec_insn_divu_rd_wdata.eq(insn_divu.spec_rd_wdata) - m.d.comb += spec_insn_divu_pc_wdata.eq(insn_divu.spec_pc_wdata) - m.d.comb += spec_insn_divu_mem_addr.eq(insn_divu.spec_mem_addr) - m.d.comb += spec_insn_divu_mem_rmask.eq(insn_divu.spec_mem_rmask) - m.d.comb += spec_insn_divu_mem_wmask.eq(insn_divu.spec_mem_wmask) - m.d.comb += spec_insn_divu_mem_wdata.eq(insn_divu.spec_mem_wdata) - - spec_insn_rem_valid = Signal(1) - spec_insn_rem_trap = Signal(1) - spec_insn_rem_rs1_addr = Signal(5) - spec_insn_rem_rs2_addr = Signal(5) - spec_insn_rem_rd_addr = Signal(5) - spec_insn_rem_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_rem_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_rem_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_rem_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_rem_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_rem_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_rem = insn_rem = rvfi_insn_rem() - m.d.comb += insn_rem.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_rem.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_rem.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_rem.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_rem.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_rem.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_rem_valid.eq(insn_rem.spec_valid) - m.d.comb += spec_insn_rem_trap.eq(insn_rem.spec_trap) - m.d.comb += spec_insn_rem_rs1_addr.eq(insn_rem.spec_rs1_addr) - m.d.comb += spec_insn_rem_rs2_addr.eq(insn_rem.spec_rs2_addr) - m.d.comb += spec_insn_rem_rd_addr.eq(insn_rem.spec_rd_addr) - m.d.comb += spec_insn_rem_rd_wdata.eq(insn_rem.spec_rd_wdata) - m.d.comb += spec_insn_rem_pc_wdata.eq(insn_rem.spec_pc_wdata) - m.d.comb += spec_insn_rem_mem_addr.eq(insn_rem.spec_mem_addr) - m.d.comb += spec_insn_rem_mem_rmask.eq(insn_rem.spec_mem_rmask) - m.d.comb += spec_insn_rem_mem_wmask.eq(insn_rem.spec_mem_wmask) - m.d.comb += spec_insn_rem_mem_wdata.eq(insn_rem.spec_mem_wdata) - - spec_insn_remu_valid = Signal(1) - spec_insn_remu_trap = Signal(1) - spec_insn_remu_rs1_addr = Signal(5) - spec_insn_remu_rs2_addr = Signal(5) - spec_insn_remu_rd_addr = Signal(5) - spec_insn_remu_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_remu_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_remu_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - spec_insn_remu_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_remu_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - spec_insn_remu_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - m.submodules.insn_remu = insn_remu = rvfi_insn_remu() - m.d.comb += insn_remu.rvfi_valid.eq(self.rvfi_valid) - m.d.comb += insn_remu.rvfi_insn.eq(self.rvfi_insn) - m.d.comb += insn_remu.rvfi_pc_rdata.eq(self.rvfi_pc_rdata) - m.d.comb += insn_remu.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) - m.d.comb += insn_remu.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) - m.d.comb += insn_remu.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - m.d.comb += spec_insn_remu_valid.eq(insn_remu.spec_valid) - m.d.comb += spec_insn_remu_trap.eq(insn_remu.spec_trap) - m.d.comb += spec_insn_remu_rs1_addr.eq(insn_remu.spec_rs1_addr) - m.d.comb += spec_insn_remu_rs2_addr.eq(insn_remu.spec_rs2_addr) - m.d.comb += spec_insn_remu_rd_addr.eq(insn_remu.spec_rd_addr) - m.d.comb += spec_insn_remu_rd_wdata.eq(insn_remu.spec_rd_wdata) - m.d.comb += spec_insn_remu_pc_wdata.eq(insn_remu.spec_pc_wdata) - m.d.comb += spec_insn_remu_mem_addr.eq(insn_remu.spec_mem_addr) - m.d.comb += spec_insn_remu_mem_rmask.eq(insn_remu.spec_mem_rmask) - m.d.comb += spec_insn_remu_mem_wmask.eq(insn_remu.spec_mem_wmask) - m.d.comb += spec_insn_remu_mem_wdata.eq(insn_remu.spec_mem_wdata) - - m.d.comb += self.spec_valid.eq(Mux(spec_insn_remu_valid, spec_insn_remu_valid, Mux(spec_insn_rem_valid, spec_insn_rem_valid, Mux(spec_insn_divu_valid, spec_insn_divu_valid, Mux(spec_insn_div_valid, spec_insn_div_valid, Mux(spec_insn_mulhu_valid, spec_insn_mulhu_valid, Mux(spec_insn_mulhsu_valid, spec_insn_mulhsu_valid, Mux(spec_insn_mulh_valid, spec_insn_mulh_valid, Mux(spec_insn_mul_valid, spec_insn_mul_valid, Mux(spec_insn_and_valid, spec_insn_and_valid, Mux(spec_insn_or_valid, spec_insn_or_valid, Mux(spec_insn_sra_valid, spec_insn_sra_valid, Mux(spec_insn_srl_valid, spec_insn_srl_valid, Mux(spec_insn_xor_valid, spec_insn_xor_valid, Mux(spec_insn_sltu_valid, spec_insn_sltu_valid, Mux(spec_insn_slt_valid, spec_insn_slt_valid, Mux(spec_insn_sll_valid, spec_insn_sll_valid, Mux(spec_insn_sub_valid, spec_insn_sub_valid, Mux(spec_insn_add_valid, spec_insn_add_valid, Mux(spec_insn_srai_valid, spec_insn_srai_valid, Mux(spec_insn_srli_valid, spec_insn_srli_valid, Mux(spec_insn_slli_valid, spec_insn_slli_valid, Mux(spec_insn_andi_valid, spec_insn_andi_valid, Mux(spec_insn_ori_valid, spec_insn_ori_valid, Mux(spec_insn_xori_valid, spec_insn_xori_valid, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_valid, Mux(spec_insn_slti_valid, spec_insn_slti_valid, Mux(spec_insn_addi_valid, spec_insn_addi_valid, Mux(spec_insn_sw_valid, spec_insn_sw_valid, Mux(spec_insn_sh_valid, spec_insn_sh_valid, Mux(spec_insn_sb_valid, spec_insn_sb_valid, Mux(spec_insn_lhu_valid, spec_insn_lhu_valid, Mux(spec_insn_lbu_valid, spec_insn_lbu_valid, Mux(spec_insn_lw_valid, spec_insn_lw_valid, Mux(spec_insn_lh_valid, spec_insn_lh_valid, Mux(spec_insn_lb_valid, spec_insn_lb_valid, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_valid, Mux(spec_insn_bltu_valid, spec_insn_bltu_valid, Mux(spec_insn_bge_valid, spec_insn_bge_valid, Mux(spec_insn_blt_valid, spec_insn_blt_valid, Mux(spec_insn_bne_valid, spec_insn_bne_valid, Mux(spec_insn_beq_valid, spec_insn_beq_valid, Mux(spec_insn_jalr_valid, spec_insn_jalr_valid, Mux(spec_insn_jal_valid, spec_insn_jal_valid, Mux(spec_insn_auipc_valid, spec_insn_auipc_valid, Mux(spec_insn_lui_valid, spec_insn_lui_valid, 0)))))))))))))))))))))))))))))))))))))))))))))) - m.d.comb += self.spec_trap.eq(Mux(spec_insn_remu_valid, spec_insn_remu_trap, Mux(spec_insn_rem_valid, spec_insn_rem_trap, Mux(spec_insn_divu_valid, spec_insn_divu_trap, Mux(spec_insn_div_valid, spec_insn_div_trap, Mux(spec_insn_mulhu_valid, spec_insn_mulhu_trap, Mux(spec_insn_mulhsu_valid, spec_insn_mulhsu_trap, Mux(spec_insn_mulh_valid, spec_insn_mulh_trap, Mux(spec_insn_mul_valid, spec_insn_mul_trap, Mux(spec_insn_and_valid, spec_insn_and_trap, Mux(spec_insn_or_valid, spec_insn_or_trap, Mux(spec_insn_sra_valid, spec_insn_sra_trap, Mux(spec_insn_srl_valid, spec_insn_srl_trap, Mux(spec_insn_xor_valid, spec_insn_xor_trap, Mux(spec_insn_sltu_valid, spec_insn_sltu_trap, Mux(spec_insn_slt_valid, spec_insn_slt_trap, Mux(spec_insn_sll_valid, spec_insn_sll_trap, Mux(spec_insn_sub_valid, spec_insn_sub_trap, Mux(spec_insn_add_valid, spec_insn_add_trap, Mux(spec_insn_srai_valid, spec_insn_srai_trap, Mux(spec_insn_srli_valid, spec_insn_srli_trap, Mux(spec_insn_slli_valid, spec_insn_slli_trap, Mux(spec_insn_andi_valid, spec_insn_andi_trap, Mux(spec_insn_ori_valid, spec_insn_ori_trap, Mux(spec_insn_xori_valid, spec_insn_xori_trap, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_trap, Mux(spec_insn_slti_valid, spec_insn_slti_trap, Mux(spec_insn_addi_valid, spec_insn_addi_trap, Mux(spec_insn_sw_valid, spec_insn_sw_trap, Mux(spec_insn_sh_valid, spec_insn_sh_trap, Mux(spec_insn_sb_valid, spec_insn_sb_trap, Mux(spec_insn_lhu_valid, spec_insn_lhu_trap, Mux(spec_insn_lbu_valid, spec_insn_lbu_trap, Mux(spec_insn_lw_valid, spec_insn_lw_trap, Mux(spec_insn_lh_valid, spec_insn_lh_trap, Mux(spec_insn_lb_valid, spec_insn_lb_trap, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_trap, Mux(spec_insn_bltu_valid, spec_insn_bltu_trap, Mux(spec_insn_bge_valid, spec_insn_bge_trap, Mux(spec_insn_blt_valid, spec_insn_blt_trap, Mux(spec_insn_bne_valid, spec_insn_bne_trap, Mux(spec_insn_beq_valid, spec_insn_beq_trap, Mux(spec_insn_jalr_valid, spec_insn_jalr_trap, Mux(spec_insn_jal_valid, spec_insn_jal_trap, Mux(spec_insn_auipc_valid, spec_insn_auipc_trap, Mux(spec_insn_lui_valid, spec_insn_lui_trap, 0)))))))))))))))))))))))))))))))))))))))))))))) - m.d.comb += self.spec_rs1_addr.eq(Mux(spec_insn_remu_valid, spec_insn_remu_rs1_addr, Mux(spec_insn_rem_valid, spec_insn_rem_rs1_addr, Mux(spec_insn_divu_valid, spec_insn_divu_rs1_addr, Mux(spec_insn_div_valid, spec_insn_div_rs1_addr, Mux(spec_insn_mulhu_valid, spec_insn_mulhu_rs1_addr, Mux(spec_insn_mulhsu_valid, spec_insn_mulhsu_rs1_addr, Mux(spec_insn_mulh_valid, spec_insn_mulh_rs1_addr, Mux(spec_insn_mul_valid, spec_insn_mul_rs1_addr, Mux(spec_insn_and_valid, spec_insn_and_rs1_addr, Mux(spec_insn_or_valid, spec_insn_or_rs1_addr, Mux(spec_insn_sra_valid, spec_insn_sra_rs1_addr, Mux(spec_insn_srl_valid, spec_insn_srl_rs1_addr, Mux(spec_insn_xor_valid, spec_insn_xor_rs1_addr, Mux(spec_insn_sltu_valid, spec_insn_sltu_rs1_addr, Mux(spec_insn_slt_valid, spec_insn_slt_rs1_addr, Mux(spec_insn_sll_valid, spec_insn_sll_rs1_addr, Mux(spec_insn_sub_valid, spec_insn_sub_rs1_addr, Mux(spec_insn_add_valid, spec_insn_add_rs1_addr, Mux(spec_insn_srai_valid, spec_insn_srai_rs1_addr, Mux(spec_insn_srli_valid, spec_insn_srli_rs1_addr, Mux(spec_insn_slli_valid, spec_insn_slli_rs1_addr, Mux(spec_insn_andi_valid, spec_insn_andi_rs1_addr, Mux(spec_insn_ori_valid, spec_insn_ori_rs1_addr, Mux(spec_insn_xori_valid, spec_insn_xori_rs1_addr, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_rs1_addr, Mux(spec_insn_slti_valid, spec_insn_slti_rs1_addr, Mux(spec_insn_addi_valid, spec_insn_addi_rs1_addr, Mux(spec_insn_sw_valid, spec_insn_sw_rs1_addr, Mux(spec_insn_sh_valid, spec_insn_sh_rs1_addr, Mux(spec_insn_sb_valid, spec_insn_sb_rs1_addr, Mux(spec_insn_lhu_valid, spec_insn_lhu_rs1_addr, Mux(spec_insn_lbu_valid, spec_insn_lbu_rs1_addr, Mux(spec_insn_lw_valid, spec_insn_lw_rs1_addr, Mux(spec_insn_lh_valid, spec_insn_lh_rs1_addr, Mux(spec_insn_lb_valid, spec_insn_lb_rs1_addr, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_rs1_addr, Mux(spec_insn_bltu_valid, spec_insn_bltu_rs1_addr, Mux(spec_insn_bge_valid, spec_insn_bge_rs1_addr, Mux(spec_insn_blt_valid, spec_insn_blt_rs1_addr, Mux(spec_insn_bne_valid, spec_insn_bne_rs1_addr, Mux(spec_insn_beq_valid, spec_insn_beq_rs1_addr, Mux(spec_insn_jalr_valid, spec_insn_jalr_rs1_addr, Mux(spec_insn_jal_valid, spec_insn_jal_rs1_addr, Mux(spec_insn_auipc_valid, spec_insn_auipc_rs1_addr, Mux(spec_insn_lui_valid, spec_insn_lui_rs1_addr, 0)))))))))))))))))))))))))))))))))))))))))))))) - m.d.comb += self.spec_rs2_addr.eq(Mux(spec_insn_remu_valid, spec_insn_remu_rs2_addr, Mux(spec_insn_rem_valid, spec_insn_rem_rs2_addr, Mux(spec_insn_divu_valid, spec_insn_divu_rs2_addr, Mux(spec_insn_div_valid, spec_insn_div_rs2_addr, Mux(spec_insn_mulhu_valid, spec_insn_mulhu_rs2_addr, Mux(spec_insn_mulhsu_valid, spec_insn_mulhsu_rs2_addr, Mux(spec_insn_mulh_valid, spec_insn_mulh_rs2_addr, Mux(spec_insn_mul_valid, spec_insn_mul_rs2_addr, Mux(spec_insn_and_valid, spec_insn_and_rs2_addr, Mux(spec_insn_or_valid, spec_insn_or_rs2_addr, Mux(spec_insn_sra_valid, spec_insn_sra_rs2_addr, Mux(spec_insn_srl_valid, spec_insn_srl_rs2_addr, Mux(spec_insn_xor_valid, spec_insn_xor_rs2_addr, Mux(spec_insn_sltu_valid, spec_insn_sltu_rs2_addr, Mux(spec_insn_slt_valid, spec_insn_slt_rs2_addr, Mux(spec_insn_sll_valid, spec_insn_sll_rs2_addr, Mux(spec_insn_sub_valid, spec_insn_sub_rs2_addr, Mux(spec_insn_add_valid, spec_insn_add_rs2_addr, Mux(spec_insn_srai_valid, spec_insn_srai_rs2_addr, Mux(spec_insn_srli_valid, spec_insn_srli_rs2_addr, Mux(spec_insn_slli_valid, spec_insn_slli_rs2_addr, Mux(spec_insn_andi_valid, spec_insn_andi_rs2_addr, Mux(spec_insn_ori_valid, spec_insn_ori_rs2_addr, Mux(spec_insn_xori_valid, spec_insn_xori_rs2_addr, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_rs2_addr, Mux(spec_insn_slti_valid, spec_insn_slti_rs2_addr, Mux(spec_insn_addi_valid, spec_insn_addi_rs2_addr, Mux(spec_insn_sw_valid, spec_insn_sw_rs2_addr, Mux(spec_insn_sh_valid, spec_insn_sh_rs2_addr, Mux(spec_insn_sb_valid, spec_insn_sb_rs2_addr, Mux(spec_insn_lhu_valid, spec_insn_lhu_rs2_addr, Mux(spec_insn_lbu_valid, spec_insn_lbu_rs2_addr, Mux(spec_insn_lw_valid, spec_insn_lw_rs2_addr, Mux(spec_insn_lh_valid, spec_insn_lh_rs2_addr, Mux(spec_insn_lb_valid, spec_insn_lb_rs2_addr, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_rs2_addr, Mux(spec_insn_bltu_valid, spec_insn_bltu_rs2_addr, Mux(spec_insn_bge_valid, spec_insn_bge_rs2_addr, Mux(spec_insn_blt_valid, spec_insn_blt_rs2_addr, Mux(spec_insn_bne_valid, spec_insn_bne_rs2_addr, Mux(spec_insn_beq_valid, spec_insn_beq_rs2_addr, Mux(spec_insn_jalr_valid, spec_insn_jalr_rs2_addr, Mux(spec_insn_jal_valid, spec_insn_jal_rs2_addr, Mux(spec_insn_auipc_valid, spec_insn_auipc_rs2_addr, Mux(spec_insn_lui_valid, spec_insn_lui_rs2_addr, 0)))))))))))))))))))))))))))))))))))))))))))))) - m.d.comb += self.spec_rd_addr.eq(Mux(spec_insn_remu_valid, spec_insn_remu_rd_addr, Mux(spec_insn_rem_valid, spec_insn_rem_rd_addr, Mux(spec_insn_divu_valid, spec_insn_divu_rd_addr, Mux(spec_insn_div_valid, spec_insn_div_rd_addr, Mux(spec_insn_mulhu_valid, spec_insn_mulhu_rd_addr, Mux(spec_insn_mulhsu_valid, spec_insn_mulhsu_rd_addr, Mux(spec_insn_mulh_valid, spec_insn_mulh_rd_addr, Mux(spec_insn_mul_valid, spec_insn_mul_rd_addr, Mux(spec_insn_and_valid, spec_insn_and_rd_addr, Mux(spec_insn_or_valid, spec_insn_or_rd_addr, Mux(spec_insn_sra_valid, spec_insn_sra_rd_addr, Mux(spec_insn_srl_valid, spec_insn_srl_rd_addr, Mux(spec_insn_xor_valid, spec_insn_xor_rd_addr, Mux(spec_insn_sltu_valid, spec_insn_sltu_rd_addr, Mux(spec_insn_slt_valid, spec_insn_slt_rd_addr, Mux(spec_insn_sll_valid, spec_insn_sll_rd_addr, Mux(spec_insn_sub_valid, spec_insn_sub_rd_addr, Mux(spec_insn_add_valid, spec_insn_add_rd_addr, Mux(spec_insn_srai_valid, spec_insn_srai_rd_addr, Mux(spec_insn_srli_valid, spec_insn_srli_rd_addr, Mux(spec_insn_slli_valid, spec_insn_slli_rd_addr, Mux(spec_insn_andi_valid, spec_insn_andi_rd_addr, Mux(spec_insn_ori_valid, spec_insn_ori_rd_addr, Mux(spec_insn_xori_valid, spec_insn_xori_rd_addr, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_rd_addr, Mux(spec_insn_slti_valid, spec_insn_slti_rd_addr, Mux(spec_insn_addi_valid, spec_insn_addi_rd_addr, Mux(spec_insn_sw_valid, spec_insn_sw_rd_addr, Mux(spec_insn_sh_valid, spec_insn_sh_rd_addr, Mux(spec_insn_sb_valid, spec_insn_sb_rd_addr, Mux(spec_insn_lhu_valid, spec_insn_lhu_rd_addr, Mux(spec_insn_lbu_valid, spec_insn_lbu_rd_addr, Mux(spec_insn_lw_valid, spec_insn_lw_rd_addr, Mux(spec_insn_lh_valid, spec_insn_lh_rd_addr, Mux(spec_insn_lb_valid, spec_insn_lb_rd_addr, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_rd_addr, Mux(spec_insn_bltu_valid, spec_insn_bltu_rd_addr, Mux(spec_insn_bge_valid, spec_insn_bge_rd_addr, Mux(spec_insn_blt_valid, spec_insn_blt_rd_addr, Mux(spec_insn_bne_valid, spec_insn_bne_rd_addr, Mux(spec_insn_beq_valid, spec_insn_beq_rd_addr, Mux(spec_insn_jalr_valid, spec_insn_jalr_rd_addr, Mux(spec_insn_jal_valid, spec_insn_jal_rd_addr, Mux(spec_insn_auipc_valid, spec_insn_auipc_rd_addr, Mux(spec_insn_lui_valid, spec_insn_lui_rd_addr, 0)))))))))))))))))))))))))))))))))))))))))))))) - m.d.comb += self.spec_rd_wdata.eq(Mux(spec_insn_remu_valid, spec_insn_remu_rd_wdata, Mux(spec_insn_rem_valid, spec_insn_rem_rd_wdata, Mux(spec_insn_divu_valid, spec_insn_divu_rd_wdata, Mux(spec_insn_div_valid, spec_insn_div_rd_wdata, Mux(spec_insn_mulhu_valid, spec_insn_mulhu_rd_wdata, Mux(spec_insn_mulhsu_valid, spec_insn_mulhsu_rd_wdata, Mux(spec_insn_mulh_valid, spec_insn_mulh_rd_wdata, Mux(spec_insn_mul_valid, spec_insn_mul_rd_wdata, Mux(spec_insn_and_valid, spec_insn_and_rd_wdata, Mux(spec_insn_or_valid, spec_insn_or_rd_wdata, Mux(spec_insn_sra_valid, spec_insn_sra_rd_wdata, Mux(spec_insn_srl_valid, spec_insn_srl_rd_wdata, Mux(spec_insn_xor_valid, spec_insn_xor_rd_wdata, Mux(spec_insn_sltu_valid, spec_insn_sltu_rd_wdata, Mux(spec_insn_slt_valid, spec_insn_slt_rd_wdata, Mux(spec_insn_sll_valid, spec_insn_sll_rd_wdata, Mux(spec_insn_sub_valid, spec_insn_sub_rd_wdata, Mux(spec_insn_add_valid, spec_insn_add_rd_wdata, Mux(spec_insn_srai_valid, spec_insn_srai_rd_wdata, Mux(spec_insn_srli_valid, spec_insn_srli_rd_wdata, Mux(spec_insn_slli_valid, spec_insn_slli_rd_wdata, Mux(spec_insn_andi_valid, spec_insn_andi_rd_wdata, Mux(spec_insn_ori_valid, spec_insn_ori_rd_wdata, Mux(spec_insn_xori_valid, spec_insn_xori_rd_wdata, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_rd_wdata, Mux(spec_insn_slti_valid, spec_insn_slti_rd_wdata, Mux(spec_insn_addi_valid, spec_insn_addi_rd_wdata, Mux(spec_insn_sw_valid, spec_insn_sw_rd_wdata, Mux(spec_insn_sh_valid, spec_insn_sh_rd_wdata, Mux(spec_insn_sb_valid, spec_insn_sb_rd_wdata, Mux(spec_insn_lhu_valid, spec_insn_lhu_rd_wdata, Mux(spec_insn_lbu_valid, spec_insn_lbu_rd_wdata, Mux(spec_insn_lw_valid, spec_insn_lw_rd_wdata, Mux(spec_insn_lh_valid, spec_insn_lh_rd_wdata, Mux(spec_insn_lb_valid, spec_insn_lb_rd_wdata, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_rd_wdata, Mux(spec_insn_bltu_valid, spec_insn_bltu_rd_wdata, Mux(spec_insn_bge_valid, spec_insn_bge_rd_wdata, Mux(spec_insn_blt_valid, spec_insn_blt_rd_wdata, Mux(spec_insn_bne_valid, spec_insn_bne_rd_wdata, Mux(spec_insn_beq_valid, spec_insn_beq_rd_wdata, Mux(spec_insn_jalr_valid, spec_insn_jalr_rd_wdata, Mux(spec_insn_jal_valid, spec_insn_jal_rd_wdata, Mux(spec_insn_auipc_valid, spec_insn_auipc_rd_wdata, Mux(spec_insn_lui_valid, spec_insn_lui_rd_wdata, 0)))))))))))))))))))))))))))))))))))))))))))))) - m.d.comb += self.spec_pc_wdata.eq(Mux(spec_insn_remu_valid, spec_insn_remu_pc_wdata, Mux(spec_insn_rem_valid, spec_insn_rem_pc_wdata, Mux(spec_insn_divu_valid, spec_insn_divu_pc_wdata, Mux(spec_insn_div_valid, spec_insn_div_pc_wdata, Mux(spec_insn_mulhu_valid, spec_insn_mulhu_pc_wdata, Mux(spec_insn_mulhsu_valid, spec_insn_mulhsu_pc_wdata, Mux(spec_insn_mulh_valid, spec_insn_mulh_pc_wdata, Mux(spec_insn_mul_valid, spec_insn_mul_pc_wdata, Mux(spec_insn_and_valid, spec_insn_and_pc_wdata, Mux(spec_insn_or_valid, spec_insn_or_pc_wdata, Mux(spec_insn_sra_valid, spec_insn_sra_pc_wdata, Mux(spec_insn_srl_valid, spec_insn_srl_pc_wdata, Mux(spec_insn_xor_valid, spec_insn_xor_pc_wdata, Mux(spec_insn_sltu_valid, spec_insn_sltu_pc_wdata, Mux(spec_insn_slt_valid, spec_insn_slt_pc_wdata, Mux(spec_insn_sll_valid, spec_insn_sll_pc_wdata, Mux(spec_insn_sub_valid, spec_insn_sub_pc_wdata, Mux(spec_insn_add_valid, spec_insn_add_pc_wdata, Mux(spec_insn_srai_valid, spec_insn_srai_pc_wdata, Mux(spec_insn_srli_valid, spec_insn_srli_pc_wdata, Mux(spec_insn_slli_valid, spec_insn_slli_pc_wdata, Mux(spec_insn_andi_valid, spec_insn_andi_pc_wdata, Mux(spec_insn_ori_valid, spec_insn_ori_pc_wdata, Mux(spec_insn_xori_valid, spec_insn_xori_pc_wdata, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_pc_wdata, Mux(spec_insn_slti_valid, spec_insn_slti_pc_wdata, Mux(spec_insn_addi_valid, spec_insn_addi_pc_wdata, Mux(spec_insn_sw_valid, spec_insn_sw_pc_wdata, Mux(spec_insn_sh_valid, spec_insn_sh_pc_wdata, Mux(spec_insn_sb_valid, spec_insn_sb_pc_wdata, Mux(spec_insn_lhu_valid, spec_insn_lhu_pc_wdata, Mux(spec_insn_lbu_valid, spec_insn_lbu_pc_wdata, Mux(spec_insn_lw_valid, spec_insn_lw_pc_wdata, Mux(spec_insn_lh_valid, spec_insn_lh_pc_wdata, Mux(spec_insn_lb_valid, spec_insn_lb_pc_wdata, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_pc_wdata, Mux(spec_insn_bltu_valid, spec_insn_bltu_pc_wdata, Mux(spec_insn_bge_valid, spec_insn_bge_pc_wdata, Mux(spec_insn_blt_valid, spec_insn_blt_pc_wdata, Mux(spec_insn_bne_valid, spec_insn_bne_pc_wdata, Mux(spec_insn_beq_valid, spec_insn_beq_pc_wdata, Mux(spec_insn_jalr_valid, spec_insn_jalr_pc_wdata, Mux(spec_insn_jal_valid, spec_insn_jal_pc_wdata, Mux(spec_insn_auipc_valid, spec_insn_auipc_pc_wdata, Mux(spec_insn_lui_valid, spec_insn_lui_pc_wdata, 0)))))))))))))))))))))))))))))))))))))))))))))) - m.d.comb += self.spec_mem_addr.eq(Mux(spec_insn_remu_valid, spec_insn_remu_mem_addr, Mux(spec_insn_rem_valid, spec_insn_rem_mem_addr, Mux(spec_insn_divu_valid, spec_insn_divu_mem_addr, Mux(spec_insn_div_valid, spec_insn_div_mem_addr, Mux(spec_insn_mulhu_valid, spec_insn_mulhu_mem_addr, Mux(spec_insn_mulhsu_valid, spec_insn_mulhsu_mem_addr, Mux(spec_insn_mulh_valid, spec_insn_mulh_mem_addr, Mux(spec_insn_mul_valid, spec_insn_mul_mem_addr, Mux(spec_insn_and_valid, spec_insn_and_mem_addr, Mux(spec_insn_or_valid, spec_insn_or_mem_addr, Mux(spec_insn_sra_valid, spec_insn_sra_mem_addr, Mux(spec_insn_srl_valid, spec_insn_srl_mem_addr, Mux(spec_insn_xor_valid, spec_insn_xor_mem_addr, Mux(spec_insn_sltu_valid, spec_insn_sltu_mem_addr, Mux(spec_insn_slt_valid, spec_insn_slt_mem_addr, Mux(spec_insn_sll_valid, spec_insn_sll_mem_addr, Mux(spec_insn_sub_valid, spec_insn_sub_mem_addr, Mux(spec_insn_add_valid, spec_insn_add_mem_addr, Mux(spec_insn_srai_valid, spec_insn_srai_mem_addr, Mux(spec_insn_srli_valid, spec_insn_srli_mem_addr, Mux(spec_insn_slli_valid, spec_insn_slli_mem_addr, Mux(spec_insn_andi_valid, spec_insn_andi_mem_addr, Mux(spec_insn_ori_valid, spec_insn_ori_mem_addr, Mux(spec_insn_xori_valid, spec_insn_xori_mem_addr, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_mem_addr, Mux(spec_insn_slti_valid, spec_insn_slti_mem_addr, Mux(spec_insn_addi_valid, spec_insn_addi_mem_addr, Mux(spec_insn_sw_valid, spec_insn_sw_mem_addr, Mux(spec_insn_sh_valid, spec_insn_sh_mem_addr, Mux(spec_insn_sb_valid, spec_insn_sb_mem_addr, Mux(spec_insn_lhu_valid, spec_insn_lhu_mem_addr, Mux(spec_insn_lbu_valid, spec_insn_lbu_mem_addr, Mux(spec_insn_lw_valid, spec_insn_lw_mem_addr, Mux(spec_insn_lh_valid, spec_insn_lh_mem_addr, Mux(spec_insn_lb_valid, spec_insn_lb_mem_addr, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_mem_addr, Mux(spec_insn_bltu_valid, spec_insn_bltu_mem_addr, Mux(spec_insn_bge_valid, spec_insn_bge_mem_addr, Mux(spec_insn_blt_valid, spec_insn_blt_mem_addr, Mux(spec_insn_bne_valid, spec_insn_bne_mem_addr, Mux(spec_insn_beq_valid, spec_insn_beq_mem_addr, Mux(spec_insn_jalr_valid, spec_insn_jalr_mem_addr, Mux(spec_insn_jal_valid, spec_insn_jal_mem_addr, Mux(spec_insn_auipc_valid, spec_insn_auipc_mem_addr, Mux(spec_insn_lui_valid, spec_insn_lui_mem_addr, 0)))))))))))))))))))))))))))))))))))))))))))))) - m.d.comb += self.spec_mem_rmask.eq(Mux(spec_insn_remu_valid, spec_insn_remu_mem_rmask, Mux(spec_insn_rem_valid, spec_insn_rem_mem_rmask, Mux(spec_insn_divu_valid, spec_insn_divu_mem_rmask, Mux(spec_insn_div_valid, spec_insn_div_mem_rmask, Mux(spec_insn_mulhu_valid, spec_insn_mulhu_mem_rmask, Mux(spec_insn_mulhsu_valid, spec_insn_mulhsu_mem_rmask, Mux(spec_insn_mulh_valid, spec_insn_mulh_mem_rmask, Mux(spec_insn_mul_valid, spec_insn_mul_mem_rmask, Mux(spec_insn_and_valid, spec_insn_and_mem_rmask, Mux(spec_insn_or_valid, spec_insn_or_mem_rmask, Mux(spec_insn_sra_valid, spec_insn_sra_mem_rmask, Mux(spec_insn_srl_valid, spec_insn_srl_mem_rmask, Mux(spec_insn_xor_valid, spec_insn_xor_mem_rmask, Mux(spec_insn_sltu_valid, spec_insn_sltu_mem_rmask, Mux(spec_insn_slt_valid, spec_insn_slt_mem_rmask, Mux(spec_insn_sll_valid, spec_insn_sll_mem_rmask, Mux(spec_insn_sub_valid, spec_insn_sub_mem_rmask, Mux(spec_insn_add_valid, spec_insn_add_mem_rmask, Mux(spec_insn_srai_valid, spec_insn_srai_mem_rmask, Mux(spec_insn_srli_valid, spec_insn_srli_mem_rmask, Mux(spec_insn_slli_valid, spec_insn_slli_mem_rmask, Mux(spec_insn_andi_valid, spec_insn_andi_mem_rmask, Mux(spec_insn_ori_valid, spec_insn_ori_mem_rmask, Mux(spec_insn_xori_valid, spec_insn_xori_mem_rmask, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_mem_rmask, Mux(spec_insn_slti_valid, spec_insn_slti_mem_rmask, Mux(spec_insn_addi_valid, spec_insn_addi_mem_rmask, Mux(spec_insn_sw_valid, spec_insn_sw_mem_rmask, Mux(spec_insn_sh_valid, spec_insn_sh_mem_rmask, Mux(spec_insn_sb_valid, spec_insn_sb_mem_rmask, Mux(spec_insn_lhu_valid, spec_insn_lhu_mem_rmask, Mux(spec_insn_lbu_valid, spec_insn_lbu_mem_rmask, Mux(spec_insn_lw_valid, spec_insn_lw_mem_rmask, Mux(spec_insn_lh_valid, spec_insn_lh_mem_rmask, Mux(spec_insn_lb_valid, spec_insn_lb_mem_rmask, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_mem_rmask, Mux(spec_insn_bltu_valid, spec_insn_bltu_mem_rmask, Mux(spec_insn_bge_valid, spec_insn_bge_mem_rmask, Mux(spec_insn_blt_valid, spec_insn_blt_mem_rmask, Mux(spec_insn_bne_valid, spec_insn_bne_mem_rmask, Mux(spec_insn_beq_valid, spec_insn_beq_mem_rmask, Mux(spec_insn_jalr_valid, spec_insn_jalr_mem_rmask, Mux(spec_insn_jal_valid, spec_insn_jal_mem_rmask, Mux(spec_insn_auipc_valid, spec_insn_auipc_mem_rmask, Mux(spec_insn_lui_valid, spec_insn_lui_mem_rmask, 0)))))))))))))))))))))))))))))))))))))))))))))) - m.d.comb += self.spec_mem_wmask.eq(Mux(spec_insn_remu_valid, spec_insn_remu_mem_wmask, Mux(spec_insn_rem_valid, spec_insn_rem_mem_wmask, Mux(spec_insn_divu_valid, spec_insn_divu_mem_wmask, Mux(spec_insn_div_valid, spec_insn_div_mem_wmask, Mux(spec_insn_mulhu_valid, spec_insn_mulhu_mem_wmask, Mux(spec_insn_mulhsu_valid, spec_insn_mulhsu_mem_wmask, Mux(spec_insn_mulh_valid, spec_insn_mulh_mem_wmask, Mux(spec_insn_mul_valid, spec_insn_mul_mem_wmask, Mux(spec_insn_and_valid, spec_insn_and_mem_wmask, Mux(spec_insn_or_valid, spec_insn_or_mem_wmask, Mux(spec_insn_sra_valid, spec_insn_sra_mem_wmask, Mux(spec_insn_srl_valid, spec_insn_srl_mem_wmask, Mux(spec_insn_xor_valid, spec_insn_xor_mem_wmask, Mux(spec_insn_sltu_valid, spec_insn_sltu_mem_wmask, Mux(spec_insn_slt_valid, spec_insn_slt_mem_wmask, Mux(spec_insn_sll_valid, spec_insn_sll_mem_wmask, Mux(spec_insn_sub_valid, spec_insn_sub_mem_wmask, Mux(spec_insn_add_valid, spec_insn_add_mem_wmask, Mux(spec_insn_srai_valid, spec_insn_srai_mem_wmask, Mux(spec_insn_srli_valid, spec_insn_srli_mem_wmask, Mux(spec_insn_slli_valid, spec_insn_slli_mem_wmask, Mux(spec_insn_andi_valid, spec_insn_andi_mem_wmask, Mux(spec_insn_ori_valid, spec_insn_ori_mem_wmask, Mux(spec_insn_xori_valid, spec_insn_xori_mem_wmask, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_mem_wmask, Mux(spec_insn_slti_valid, spec_insn_slti_mem_wmask, Mux(spec_insn_addi_valid, spec_insn_addi_mem_wmask, Mux(spec_insn_sw_valid, spec_insn_sw_mem_wmask, Mux(spec_insn_sh_valid, spec_insn_sh_mem_wmask, Mux(spec_insn_sb_valid, spec_insn_sb_mem_wmask, Mux(spec_insn_lhu_valid, spec_insn_lhu_mem_wmask, Mux(spec_insn_lbu_valid, spec_insn_lbu_mem_wmask, Mux(spec_insn_lw_valid, spec_insn_lw_mem_wmask, Mux(spec_insn_lh_valid, spec_insn_lh_mem_wmask, Mux(spec_insn_lb_valid, spec_insn_lb_mem_wmask, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_mem_wmask, Mux(spec_insn_bltu_valid, spec_insn_bltu_mem_wmask, Mux(spec_insn_bge_valid, spec_insn_bge_mem_wmask, Mux(spec_insn_blt_valid, spec_insn_blt_mem_wmask, Mux(spec_insn_bne_valid, spec_insn_bne_mem_wmask, Mux(spec_insn_beq_valid, spec_insn_beq_mem_wmask, Mux(spec_insn_jalr_valid, spec_insn_jalr_mem_wmask, Mux(spec_insn_jal_valid, spec_insn_jal_mem_wmask, Mux(spec_insn_auipc_valid, spec_insn_auipc_mem_wmask, Mux(spec_insn_lui_valid, spec_insn_lui_mem_wmask, 0)))))))))))))))))))))))))))))))))))))))))))))) - m.d.comb += self.spec_mem_wdata.eq(Mux(spec_insn_remu_valid, spec_insn_remu_mem_wdata, Mux(spec_insn_rem_valid, spec_insn_rem_mem_wdata, Mux(spec_insn_divu_valid, spec_insn_divu_mem_wdata, Mux(spec_insn_div_valid, spec_insn_div_mem_wdata, Mux(spec_insn_mulhu_valid, spec_insn_mulhu_mem_wdata, Mux(spec_insn_mulhsu_valid, spec_insn_mulhsu_mem_wdata, Mux(spec_insn_mulh_valid, spec_insn_mulh_mem_wdata, Mux(spec_insn_mul_valid, spec_insn_mul_mem_wdata, Mux(spec_insn_and_valid, spec_insn_and_mem_wdata, Mux(spec_insn_or_valid, spec_insn_or_mem_wdata, Mux(spec_insn_sra_valid, spec_insn_sra_mem_wdata, Mux(spec_insn_srl_valid, spec_insn_srl_mem_wdata, Mux(spec_insn_xor_valid, spec_insn_xor_mem_wdata, Mux(spec_insn_sltu_valid, spec_insn_sltu_mem_wdata, Mux(spec_insn_slt_valid, spec_insn_slt_mem_wdata, Mux(spec_insn_sll_valid, spec_insn_sll_mem_wdata, Mux(spec_insn_sub_valid, spec_insn_sub_mem_wdata, Mux(spec_insn_add_valid, spec_insn_add_mem_wdata, Mux(spec_insn_srai_valid, spec_insn_srai_mem_wdata, Mux(spec_insn_srli_valid, spec_insn_srli_mem_wdata, Mux(spec_insn_slli_valid, spec_insn_slli_mem_wdata, Mux(spec_insn_andi_valid, spec_insn_andi_mem_wdata, Mux(spec_insn_ori_valid, spec_insn_ori_mem_wdata, Mux(spec_insn_xori_valid, spec_insn_xori_mem_wdata, Mux(spec_insn_sltiu_valid, spec_insn_sltiu_mem_wdata, Mux(spec_insn_slti_valid, spec_insn_slti_mem_wdata, Mux(spec_insn_addi_valid, spec_insn_addi_mem_wdata, Mux(spec_insn_sw_valid, spec_insn_sw_mem_wdata, Mux(spec_insn_sh_valid, spec_insn_sh_mem_wdata, Mux(spec_insn_sb_valid, spec_insn_sb_mem_wdata, Mux(spec_insn_lhu_valid, spec_insn_lhu_mem_wdata, Mux(spec_insn_lbu_valid, spec_insn_lbu_mem_wdata, Mux(spec_insn_lw_valid, spec_insn_lw_mem_wdata, Mux(spec_insn_lh_valid, spec_insn_lh_mem_wdata, Mux(spec_insn_lb_valid, spec_insn_lb_mem_wdata, Mux(spec_insn_bgeu_valid, spec_insn_bgeu_mem_wdata, Mux(spec_insn_bltu_valid, spec_insn_bltu_mem_wdata, Mux(spec_insn_bge_valid, spec_insn_bge_mem_wdata, Mux(spec_insn_blt_valid, spec_insn_blt_mem_wdata, Mux(spec_insn_bne_valid, spec_insn_bne_mem_wdata, Mux(spec_insn_beq_valid, spec_insn_beq_mem_wdata, Mux(spec_insn_jalr_valid, spec_insn_jalr_mem_wdata, Mux(spec_insn_jal_valid, spec_insn_jal_mem_wdata, Mux(spec_insn_auipc_valid, spec_insn_auipc_mem_wdata, Mux(spec_insn_lui_valid, spec_insn_lui_mem_wdata, 0)))))))))))))))))))))))))))))))))))))))))))))) - - return m diff --git a/insns/isa_rv32im.txt b/insns/isa_rv32im.txt deleted file mode 100644 index f5412b3..0000000 --- a/insns/isa_rv32im.txt +++ /dev/null @@ -1,45 +0,0 @@ -lui -auipc -jal -jalr -beq -bne -blt -bge -bltu -bgeu -lb -lh -lw -lbu -lhu -sb -sh -sw -addi -slti -sltiu -xori -ori -andi -slli -srli -srai -add -sub -sll -slt -sltu -xor -srl -sra -or -and -mul -mulh -mulhsu -mulhu -div -divu -rem -remu diff --git a/insns/isa_rv32im_gen.py b/insns/isa_rv32im_gen.py deleted file mode 100644 index 3998357..0000000 --- a/insns/isa_rv32im_gen.py +++ /dev/null @@ -1,107 +0,0 @@ -with open('isa_rv32im.py', 'w') as isa_rv32im: - def fprint(strng): - print(strng, file=isa_rv32im) - fprint("# Generated by isa_rv32im_gen.py") - fprint("from nmigen import *") - with open('isa_rv32im.txt', 'r') as isa_rv32im_txt_file: - isa_rv32im_insns = isa_rv32im_txt_file.read().split('\n')[:-1] - for isa_rv32im_insn in isa_rv32im_insns: - fprint("from insn_%s import *" % isa_rv32im_insn) - fprint("") - fprint("class rvfi_isa_rv32im(Elaboratable):") - fprint(" def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):") - fprint(" self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN") - fprint(" self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN") - fprint(" self.rvfi_valid = Signal(1)") - fprint(" self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)") - fprint(" self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)") - fprint(" self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)") - fprint(" self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)") - fprint(" self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)") - fprint("") - fprint(" self.spec_valid = Signal(1)") - fprint(" self.spec_trap = Signal(1)") - fprint(" self.spec_rs1_addr = Signal(5)") - fprint(" self.spec_rs2_addr = Signal(5)") - fprint(" self.spec_rd_addr = Signal(5)") - fprint(" self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)") - fprint(" self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)") - fprint(" self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)") - fprint(" self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))") - fprint(" self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))") - fprint(" self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)") - fprint(" def ports(self):") - fprint(" input_ports = [") - fprint(" self.rvfi_valid,") - fprint(" self.rvfi_insn,") - fprint(" self.rvfi_pc_rdata,") - fprint(" self.rvfi_rs1_rdata,") - fprint(" self.rvfi_rs2_rdata,") - fprint(" self.rvfi_mem_rdata") - fprint(" ]") - fprint(" output_ports = [") - fprint(" self.spec_valid,") - fprint(" self.spec_trap,") - fprint(" self.spec_rs1_addr,") - fprint(" self.spec_rs2_addr,") - fprint(" self.spec_rd_addr,") - fprint(" self.spec_rd_wdata,") - fprint(" self.spec_pc_wdata,") - fprint(" self.spec_mem_addr,") - fprint(" self.spec_mem_rmask,") - fprint(" self.spec_mem_wmask,") - fprint(" self.spec_mem_wdata") - fprint(" ]") - fprint(" return input_ports + output_ports") - fprint(" def elaborate(self, platform):") - fprint(" m = Module()") - fprint("") - for isa_rv32im_insn in isa_rv32im_insns: - fprint(" spec_insn_%s_valid = Signal(1)" % isa_rv32im_insn) - fprint(" spec_insn_%s_trap = Signal(1)" % isa_rv32im_insn) - fprint(" spec_insn_%s_rs1_addr = Signal(5)" % isa_rv32im_insn) - fprint(" spec_insn_%s_rs2_addr = Signal(5)" % isa_rv32im_insn) - fprint(" spec_insn_%s_rd_addr = Signal(5)" % isa_rv32im_insn) - fprint(" spec_insn_%s_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)" % isa_rv32im_insn) - fprint(" spec_insn_%s_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)" % isa_rv32im_insn) - fprint(" spec_insn_%s_mem_addr = Signal(self.RISCV_FORMAL_XLEN)" % isa_rv32im_insn) - fprint(" spec_insn_%s_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))" % isa_rv32im_insn) - fprint(" spec_insn_%s_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))" % isa_rv32im_insn) - fprint(" spec_insn_%s_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)" % isa_rv32im_insn) - fprint(" m.submodules.insn_%s = insn_%s = rvfi_insn_%s()" % (isa_rv32im_insn, isa_rv32im_insn, isa_rv32im_insn)) - fprint(" m.d.comb += insn_%s.rvfi_valid.eq(self.rvfi_valid)" % isa_rv32im_insn) - fprint(" m.d.comb += insn_%s.rvfi_insn.eq(self.rvfi_insn)" % isa_rv32im_insn) - fprint(" m.d.comb += insn_%s.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)" % isa_rv32im_insn) - fprint(" m.d.comb += insn_%s.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)" % isa_rv32im_insn) - fprint(" m.d.comb += insn_%s.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)" % isa_rv32im_insn) - fprint(" m.d.comb += insn_%s.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)" % isa_rv32im_insn) - fprint(" m.d.comb += spec_insn_%s_valid.eq(insn_%s.spec_valid)" % (isa_rv32im_insn, isa_rv32im_insn)) - fprint(" m.d.comb += spec_insn_%s_trap.eq(insn_%s.spec_trap)" % (isa_rv32im_insn, isa_rv32im_insn)) - fprint(" m.d.comb += spec_insn_%s_rs1_addr.eq(insn_%s.spec_rs1_addr)" % (isa_rv32im_insn, isa_rv32im_insn)) - fprint(" m.d.comb += spec_insn_%s_rs2_addr.eq(insn_%s.spec_rs2_addr)" % (isa_rv32im_insn, isa_rv32im_insn)) - fprint(" m.d.comb += spec_insn_%s_rd_addr.eq(insn_%s.spec_rd_addr)" % (isa_rv32im_insn, isa_rv32im_insn)) - fprint(" m.d.comb += spec_insn_%s_rd_wdata.eq(insn_%s.spec_rd_wdata)" % (isa_rv32im_insn, isa_rv32im_insn)) - fprint(" m.d.comb += spec_insn_%s_pc_wdata.eq(insn_%s.spec_pc_wdata)" % (isa_rv32im_insn, isa_rv32im_insn)) - fprint(" m.d.comb += spec_insn_%s_mem_addr.eq(insn_%s.spec_mem_addr)" % (isa_rv32im_insn, isa_rv32im_insn)) - fprint(" m.d.comb += spec_insn_%s_mem_rmask.eq(insn_%s.spec_mem_rmask)" % (isa_rv32im_insn, isa_rv32im_insn)) - fprint(" m.d.comb += spec_insn_%s_mem_wmask.eq(insn_%s.spec_mem_wmask)" % (isa_rv32im_insn, isa_rv32im_insn)) - fprint(" m.d.comb += spec_insn_%s_mem_wdata.eq(insn_%s.spec_mem_wdata)" % (isa_rv32im_insn, isa_rv32im_insn)) - fprint("") - def gen_spec(strng): - result = "0" - for isa_rv32im_insn in isa_rv32im_insns: - result = "Mux(spec_insn_%s_valid, spec_insn_%s_%s, %s)" % (isa_rv32im_insn, isa_rv32im_insn, strng, result) - fprint(" m.d.comb += self.spec_%s.eq(%s)" % (strng, result)) - gen_spec("valid") - gen_spec("trap") - gen_spec("rs1_addr") - gen_spec("rs2_addr") - gen_spec("rd_addr") - gen_spec("rd_wdata") - gen_spec("pc_wdata") - gen_spec("mem_addr") - gen_spec("mem_rmask") - gen_spec("mem_wmask") - gen_spec("mem_wdata") - fprint("") - fprint(" return m")