diff --git a/rvfi/insns/insn_addiw.py b/rvfi/insns/insn_addiw.py
new file mode 100644
index 0000000..13443a8
--- /dev/null
+++ b/rvfi/insns/insn_addiw.py
@@ -0,0 +1,19 @@
+from .insn_rv64i_i_type import *
+
+"""
+ADDIW instruction
+"""
+
+class InsnAddiw(InsnRV64IIType):
+    def elaborate(self, platform):
+        m = super().elaborate(platform)
+
+        result = Signal(32)
+        m.d.comb += result.eq(self.rvfi_rs1_rdata[:32] + self.insn_imm[:32])
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b0011011))
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
+        m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
+        m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, (Mux(result[31], 2 ** (self.params.xlen - 32) - 1, 0) << 32) | result, 0))
+        m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
+
+        return m