From 371fcc81c11993625bd75f4cf28583f765ef21e3 Mon Sep 17 00:00:00 2001
From: Donald Sebastian Leung <dl@m-labs.hk>
Date: Tue, 11 Aug 2020 17:25:57 +0800
Subject: [PATCH] Add RV32I U-Type Instruction Format

---
 insns/InsnRV32IUType.py | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)
 create mode 100644 insns/InsnRV32IUType.py

diff --git a/insns/InsnRV32IUType.py b/insns/InsnRV32IUType.py
new file mode 100644
index 0000000..4016206
--- /dev/null
+++ b/insns/InsnRV32IUType.py
@@ -0,0 +1,26 @@
+from Insn import *
+
+"""
+RV32I U-Type Instruction
+"""
+
+class InsnRV32IUType(Insn):
+    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, opcode):
+        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED)
+        self.opcode = opcode
+    def elaborate(self, platform):
+        m = super().elaborate(platform)
+
+        m.d.comb += self.insn_imm.eq(Value.as_signed(self.rvfi_insn[12:32] << 12))
+
+        if self.RISCV_FORMAL_CSR_MISA:
+            m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0)
+            m.d.comb += self.spec_csr_misa_rmask.eq(0)
+        else:
+            m.d.comb += self.misa_ok.eq(1)
+
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_opcode == self.opcode))
+        m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
+        m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
+
+        return m