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Complete generator for RV32I ISA

This commit is contained in:
Donald Sebastian Leung 2020-07-23 14:33:25 +08:00
parent 2e7cc106aa
commit 35a53071aa
2 changed files with 1209 additions and 11 deletions
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1162
insns/isa_rv32i.py
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58
insns/isa_rv32i_gen.py
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@ -3,6 +3,10 @@ with open('isa_rv32i.py', 'w') as isa_rv32i:
print(strng, file=isa_rv32i) print(strng, file=isa_rv32i)
fprint("# Generated by isa_rv32i_gen.py") fprint("# Generated by isa_rv32i_gen.py")
fprint("from nmigen import *") fprint("from nmigen import *")
with open('isa_rv32i.txt', 'r') as isa_rv32i_txt_file:
isa_rv32i_insns = isa_rv32i_txt_file.read().split('\n')[:-1]
for isa_rv32i_insn in isa_rv32i_insns:
fprint("from insn_%s import *" % isa_rv32i_insn)
fprint("") fprint("")
fprint("class rvfi_isa_rv32i(Elaboratable):") fprint("class rvfi_isa_rv32i(Elaboratable):")
fprint(" def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):") fprint(" def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):")
@ -52,12 +56,52 @@ with open('isa_rv32i.py', 'w') as isa_rv32i:
fprint(" def elaborate(self, platform):") fprint(" def elaborate(self, platform):")
fprint(" m = Module()") fprint(" m = Module()")
fprint("") fprint("")
# TODO for isa_rv32i_insn in isa_rv32i_insns:
fprint(" spec_insn_%s_valid = Signal(1)" % isa_rv32i_insn)
fprint(" spec_insn_%s_trap = Signal(1)" % isa_rv32i_insn)
fprint(" spec_insn_%s_rs1_addr = Signal(5)" % isa_rv32i_insn)
fprint(" spec_insn_%s_rs2_addr = Signal(5)" % isa_rv32i_insn)
fprint(" spec_insn_%s_rd_addr = Signal(5)" % isa_rv32i_insn)
fprint(" spec_insn_%s_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)" % isa_rv32i_insn)
fprint(" spec_insn_%s_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)" % isa_rv32i_insn)
fprint(" spec_insn_%s_mem_addr = Signal(self.RISCV_FORMAL_XLEN)" % isa_rv32i_insn)
fprint(" spec_insn_%s_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))" % isa_rv32i_insn)
fprint(" spec_insn_%s_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))" % isa_rv32i_insn)
fprint(" spec_insn_%s_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)" % isa_rv32i_insn)
fprint(" m.submodules.insn_%s = insn_%s = rvfi_insn_%s()" % (isa_rv32i_insn, isa_rv32i_insn, isa_rv32i_insn))
fprint(" m.d.comb += insn_%s.rvfi_valid.eq(self.rvfi_valid)" % isa_rv32i_insn)
fprint(" m.d.comb += insn_%s.rvfi_insn.eq(self.rvfi_insn)" % isa_rv32i_insn)
fprint(" m.d.comb += insn_%s.rvfi_pc_rdata.eq(self.rvfi_pc_rdata)" % isa_rv32i_insn)
fprint(" m.d.comb += insn_%s.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)" % isa_rv32i_insn)
fprint(" m.d.comb += insn_%s.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)" % isa_rv32i_insn)
fprint(" m.d.comb += insn_%s.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)" % isa_rv32i_insn)
fprint(" m.d.comb += spec_insn_%s_valid.eq(insn_%s.spec_valid)" % (isa_rv32i_insn, isa_rv32i_insn))
fprint(" m.d.comb += spec_insn_%s_trap.eq(insn_%s.spec_trap)" % (isa_rv32i_insn, isa_rv32i_insn))
fprint(" m.d.comb += spec_insn_%s_rs1_addr.eq(insn_%s.spec_rs1_addr)" % (isa_rv32i_insn, isa_rv32i_insn))
fprint(" m.d.comb += spec_insn_%s_rs2_addr.eq(insn_%s.spec_rs2_addr)" % (isa_rv32i_insn, isa_rv32i_insn))
fprint(" m.d.comb += spec_insn_%s_rd_addr.eq(insn_%s.spec_rd_addr)" % (isa_rv32i_insn, isa_rv32i_insn))
fprint(" m.d.comb += spec_insn_%s_rd_wdata.eq(insn_%s.spec_rd_wdata)" % (isa_rv32i_insn, isa_rv32i_insn))
fprint(" m.d.comb += spec_insn_%s_pc_wdata.eq(insn_%s.spec_pc_wdata)" % (isa_rv32i_insn, isa_rv32i_insn))
fprint(" m.d.comb += spec_insn_%s_mem_addr.eq(insn_%s.spec_mem_addr)" % (isa_rv32i_insn, isa_rv32i_insn))
fprint(" m.d.comb += spec_insn_%s_mem_rmask.eq(insn_%s.spec_mem_rmask)" % (isa_rv32i_insn, isa_rv32i_insn))
fprint(" m.d.comb += spec_insn_%s_mem_wmask.eq(insn_%s.spec_mem_wmask)" % (isa_rv32i_insn, isa_rv32i_insn))
fprint(" m.d.comb += spec_insn_%s_mem_wdata.eq(insn_%s.spec_mem_wdata)" % (isa_rv32i_insn, isa_rv32i_insn))
fprint("")
def gen_spec(strng):
result = "0"
for isa_rv32i_insn in isa_rv32i_insns:
result = "Mux(spec_insn_%s_valid, spec_insn_%s_%s, %s)" % (isa_rv32i_insn, isa_rv32i_insn, strng, result)
fprint(" m.d.comb += self.spec_%s.eq(%s)" % (strng, result))
gen_spec("valid")
gen_spec("trap")
gen_spec("rs1_addr")
gen_spec("rs2_addr")
gen_spec("rd_addr")
gen_spec("rd_wdata")
gen_spec("pc_wdata")
gen_spec("mem_addr")
gen_spec("mem_rmask")
gen_spec("mem_wmask")
gen_spec("mem_wdata")
fprint("") fprint("")
fprint(" return m") fprint(" return m")
# For debugging purposes only
fprint("")
fprint("test = rvfi_isa_rv32i()")
fprint("test.ports()")
fprint("test.elaborate(platform=None)")