From 33ecb317b2b91c1d1c1825c95d530252605c153c Mon Sep 17 00:00:00 2001
From: Donald Sebastian Leung
Date: Mon, 3 Aug 2020 10:19:01 +0800
Subject: [PATCH] Add SB-type instruction
---
insns/insn_SB.py | 38 ++++++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
create mode 100644 insns/insn_SB.py
diff --git a/insns/insn_SB.py b/insns/insn_SB.py
new file mode 100644
index 0000000..352f0c6
--- /dev/null
+++ b/insns/insn_SB.py
@@ -0,0 +1,38 @@
+from insn import *
+
+class rvfi_insn_SB(rvfi_insn):
+ def __init__(self):
+ super(rvfi_insn_SB, self).__init__()
+ self.insn_padding = Signal(32)
+ self.insn_imm = Signal(32)
+ self.insn_rs2 = Signal(5)
+ self.insn_rs1 = Signal(5)
+ self.insn_funct3 = Signal(3)
+ self.insn_opcode = Signal(7)
+ self.misa_ok = Signal(1)
+ self.ialign16 = Signal(1)
+ def ports(self):
+ return super(rvfi_insn_SB, self).ports()
+ def elaborate(self, platform):
+ m = super(rvfi_insn_SB, self).elaborate(platform)
+
+ # SB-type instruction format
+ m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32)
+ m.d.comb += self.insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[8:12], self.rvfi_insn[25:31], self.rvfi_insn[7], self.rvfi_insn[31]) << 1))
+ m.d.comb += self.insn_rs2.eq(self.rvfi_insn[20:25])
+ m.d.comb += self.insn_rs1.eq(self.rvfi_insn[15:20])
+ m.d.comb += self.insn_funct3.eq(self.rvfi_insn[12:15])
+ m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7])
+
+ m.d.comb += self.misa_ok.eq(1)
+ m.d.comb += self.ialign16.eq(0)
+
+ # default assignments
+ m.d.comb += self.spec_rd_addr.eq(0)
+ m.d.comb += self.spec_rd_wdata.eq(0)
+ m.d.comb += self.spec_mem_addr.eq(0)
+ m.d.comb += self.spec_mem_rmask.eq(0)
+ m.d.comb += self.spec_mem_wmask.eq(0)
+ m.d.comb += self.spec_mem_wdata.eq(0)
+
+ return m