From 31753e36791b46f9db7b664fee06577dcdc7c7b5 Mon Sep 17 00:00:00 2001
From: Donald Sebastian Leung <dl@m-labs.hk>
Date: Mon, 10 Aug 2020 17:35:43 +0800
Subject: [PATCH] Add ANDI instruction

---
 insns/InsnAndi.py | 15 +++++++++++++++
 1 file changed, 15 insertions(+)
 create mode 100644 insns/InsnAndi.py

diff --git a/insns/InsnAndi.py b/insns/InsnAndi.py
new file mode 100644
index 0000000..aa6c054
--- /dev/null
+++ b/insns/InsnAndi.py
@@ -0,0 +1,15 @@
+from InsnRV32IITypeArith import *
+
+"""
+ANDI instruction
+"""
+
+class InsnAndi(InsnRV32IITypeArith):
+    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED):
+        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b111)
+    def elaborate(self, platform):
+        m = super().elaborate(platform)
+
+        m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata & self.insn_imm, 0))
+
+        return m