From 28949f36f42421cd1bc27b5330b9f56fddf54fb8 Mon Sep 17 00:00:00 2001
From: Donald Sebastian Leung
Date: Thu, 13 Aug 2020 13:46:16 +0800
Subject: [PATCH] Fix typo in InsnSw.py
---
insns/InsnSw.py | 2 +-
insns/IsaRV32I.py | 148 ++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 149 insertions(+), 1 deletion(-)
create mode 100644 insns/IsaRV32I.py
diff --git a/insns/InsnSw.py b/insns/InsnSw.py
index 9db387f..cd17787 100644
--- a/insns/InsnSw.py
+++ b/insns/InsnSw.py
@@ -4,6 +4,6 @@ from InsnRV32ISType import *
SW instruction
"""
-class InshSw(InsnRV32ISType):
+class InsnSw(InsnRV32ISType):
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM):
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM, 0b010, 4)
diff --git a/insns/IsaRV32I.py b/insns/IsaRV32I.py
new file mode 100644
index 0000000..e895d8d
--- /dev/null
+++ b/insns/IsaRV32I.py
@@ -0,0 +1,148 @@
+from InsnLui import *
+from InsnAuipc import *
+from InsnJal import *
+from InsnJalr import *
+from InsnBeq import *
+from InsnBne import *
+from InsnBlt import *
+from InsnBge import *
+from InsnBltu import *
+from InsnBgeu import *
+from InsnLb import *
+from InsnLh import *
+from InsnLw import *
+from InsnLbu import *
+from InsnLhu import *
+from InsnSb import *
+from InsnSh import *
+from InsnSw import *
+from InsnAddi import *
+from InsnSlti import *
+from InsnSltiu import *
+from InsnXori import *
+from InsnOri import *
+from InsnAndi import *
+from InsnSlli import *
+from InsnSrli import *
+from InsnSrai import *
+from InsnAdd import *
+from InsnSub import *
+from InsnSll import *
+from InsnSlt import *
+from InsnSltu import *
+from InsnXor import *
+from InsnSrl import *
+from InsnSra import *
+from InsnOr import *
+from InsnAnd import *
+
+"""
+RV32I Base ISA
+"""
+
+class IsaRV32I(Elaboratable):
+ def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM):
+ # Core-specific constants
+ self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+ self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
+ self.RISCV_FORMAL_CSR_MISA = RISCV_FORMAL_CSR_MISA
+ self.RISCV_FORMAL_COMPRESSED = RISCV_FORMAL_COMPRESSED
+ self.RISCV_FORMAL_ALIGNED_MEM = RISCV_FORMAL_ALIGNED_MEM
+
+ # Input ports
+ self.rvfi_valid = Signal(1)
+ self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
+ self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
+ self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
+ self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
+ self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
+ if self.RISCV_FORMAL_CSR_MISA:
+ self.rvfi_csr_misa_rdata = Signal(self.RISCV_FORMAL_XLEN)
+
+ # Output ports
+ if self.RISCV_FORMAL_CSR_MISA:
+ self.spec_csr_misa_rmask = Signal(self.RISCV_FORMAL_XLEN)
+ self.spec_valid = Signal(1)
+ self.spec_trap = Signal(1)
+ self.spec_rs1_addr = Signal(5)
+ self.spec_rs2_addr = Signal(5)
+ self.spec_rd_addr = Signal(5)
+ self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
+ self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
+ self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
+ self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
+ self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
+ self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
+ def ports(self):
+ input_ports = [
+ self.rvfi_valid,
+ self.rvfi_insn,
+ self.rvfi_pc_rdata,
+ self.rvfi_rs1_rdata,
+ self.rvfi_rs2_rdata,
+ self.rvfi_mem_rdata
+ ]
+ if self.RISCV_FORMAL_CSR_MISA:
+ input_ports.append(self.rvfi_csr_misa_rdata)
+ output_ports = [
+ self.spec_valid,
+ self.spec_trap,
+ self.spec_rs1_addr,
+ self.spec_rs2_addr,
+ self.spec_rd_addr,
+ self.spec_rd_wdata,
+ self.spec_pc_wdata,
+ self.spec_mem_addr,
+ self.spec_mem_rmask,
+ self.spec_mem_wmask,
+ self.spec_mem_wdata
+ ]
+ if self.RISCV_FORMAL_CSR_MISA:
+ output_ports.append(self.spec_csr_misa_rmask)
+ return input_ports + output_ports
+ def elaborate(self, platform):
+ m = Module()
+
+ insn_submodules = {}
+
+ m.submodules._lui = insn_submodules['lui'] = InsnLui(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
+ m.submodules._auipc = insn_submodules['auipc'] = InsnAuipc(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
+ m.submodules._jal = insn_submodules['jal'] = InsnJal(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
+ m.submodules._jalr = insn_submodules['jalr'] = InsnJalr(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
+ m.submodules._beq = insn_submodules['beq'] = InsnBeq(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
+ m.submodules._bne = insn_submodules['bne'] = InsnBne(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
+ m.submodules._blt = insn_submodules['blt'] = InsnBlt(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
+ m.submodules._bge = insn_submodules['bge'] = InsnBge(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
+ m.submodules._bltu = insn_submodules['bltu'] = InsnBltu(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
+ m.submodules._bgeu = insn_submodules['bgeu'] = InsnBgeu(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
+ m.submodules._lb = insn_submodules['lb'] = InsnLb(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
+ m.submodules._lh = insn_submodules['lh'] = InsnLh(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
+ m.submodules._lw = insn_submodules['lw'] = InsnLw(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
+ m.submodules._lbu = insn_submodules['lbu'] = InsnLbu(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
+ m.submodules._lhu = insn_submodules['lhu'] = InsnLhu(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
+ m.submodules._sb = insn_submodules['sb'] = InsnSb(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
+ m.submodules._sh = insn_submodules['Sh'] = InsnSh(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
+ m.submodules._sw = insn_submodules['sw'] = InsnSw(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
+ m.submodules._addi = insn_submodules['addi'] = InsnAddi(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
+ m.submodules._slti = insn_submodules['slti'] = InsnSlti(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
+ m.submodules._sltiu = insn_submodules['sltiu'] = InsnSltiu(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
+ m.submodules._xori = insn_submodules['xori'] = InsnXori(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
+ m.submodules._ori = insn_submodules['ori'] = InsnOri(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
+ m.submodules._andi = insn_submodules['andi'] = InsnAndi(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
+ m.submodules._slli = insn_submodules['slli'] = InsnSlli(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
+ m.submodules._srli = insn_submodules['srli'] = InsnSrli(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
+ m.submodules._srai = insn_submodules['srai'] = InsnSrai(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
+ m.submodules._add = insn_submodules['add'] = InsnAdd(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
+ m.submodules._sub = insn_submodules['sub'] = InsnSub(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
+ m.submodules._sll = insn_submodules['sll'] = InsnSll(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
+ m.submodules._slt = insn_submodules['slt'] = InsnSlt(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
+ m.submodules._sltu = insn_submodules['sltu'] = InsnSltu(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
+ m.submodules._xor = insn_submodules['xor'] = InsnXor(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
+ m.submodules._srl = insn_submodules['srl'] = InsnSrl(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
+ m.submodules._sra = insn_submodules['sra'] = InsnSra(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
+ m.submodules._or = insn_submodules['or'] = InsnOr(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
+ m.submodules._and = insn_submodules['and'] = InsnAnd(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
+
+ # TODO
+
+ return m