Update README

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Donald Sebastian Leung 2020-09-17 17:06:55 +08:00
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@ -29,20 +29,17 @@ $ python -m rvfi.cores.minerva.verify
This should run in the order of a few hours.
### Progress
- [x] Instruction Checks
- [x] PC forward checks
- [x] PC backward checks
- [x] Register checks
- [x] Causal checks
- [x] Liveness checks
- [x] Uniqueness checks
## Scope
The RV32I, RV32M, RV64I and RV64M ISAs are currently implemented but only RV32IM are being tested by integrating with the Minerva core.
## Possible improvements
In no particular order:
- Combine individual instruction checks into single ISA check (currently, doing so takes forever even when depth is set to only `20`)
- Parallelize execution of verification tasks to reduce the total time required to run all verification tasks on a multi-core system
## License
See [LICENSE](./LICENSE)