From 2790cb1f4cabec1d0c7ca4cf3d51d15a7d09a26a Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Thu, 27 Aug 2020 13:28:29 +0800 Subject: [PATCH] Add RV64I I-Type Instruction (Shift Variation) --- rvfi/insns/insn_rv64i_i_type_shift.py | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 rvfi/insns/insn_rv64i_i_type_shift.py diff --git a/rvfi/insns/insn_rv64i_i_type_shift.py b/rvfi/insns/insn_rv64i_i_type_shift.py new file mode 100644 index 0000000..f39a168 --- /dev/null +++ b/rvfi/insns/insn_rv64i_i_type_shift.py @@ -0,0 +1,20 @@ +from .insn_rv64i_i_type import * + +""" +RV64I I-Type Instruction (Shift Variation) +""" + +class InsnRV64IITypeShift(InsnRV64IIType): + def __init__(self, params, funct6, funct3): + super().__init__(params) + self.funct6 = funct6 + self.funct3 = funct3 + def elaborate(self, platform): + m = super().elaborate(platform) + + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct6 == self.funct6) & (self.insn_funct3 == self.funct3) & (self.insn_opcode == 0b0011011) & ~self.insn_shamt[5]) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + + return m