From 2055f5159b7966d9f3684ef75bd2df060f3a62b4 Mon Sep 17 00:00:00 2001
From: Donald Sebastian Leung <dl@m-labs.hk>
Date: Thu, 27 Aug 2020 15:48:11 +0800
Subject: [PATCH] Add ADDW instruction

---
 rvfi/insns/insn_addw.py | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
 create mode 100644 rvfi/insns/insn_addw.py

diff --git a/rvfi/insns/insn_addw.py b/rvfi/insns/insn_addw.py
new file mode 100644
index 0000000..115af96
--- /dev/null
+++ b/rvfi/insns/insn_addw.py
@@ -0,0 +1,17 @@
+from .insn_rv64i_r_type import *
+
+"""
+ADDW instruction
+"""
+
+class InsnAddw(InsnRV64IRType):
+    def __init__(self, params):
+        super().__init__(params, 0b0000000, 0b000)
+    def elaborate(self, platform):
+        m = super().elaborate(platform)
+
+        result = Signal(32)
+        m.d.comb += result.eq(self.rvfi_rs1_rdata[:32] + self.rvfi_rs2_rdata[:32])
+        m.d.comb += spec_rd_wdata.eq(Mux(self.spec_rd_addr, (Mux(result[31], 2 ** (self.params.xlen - 32) - 1, 0) << 32) | result, 0))
+
+        return m