From 0f71c1dad106802865bea370b8a0ec801f4f0693 Mon Sep 17 00:00:00 2001
From: Donald Sebastian Leung
Date: Tue, 11 Aug 2020 14:00:04 +0800
Subject: [PATCH] Add RV32I S-Type Instruction Format
---
insns/InsnRV32ISType.py | 46 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 46 insertions(+)
create mode 100644 insns/InsnRV32ISType.py
diff --git a/insns/InsnRV32ISType.py b/insns/InsnRV32ISType.py
new file mode 100644
index 0000000..089173f
--- /dev/null
+++ b/insns/InsnRV32ISType.py
@@ -0,0 +1,46 @@
+from Insn import *
+
+"""
+RV32I S-Type Instruction
+"""
+
+class InsnRV32ISType(Insn):
+ def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM, funct3, mask_shift):
+ super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED)
+ self.RISCV_FORMAL_ALIGNED_MEM = RISCV_FORMAL_ALIGNED_MEM
+ self.funct3 = funct3
+ self.mask_shift = mask_shift
+ self.addr = Signal(self.RISCV_FORMAL_XLEN)
+ def elaborate(self, platform):
+ m = super().elaborate(platform)
+
+ m.d.comb += self.insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[7:12], self.rvfi_insn[25:32])))
+
+ if self.RISCV_FORMAL_CSR_MISA:
+ m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0)
+ m.d.comb += self.spec_csr_misa_rmask.eq(0)
+ else:
+ m.d.comb += self.misa_ok.eq(1)
+
+ if self.RISCV_FORMAL_ALIGNED_MEM:
+ m.d.comb += self.addr.eq(self.rvfi_rs1_rdata + self.insn_imm)
+ m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == self.funct3) & (self.insn_opcode == 0b0100011))
+ m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
+ m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
+ m.d.comb += self.spec_mem_addr.eq(self.addr & ~(int(self.RISCV_FORMAL_XLEN // 8) - 1))
+ m.d.comb += self.spec_mem_wmask.eq(((1 << self.mask_shift) - 1) << (self.addr - self.spec_mem_addr))
+ m.d.comb += self.spec_mem_wdata.eq(self.rvfi_rs2_rdata << (8 * (self.addr - self.spec_mem_addr)))
+ m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
+ m.d.comb += self.spec_trap.eq(((self.addr & (self.mask_shift - 1)) != 0) | ~self.misa_ok)
+ else:
+ m.d.comb += self.addr.eq(self.rvfi_rs1_rdata + self.insn_imm)
+ m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == self.funct3) & (self.insn_opcode == 0b0100011))
+ m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
+ m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
+ m.d.comb += self.spec_mem_addr.eq(self.addr)
+ m.d.comb += self.spec_mem_wmask.eq((1 << self.mask_shift) - 1)
+ m.d.comb += self.spec_mem_wdata.eq(self.rvfi_rs2_rdata)
+ m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
+ m.d.comb += self.spec_trap.eq(~self.misa_ok)
+
+ return m