From 0af1f20423a6b2ef116856b573e0cc573fdce900 Mon Sep 17 00:00:00 2001
From: Donald Sebastian Leung <dl@m-labs.hk>
Date: Thu, 27 Aug 2020 11:46:04 +0800
Subject: [PATCH] Add RV64I I-Type Instruction

---
 rvfi/insns/insn_rv64i_i_type.py | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
 create mode 100644 rvfi/insns/insn_rv64i_i_type.py

diff --git a/rvfi/insns/insn_rv64i_i_type.py b/rvfi/insns/insn_rv64i_i_type.py
new file mode 100644
index 0000000..a590253
--- /dev/null
+++ b/rvfi/insns/insn_rv64i_i_type.py
@@ -0,0 +1,19 @@
+from .insn import *
+
+"""
+RV64I I-Type Instruction
+"""
+
+class InsnRV64IIType(Insn):
+    def elaborate(self, platform):
+        m = super().elaborate(platform)
+
+        m.d.comb += self.insn_imm.eq(Value.as_signed(sefl.rvfi_insn[20:32]))
+
+        if self.params.csr_misa:
+            m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0)
+            m.d.comb += self.spec_csr_misa_rmask.eq(0)
+        else:
+            m.d.comb += self.misa_ok.eq(1)
+
+        return m