From 036f842faaa484985f241b431632e113b3054759 Mon Sep 17 00:00:00 2001
From: Donald Sebastian Leung <dl@m-labs.hk>
Date: Mon, 10 Aug 2020 17:12:09 +0800
Subject: [PATCH] Add RV32I I-Type Instruction (Arithmetic Variation)

---
 insns/InsnRV32IITypeArith.py | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)
 create mode 100644 insns/InsnRV32IITypeArith.py

diff --git a/insns/InsnRV32IITypeArith.py b/insns/InsnRV32IITypeArith.py
new file mode 100644
index 0000000..2c78a4b
--- /dev/null
+++ b/insns/InsnRV32IITypeArith.py
@@ -0,0 +1,25 @@
+from InsnRV32IIType import *
+
+"""
+RV32I I-Type Instruction (Arithmetic Variation)
+"""
+
+class InsnRV32IITypeArith(InsnRV32IIType):
+    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, funct3):
+        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED)
+        self.funct3 = funct3
+    def elaborate(self, platform):
+        m = super().elaborate(platform)
+
+        if self.RISCV_FORMAL_CSR_MISA:
+            m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0)
+            m.d.comb += self.spec_csr_misa_rmask.eq(0)
+        else:
+            m.d.comb += self.misa_ok.eq(1)
+
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == self.funct3) & (self.insn_opcode == 0b0010011))
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
+        m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
+        m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
+
+        return m