From 0234b658902b8d231b2a2863e7be6da9cf2f0072 Mon Sep 17 00:00:00 2001
From: Donald Sebastian Leung
Date: Mon, 3 Aug 2020 14:51:36 +0800
Subject: [PATCH] Add SLLI instruction
---
insns/insn_slli.py | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
create mode 100644 insns/insn_slli.py
diff --git a/insns/insn_slli.py b/insns/insn_slli.py
new file mode 100644
index 0000000..6d18539
--- /dev/null
+++ b/insns/insn_slli.py
@@ -0,0 +1,20 @@
+from insn_I_shift import *
+
+class rvfi_insn_slli(rvfi_insn_I_shift):
+ def __init__(self):
+ super(rvfi_insn_slli, self).__init__()
+ def ports(self):
+ return super(rvfi_insn_slli, self).ports()
+ def elaborate(self, platform):
+ m = super(rvfi_insn_slli, self).elaborate(platform)
+
+ # SLLI instruction
+ result = Signal(32)
+ m.d.comb += result.eq(self.rvfi_rs1_rdata << self.insn_shamt)
+ m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct6 == 0b000000) & (self.insn_funct3 == 0b001) & (self.insn_opcode == 0b0010011) & (~self.insn_shamt[5]))
+ m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
+ m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
+ m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
+ m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
+
+ return m