2020-08-17 11:50:53 +08:00
|
|
|
from .insn_rv32i_i_type_shift import *
|
2020-08-10 12:29:52 +08:00
|
|
|
|
2020-08-10 12:31:20 +08:00
|
|
|
"""
|
|
|
|
|
SLLI instruction
|
|
|
|
|
"""
|
|
|
|
|
|
2020-08-10 12:29:52 +08:00
|
|
|
class InsnSlli(InsnRV32IITypeShift):
|
2020-08-12 13:36:50 +08:00
|
|
|
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
|
|
|
|
|
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b000000, 0b001)
|
2020-08-10 12:29:52 +08:00
|
|
|
def elaborate(self, platform):
|
|
|
|
|
m = super().elaborate(platform)
|
|
|
|
|
|
|
|
|
|
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata << self.insn_shamt, 0))
|
|
|
|
|
|
|
|
|
|
return m
|
