623 lines
16 KiB
Python
623 lines
16 KiB
Python
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# nmigen: UnusedElaboratable=no
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from ..hdl.ast import *
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from ..hdl.cd import *
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from ..hdl.ir import *
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from ..hdl.xfrm import *
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from ..hdl.mem import *
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from .utils import *
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class DomainRenamerTestCase(FHDLTestCase):
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def setUp(self):
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self.s1 = Signal()
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self.s2 = Signal()
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self.s3 = Signal()
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self.s4 = Signal()
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self.s5 = Signal()
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self.c1 = Signal()
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def test_rename_signals(self):
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f = Fragment()
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f.add_statements(
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self.s1.eq(ClockSignal()),
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ResetSignal().eq(self.s2),
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self.s3.eq(0),
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self.s4.eq(ClockSignal("other")),
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self.s5.eq(ResetSignal("other")),
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)
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f.add_driver(self.s1, None)
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f.add_driver(self.s2, None)
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f.add_driver(self.s3, "sync")
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f = DomainRenamer("pix")(f)
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self.assertRepr(f.statements, """
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(
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(eq (sig s1) (clk pix))
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(eq (rst pix) (sig s2))
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(eq (sig s3) (const 1'd0))
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(eq (sig s4) (clk other))
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(eq (sig s5) (rst other))
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)
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""")
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self.assertEqual(f.drivers, {
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None: SignalSet((self.s1, self.s2)),
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"pix": SignalSet((self.s3,)),
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})
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def test_rename_multi(self):
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f = Fragment()
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f.add_statements(
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self.s1.eq(ClockSignal()),
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self.s2.eq(ResetSignal("other")),
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)
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f = DomainRenamer({"sync": "pix", "other": "pix2"})(f)
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self.assertRepr(f.statements, """
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(
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(eq (sig s1) (clk pix))
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(eq (sig s2) (rst pix2))
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)
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""")
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def test_rename_cd(self):
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cd_sync = ClockDomain()
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cd_pix = ClockDomain()
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f = Fragment()
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f.add_domains(cd_sync, cd_pix)
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f = DomainRenamer("ext")(f)
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self.assertEqual(cd_sync.name, "ext")
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self.assertEqual(f.domains, {
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"ext": cd_sync,
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"pix": cd_pix,
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})
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def test_rename_cd_subfragment(self):
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cd_sync = ClockDomain()
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cd_pix = ClockDomain()
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f1 = Fragment()
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f1.add_domains(cd_sync, cd_pix)
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f2 = Fragment()
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f2.add_domains(cd_sync)
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f1.add_subfragment(f2)
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f1 = DomainRenamer("ext")(f1)
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self.assertEqual(cd_sync.name, "ext")
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self.assertEqual(f1.domains, {
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"ext": cd_sync,
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"pix": cd_pix,
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})
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def test_rename_wrong_to_comb(self):
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with self.assertRaises(ValueError,
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msg="Domain 'sync' may not be renamed to 'comb'"):
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DomainRenamer("comb")
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def test_rename_wrong_from_comb(self):
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with self.assertRaises(ValueError,
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msg="Domain 'comb' may not be renamed"):
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DomainRenamer({"comb": "sync"})
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class DomainLowererTestCase(FHDLTestCase):
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def setUp(self):
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self.s = Signal()
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def test_lower_clk(self):
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sync = ClockDomain()
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f = Fragment()
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f.add_domains(sync)
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f.add_statements(
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self.s.eq(ClockSignal("sync"))
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)
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f = DomainLowerer()(f)
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self.assertRepr(f.statements, """
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(
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(eq (sig s) (sig clk))
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)
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""")
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def test_lower_rst(self):
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sync = ClockDomain()
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f = Fragment()
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f.add_domains(sync)
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f.add_statements(
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self.s.eq(ResetSignal("sync"))
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)
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f = DomainLowerer()(f)
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self.assertRepr(f.statements, """
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(
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(eq (sig s) (sig rst))
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)
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""")
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def test_lower_rst_reset_less(self):
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sync = ClockDomain(reset_less=True)
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f = Fragment()
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f.add_domains(sync)
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f.add_statements(
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self.s.eq(ResetSignal("sync", allow_reset_less=True))
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)
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f = DomainLowerer()(f)
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self.assertRepr(f.statements, """
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(
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(eq (sig s) (const 1'd0))
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)
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""")
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def test_lower_drivers(self):
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sync = ClockDomain()
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pix = ClockDomain()
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f = Fragment()
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f.add_domains(sync, pix)
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f.add_driver(ClockSignal("pix"), None)
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f.add_driver(ResetSignal("pix"), "sync")
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f = DomainLowerer()(f)
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self.assertEqual(f.drivers, {
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None: SignalSet((pix.clk,)),
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"sync": SignalSet((pix.rst,))
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})
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def test_lower_wrong_domain(self):
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f = Fragment()
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f.add_statements(
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self.s.eq(ClockSignal("xxx"))
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)
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with self.assertRaises(DomainError,
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msg="Signal (clk xxx) refers to nonexistent domain 'xxx'"):
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DomainLowerer()(f)
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def test_lower_wrong_reset_less_domain(self):
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sync = ClockDomain(reset_less=True)
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f = Fragment()
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f.add_domains(sync)
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f.add_statements(
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self.s.eq(ResetSignal("sync"))
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)
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with self.assertRaises(DomainError,
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msg="Signal (rst sync) refers to reset of reset-less domain 'sync'"):
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DomainLowerer()(f)
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class SampleLowererTestCase(FHDLTestCase):
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def setUp(self):
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self.i = Signal()
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self.o1 = Signal()
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self.o2 = Signal()
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self.o3 = Signal()
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def test_lower_signal(self):
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f = Fragment()
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f.add_statements(
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self.o1.eq(Sample(self.i, 2, "sync")),
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self.o2.eq(Sample(self.i, 1, "sync")),
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self.o3.eq(Sample(self.i, 1, "pix")),
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)
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f = SampleLowerer()(f)
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self.assertRepr(f.statements, """
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(
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(eq (sig o1) (sig $sample$s$i$sync$2))
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(eq (sig o2) (sig $sample$s$i$sync$1))
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(eq (sig o3) (sig $sample$s$i$pix$1))
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(eq (sig $sample$s$i$sync$1) (sig i))
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(eq (sig $sample$s$i$sync$2) (sig $sample$s$i$sync$1))
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(eq (sig $sample$s$i$pix$1) (sig i))
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)
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""")
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self.assertEqual(len(f.drivers["sync"]), 2)
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self.assertEqual(len(f.drivers["pix"]), 1)
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def test_lower_const(self):
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f = Fragment()
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f.add_statements(
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self.o1.eq(Sample(1, 2, "sync")),
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)
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f = SampleLowerer()(f)
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self.assertRepr(f.statements, """
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(
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(eq (sig o1) (sig $sample$c$1$sync$2))
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(eq (sig $sample$c$1$sync$1) (const 1'd1))
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(eq (sig $sample$c$1$sync$2) (sig $sample$c$1$sync$1))
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)
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""")
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self.assertEqual(len(f.drivers["sync"]), 2)
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class SwitchCleanerTestCase(FHDLTestCase):
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def test_clean(self):
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a = Signal()
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b = Signal()
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c = Signal()
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stmts = [
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Switch(a, {
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1: a.eq(0),
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0: [
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b.eq(1),
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Switch(b, {1: [
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Switch(a|b, {})
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]})
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]
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})
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]
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self.assertRepr(SwitchCleaner()(stmts), """
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(
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(switch (sig a)
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(case 1
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(eq (sig a) (const 1'd0)))
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(case 0
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(eq (sig b) (const 1'd1)))
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)
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)
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""")
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class LHSGroupAnalyzerTestCase(FHDLTestCase):
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def test_no_group_unrelated(self):
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a = Signal()
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b = Signal()
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stmts = [
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a.eq(0),
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b.eq(0),
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]
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groups = LHSGroupAnalyzer()(stmts)
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self.assertEqual(list(groups.values()), [
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SignalSet((a,)),
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SignalSet((b,)),
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])
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def test_group_related(self):
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a = Signal()
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b = Signal()
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stmts = [
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a.eq(0),
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Cat(a, b).eq(0),
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]
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groups = LHSGroupAnalyzer()(stmts)
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self.assertEqual(list(groups.values()), [
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SignalSet((a, b)),
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])
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def test_no_loops(self):
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a = Signal()
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b = Signal()
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stmts = [
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a.eq(0),
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Cat(a, b).eq(0),
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Cat(a, b).eq(0),
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]
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groups = LHSGroupAnalyzer()(stmts)
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self.assertEqual(list(groups.values()), [
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SignalSet((a, b)),
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])
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def test_switch(self):
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a = Signal()
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b = Signal()
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stmts = [
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a.eq(0),
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Switch(a, {
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1: b.eq(0),
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})
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]
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groups = LHSGroupAnalyzer()(stmts)
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self.assertEqual(list(groups.values()), [
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SignalSet((a,)),
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SignalSet((b,)),
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])
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def test_lhs_empty(self):
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stmts = [
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Cat().eq(0)
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]
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groups = LHSGroupAnalyzer()(stmts)
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self.assertEqual(list(groups.values()), [
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])
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class LHSGroupFilterTestCase(FHDLTestCase):
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def test_filter(self):
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a = Signal()
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b = Signal()
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c = Signal()
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stmts = [
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Switch(a, {
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1: a.eq(0),
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0: [
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b.eq(1),
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Switch(b, {1: []})
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]
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})
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]
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self.assertRepr(LHSGroupFilter(SignalSet((a,)))(stmts), """
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(
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(switch (sig a)
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(case 1
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(eq (sig a) (const 1'd0)))
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(case 0 )
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)
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)
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""")
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def test_lhs_empty(self):
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stmts = [
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Cat().eq(0)
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]
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self.assertRepr(LHSGroupFilter(SignalSet())(stmts), "()")
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class ResetInserterTestCase(FHDLTestCase):
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def setUp(self):
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self.s1 = Signal()
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self.s2 = Signal(reset=1)
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self.s3 = Signal(reset=1, reset_less=True)
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self.c1 = Signal()
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def test_reset_default(self):
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f = Fragment()
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f.add_statements(
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self.s1.eq(1)
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)
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f.add_driver(self.s1, "sync")
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f = ResetInserter(self.c1)(f)
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self.assertRepr(f.statements, """
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|
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(
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(eq (sig s1) (const 1'd1))
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|
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(switch (sig c1)
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||
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(case 1 (eq (sig s1) (const 1'd0)))
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||
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)
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)
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""")
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def test_reset_cd(self):
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f = Fragment()
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f.add_statements(
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self.s1.eq(1),
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|
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self.s2.eq(0),
|
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)
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f.add_domains(ClockDomain("sync"))
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||
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f.add_driver(self.s1, "sync")
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f.add_driver(self.s2, "pix")
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|
|
f = ResetInserter({"pix": self.c1})(f)
|
||
|
|
self.assertRepr(f.statements, """
|
||
|
|
(
|
||
|
|
(eq (sig s1) (const 1'd1))
|
||
|
|
(eq (sig s2) (const 1'd0))
|
||
|
|
(switch (sig c1)
|
||
|
|
(case 1 (eq (sig s2) (const 1'd1)))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
""")
|
||
|
|
|
||
|
|
def test_reset_value(self):
|
||
|
|
f = Fragment()
|
||
|
|
f.add_statements(
|
||
|
|
self.s2.eq(0)
|
||
|
|
)
|
||
|
|
f.add_driver(self.s2, "sync")
|
||
|
|
|
||
|
|
f = ResetInserter(self.c1)(f)
|
||
|
|
self.assertRepr(f.statements, """
|
||
|
|
(
|
||
|
|
(eq (sig s2) (const 1'd0))
|
||
|
|
(switch (sig c1)
|
||
|
|
(case 1 (eq (sig s2) (const 1'd1)))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
""")
|
||
|
|
|
||
|
|
def test_reset_less(self):
|
||
|
|
f = Fragment()
|
||
|
|
f.add_statements(
|
||
|
|
self.s3.eq(0)
|
||
|
|
)
|
||
|
|
f.add_driver(self.s3, "sync")
|
||
|
|
|
||
|
|
f = ResetInserter(self.c1)(f)
|
||
|
|
self.assertRepr(f.statements, """
|
||
|
|
(
|
||
|
|
(eq (sig s3) (const 1'd0))
|
||
|
|
(switch (sig c1)
|
||
|
|
(case 1 )
|
||
|
|
)
|
||
|
|
)
|
||
|
|
""")
|
||
|
|
|
||
|
|
|
||
|
|
class EnableInserterTestCase(FHDLTestCase):
|
||
|
|
def setUp(self):
|
||
|
|
self.s1 = Signal()
|
||
|
|
self.s2 = Signal()
|
||
|
|
self.s3 = Signal()
|
||
|
|
self.c1 = Signal()
|
||
|
|
|
||
|
|
def test_enable_default(self):
|
||
|
|
f = Fragment()
|
||
|
|
f.add_statements(
|
||
|
|
self.s1.eq(1)
|
||
|
|
)
|
||
|
|
f.add_driver(self.s1, "sync")
|
||
|
|
|
||
|
|
f = EnableInserter(self.c1)(f)
|
||
|
|
self.assertRepr(f.statements, """
|
||
|
|
(
|
||
|
|
(eq (sig s1) (const 1'd1))
|
||
|
|
(switch (sig c1)
|
||
|
|
(case 0 (eq (sig s1) (sig s1)))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
""")
|
||
|
|
|
||
|
|
def test_enable_cd(self):
|
||
|
|
f = Fragment()
|
||
|
|
f.add_statements(
|
||
|
|
self.s1.eq(1),
|
||
|
|
self.s2.eq(0),
|
||
|
|
)
|
||
|
|
f.add_driver(self.s1, "sync")
|
||
|
|
f.add_driver(self.s2, "pix")
|
||
|
|
|
||
|
|
f = EnableInserter({"pix": self.c1})(f)
|
||
|
|
self.assertRepr(f.statements, """
|
||
|
|
(
|
||
|
|
(eq (sig s1) (const 1'd1))
|
||
|
|
(eq (sig s2) (const 1'd0))
|
||
|
|
(switch (sig c1)
|
||
|
|
(case 0 (eq (sig s2) (sig s2)))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
""")
|
||
|
|
|
||
|
|
def test_enable_subfragment(self):
|
||
|
|
f1 = Fragment()
|
||
|
|
f1.add_statements(
|
||
|
|
self.s1.eq(1)
|
||
|
|
)
|
||
|
|
f1.add_driver(self.s1, "sync")
|
||
|
|
|
||
|
|
f2 = Fragment()
|
||
|
|
f2.add_statements(
|
||
|
|
self.s2.eq(1)
|
||
|
|
)
|
||
|
|
f2.add_driver(self.s2, "sync")
|
||
|
|
f1.add_subfragment(f2)
|
||
|
|
|
||
|
|
f1 = EnableInserter(self.c1)(f1)
|
||
|
|
(f2, _), = f1.subfragments
|
||
|
|
self.assertRepr(f1.statements, """
|
||
|
|
(
|
||
|
|
(eq (sig s1) (const 1'd1))
|
||
|
|
(switch (sig c1)
|
||
|
|
(case 0 (eq (sig s1) (sig s1)))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
""")
|
||
|
|
self.assertRepr(f2.statements, """
|
||
|
|
(
|
||
|
|
(eq (sig s2) (const 1'd1))
|
||
|
|
(switch (sig c1)
|
||
|
|
(case 0 (eq (sig s2) (sig s2)))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
""")
|
||
|
|
|
||
|
|
def test_enable_read_port(self):
|
||
|
|
mem = Memory(width=8, depth=4)
|
||
|
|
f = EnableInserter(self.c1)(mem.read_port(transparent=False)).elaborate(platform=None)
|
||
|
|
self.assertRepr(f.named_ports["EN"][0], """
|
||
|
|
(m (sig c1) (sig mem_r_en) (const 1'd0))
|
||
|
|
""")
|
||
|
|
|
||
|
|
def test_enable_write_port(self):
|
||
|
|
mem = Memory(width=8, depth=4)
|
||
|
|
f = EnableInserter(self.c1)(mem.write_port()).elaborate(platform=None)
|
||
|
|
self.assertRepr(f.named_ports["EN"][0], """
|
||
|
|
(m (sig c1) (cat (repl (slice (sig mem_w_en) 0:1) 8)) (const 8'd0))
|
||
|
|
""")
|
||
|
|
|
||
|
|
|
||
|
|
class _MockElaboratable(Elaboratable):
|
||
|
|
def __init__(self):
|
||
|
|
self.s1 = Signal()
|
||
|
|
|
||
|
|
def elaborate(self, platform):
|
||
|
|
f = Fragment()
|
||
|
|
f.add_statements(
|
||
|
|
self.s1.eq(1)
|
||
|
|
)
|
||
|
|
f.add_driver(self.s1, "sync")
|
||
|
|
return f
|
||
|
|
|
||
|
|
|
||
|
|
class TransformedElaboratableTestCase(FHDLTestCase):
|
||
|
|
def setUp(self):
|
||
|
|
self.c1 = Signal()
|
||
|
|
self.c2 = Signal()
|
||
|
|
|
||
|
|
def test_getattr(self):
|
||
|
|
e = _MockElaboratable()
|
||
|
|
te = EnableInserter(self.c1)(e)
|
||
|
|
|
||
|
|
self.assertIs(te.s1, e.s1)
|
||
|
|
|
||
|
|
def test_composition(self):
|
||
|
|
e = _MockElaboratable()
|
||
|
|
te1 = EnableInserter(self.c1)(e)
|
||
|
|
te2 = ResetInserter(self.c2)(te1)
|
||
|
|
|
||
|
|
self.assertIsInstance(te1, TransformedElaboratable)
|
||
|
|
self.assertIs(te1, te2)
|
||
|
|
|
||
|
|
f = Fragment.get(te2, None)
|
||
|
|
self.assertRepr(f.statements, """
|
||
|
|
(
|
||
|
|
(eq (sig s1) (const 1'd1))
|
||
|
|
(switch (sig c1)
|
||
|
|
(case 0 (eq (sig s1) (sig s1)))
|
||
|
|
)
|
||
|
|
(switch (sig c2)
|
||
|
|
(case 1 (eq (sig s1) (const 1'd0)))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
""")
|
||
|
|
|
||
|
|
|
||
|
|
class MockUserValue(UserValue):
|
||
|
|
def __init__(self, lowered):
|
||
|
|
super().__init__()
|
||
|
|
self.lowered = lowered
|
||
|
|
|
||
|
|
def lower(self):
|
||
|
|
return self.lowered
|
||
|
|
|
||
|
|
|
||
|
|
class UserValueTestCase(FHDLTestCase):
|
||
|
|
def setUp(self):
|
||
|
|
self.s = Signal()
|
||
|
|
self.c = Signal()
|
||
|
|
self.uv = MockUserValue(self.s)
|
||
|
|
|
||
|
|
def test_lower(self):
|
||
|
|
sync = ClockDomain()
|
||
|
|
f = Fragment()
|
||
|
|
f.add_domains(sync)
|
||
|
|
f.add_statements(
|
||
|
|
self.uv.eq(1)
|
||
|
|
)
|
||
|
|
for signal in self.uv._lhs_signals():
|
||
|
|
f.add_driver(signal, "sync")
|
||
|
|
|
||
|
|
f = ResetInserter(self.c)(f)
|
||
|
|
f = DomainLowerer()(f)
|
||
|
|
self.assertRepr(f.statements, """
|
||
|
|
(
|
||
|
|
(eq (sig s) (const 1'd1))
|
||
|
|
(switch (sig c)
|
||
|
|
(case 1 (eq (sig s) (const 1'd0)))
|
||
|
|
)
|
||
|
|
(switch (sig rst)
|
||
|
|
(case 1 (eq (sig s) (const 1'd0)))
|
||
|
|
)
|
||
|
|
)
|
||
|
|
""")
|