2020-08-07 15:51:21 +08:00
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from InsnRV32IRType import *
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2020-08-07 16:06:15 +08:00
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"""
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SRA instruction
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"""
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2020-08-07 15:51:21 +08:00
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class InsnSra(InsnRV32IRType):
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def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED):
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2020-08-10 11:15:05 +08:00
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super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0100000, 0b101, 0b0110011)
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2020-08-07 15:51:21 +08:00
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def elaborate(self, platform):
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2020-08-10 11:15:05 +08:00
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m = super().elaborate(platform)
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2020-08-07 15:51:21 +08:00
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m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, (Value.as_signed(self.rvfi_rs1_rdata) >> Mux(self.RISCV_FORMAL_XLEN == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5])) | (-(Value.as_signed(self.rvfi_rs1_rdata) < 0) << (self.RISCV_FORMAL_XLEN - Mux(self.RISCV_FORMAL_XLEN == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5]))), 0))
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return m
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