linuswck
bd27e93a73
- Revert commit 25dd0db. Related Issue: #40. - Fail to meet timing for IIR Filter's Multiply and Add operation as multiplication operation cannot be fitted inside a single DSP Slice (25b x 18b). Thus, multiple DSPs are needed for multiplication. This causes timing violation at 100MHz and 125MHz sys frequency.
23 lines
819 B
Diff
23 lines
819 B
Diff
diff --git a/gateware/linien_module.py b/gateware/linien_module.py
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index a64714c..1d905de 100644
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--- a/gateware/linien_module.py
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+++ b/gateware/linien_module.py
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@@ -47,7 +47,7 @@ from .lowlevel.scopegen import ScopeGen
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class LinienLogic(Module, AutoCSR):
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- def __init__(self, width=14, signal_width=25, chain_factor_width=8, coeff_width=25):
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+ def __init__(self, width=14, signal_width=25, chain_factor_width=8, coeff_width=18):
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self.init_csr(width, chain_factor_width)
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self.init_submodules(width, signal_width)
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self.connect_pid()
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@@ -154,7 +154,7 @@ class LinienModule(Module, AutoCSR):
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def __init__(self, soc):
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width = 14
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signal_width = 25
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- coeff_width = 25
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+ coeff_width = 18
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chain_factor_bits = 8
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self.init_submodules(
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