95 lines
3.6 KiB
Python
95 lines
3.6 KiB
Python
# This file is part of Fast Servo Software Package.
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#
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# Copyright (C) 2023 Jakub Matyas
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# Warsaw University of Technology <jakubk.m@gmail.com>
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# SPDX-License-Identifier: GPL-3.0-or-later
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#
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# This program is free software: you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation, either version 3 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program. If not, see <https://www.gnu.org/licenses/>.
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from migen import *
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from misoc.interconnect.csr import AutoCSR, CSRStorage
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from migen.genlib.io import DDROutput
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from misoc.interconnect.stream import AsyncFIFO
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class DAC(Module, AutoCSR):
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def __init__(self, platform):
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dac_pads = platform.request("dac")
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dac_afe_pads = platform.request("dac_afe")
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self.dac_ctrl = CSRStorage(3)
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self.output_value_ch0 = CSRStorage(14)
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self.output_value_ch1 = CSRStorage(14)
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manual_override = Signal()
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ch0_pd = Signal()
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ch1_pd = Signal()
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output_data_ch0 = Signal(14)
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output_data_ch1 = Signal(14)
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self.data_in = [Signal(14, reset_less=True), Signal(14, reset_less=True)]
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self.data_in_cdc = [Signal(14, reset_less=True), Signal(14, reset_less=True)]
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platform.add_period_constraint(dac_pads.dclkio, 10.0)
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self.submodules.cdc_fifo = ClockDomainsRenamer({"write": "sys", "read": "dco2d"})(AsyncFIFO([("data", 28)], 2))
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self.comb += [
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self.cdc_fifo.sink.data.eq(Cat(self.data_in[0], self.data_in[1])),
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self.cdc_fifo.sink.stb.eq(~ResetSignal("sys")),
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Cat(self.data_in_cdc[0], self.data_in_cdc[1]).eq(self.cdc_fifo.source.data),
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self.cdc_fifo.source.ack.eq(~ResetSignal("dco2d")),
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]
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self.comb += [
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Cat(manual_override, ch0_pd, ch1_pd).eq(self.dac_ctrl.storage),
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dac_pads.rst.eq(ResetSignal("dco2d")),
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dac_afe_pads.ch1_pd_n.eq(~ch0_pd),
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dac_afe_pads.ch2_pd_n.eq(~ch1_pd),
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output_data_ch0.eq(
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Mux(manual_override, self.output_value_ch0.storage, self.data_in_cdc[0])
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),
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output_data_ch1.eq(
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Mux(manual_override, self.output_value_ch1.storage, self.data_in_cdc[1])
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),
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]
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self.specials += [
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Instance("ODDR",
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i_C=ClockSignal("dco2d"),
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i_CE=~ResetSignal("dco2d"),
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i_D1=output_data_ch0[lane], # DDR CLK Rising Edge
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i_D2=output_data_ch1[lane], # DDR CLK Falling Edge
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o_Q=dac_pads.data[lane],
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p_DDR_CLK_EDGE="SAME_EDGE")
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for lane in range(14)]
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self.specials += Instance("ODDR",
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i_C=ClockSignal("dco2d_45_degree"),
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i_CE=~ResetSignal("dco2d"),
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i_D1=0,
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i_D2=1,
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o_Q=dac_pads.dclkio,
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p_DDR_CLK_EDGE="SAME_EDGE")
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class AUX_DAC_CTRL(Module, AutoCSR):
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def __init__(self, platform):
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dac_aux_pads = platform.request("aux_dac")
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self.dac_aux_ctrl = CSRStorage(3)
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self.comb += [
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dac_aux_pads.nclr.eq(~self.dac_aux_ctrl.storage[0]),
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dac_aux_pads.bin.eq(self.dac_aux_ctrl.storage[1]),
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dac_aux_pads.nldac.eq(~self.dac_aux_ctrl.storage[2]),
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]
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