111 lines
2.6 KiB
Verilog
111 lines
2.6 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company: WUT
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// Engineer: Jakub Matyas
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//
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// Create Date: 03/02/2023 01:39:08 PM
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// Design Name:
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// Module Name: spi2threewire
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module spi2threewire (
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output ps_sclk_i,
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input ps_sclk_o,
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input ps_sclk_t,
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output ps_mosi_i,
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input ps_mosi_o,
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input ps_mosi_t,
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output ps_miso_i,
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input ps_miso_o,
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input ps_miso_t,
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output ps_ss_i,
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input [2:0] ps_ss,
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input ps_ss_t,
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output o_ss,
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output o_sclk,
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inout sdio
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);
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assign ps_sclk_i = 1'b0;
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assign ps_mosi_i = 1'b0;
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assign ps_ss_i = 1'b1;
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reg [3:0] bit_count = 'd0;
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// rd_wr_n - whether it will be READ transaction or WRITE
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// first bit of the command
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reg rd_wr_n = 'd0;
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reg sdio_buffer_direction = 'd0;
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wire s_sclk;
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wire s_csn;
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wire s_sdio_buffer_direction;
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assign s_sclk = ps_sclk_o;
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assign s_csn = ps_ss[0];
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assign o_ss = s_csn;
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// 1 if there is a SPI tranmsission going on (CS_N is LOW)
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// AND transmission is of READ type
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// 0 otherwise
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assign s_sdio_buffer_direction = sdio_buffer_direction & ~s_csn;
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always @(posedge s_sclk or posedge s_csn) begin
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if (s_csn == 1'b1) begin
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// after the transmission, fill bit counter with ZEROS
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// and zero transmission type (rd_wr_n)
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bit_count <= 4'd0;
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rd_wr_n <= 1'b0;
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end else begin
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// on every rising edge increment bit counter
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// sample first bit to get the knowledge of the transmission type
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bit_count <= (bit_count < 4'd15) ? bit_count + 1'b1 : bit_count;
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if (bit_count == 4'b0)
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rd_wr_n <= ps_mosi_o;
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end
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end
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always @(negedge s_sclk or posedge s_csn) begin
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if (s_csn == 1'b1)
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sdio_buffer_direction <= 1'b0;
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else begin
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if (bit_count == 4'd8)
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// after the 8th bit, on falling edge,
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// set the SDIO buffer direction
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// accordingly to the transmission type
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sdio_buffer_direction <= rd_wr_n;
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end
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end
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IOBUF IOBUF_inst (
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.O(ps_miso_i),
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.IO(sdio),
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.I(ps_mosi_o),
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.T(s_sdio_buffer_direction) // 3-state enable input, high=input (from ext), low=output
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);
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OBUFT sclk_buf (
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.O(o_sclk),
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.I(ps_sclk_o),
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.T('b0)
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);
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endmodule |