/*
 * CAUTION: This file is automatically generated by Xilinx.
 * Version: XSCT 2022.2
 * Today is: Fri Jan 26 10:52:46 2024
 */


/ {
	cpus {
		cpu@0 {
			operating-points = <500000 1000000 250000 1000000>;
		};
	};
};
&gem0 {
	enet-reset = <&gpio0 50 0>;
	phy-mode = "rgmii-id";
	status = "okay";
	xlnx,ptp-enet-clock = <0x4f790d8>;
};
&gpio0 {
	emio-gpio-width = <64>;
	gpio-mask-high = <0x0>;
	gpio-mask-low = <0x5600>;
};
&i2c0 {
	clock-frequency = <400000>;
	status = "okay";
};
&i2c1 {
	clock-frequency = <400000>;
	status = "okay";
};
&intc {
	num_cpus = <2>;
	num_interrupts = <96>;
};
&qspi {
	is-dual = <0>;
	num-cs = <1>;
	spi-rx-bus-width = <4>;
	spi-tx-bus-width = <4>;
	status = "okay";
};
&sdhci0 {
	status = "okay";
	xlnx,has-cd = <0x0>;
	xlnx,has-power = <0x0>;
	xlnx,has-wp = <0x0>;
};
&spi0 {
	is-decoded-cs = <0>;
	num-cs = <3>;
	status = "okay";
};
&spi1 {
	is-decoded-cs = <0>;
	num-cs = <3>;
	status = "okay";
};
&uart0 {
	cts-override ;
	device_type = "serial";
	port-number = <0>;
	status = "okay";
};
&usb0 {
	phy_type = "ulpi";
	status = "okay";
	usb-reset = <&gpio0 51 0>;
};
&clkc {
	fclk-enable = <0x0>;
	ps-clk-frequency = <33333333>;
};