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linien-ser
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@ -20,15 +20,13 @@
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from migen import *
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from migen.genlib.cdc import MultiReg
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from misoc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage
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from misoc.interconnect.stream import AsyncFIFO
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class CRG(Module):
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class _CRG(Module):
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def __init__(self, platform, dco_clk, dco_freq=200e6):
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self.clock_domains.cd_dco = ClockDomain()
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self.clock_domains.cd_dco2x = ClockDomain()
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self.clock_domains.cd_dco2d = ClockDomain()
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self.clock_domains.cd_dco2d_45_degree = ClockDomain()
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dco_clk_p, dco_clk_n = dco_clk
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dco_clk_buf = Signal()
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@ -43,83 +41,59 @@ class CRG(Module):
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clk_dco = Signal()
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clk_dco2x = Signal()
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clk_dco2d = Signal()
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clk_dco2d_45_degree = Signal()
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mmcm_ps_psdone = Signal()
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self.locked = Signal()
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self.mmcm_rst = Signal()
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self.ddr_clk_phase_shift_en = Signal()
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self.ddr_clk_phase_incdec = Signal()
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platform.add_period_constraint(dco_clk_p, 1e9 / dco_freq)
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self.specials += [
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Instance(
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"MMCME2_ADV",
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"PLLE2_BASE",
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p_BANDWIDTH="OPTIMIZED",
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p_DIVCLK_DIVIDE=1,
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p_CLKFBOUT_PHASE=0.0,
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p_CLKFBOUT_MULT_F=4, # VCO @ 800 MHz
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p_CLKFBOUT_MULT=4, # VCO @ 800 MHz
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p_CLKIN1_PERIOD=(1e9 / dco_freq),
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p_REF_JITTER1=0.01,
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p_STARTUP_WAIT="FALSE",
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i_CLKIN1=dco_clk_buf,
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i_PWRDWN=0,
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i_RST=ResetSignal("sys") | self.mmcm_rst,
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i_RST=ResetSignal("sys"),
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i_CLKFBIN=clk_feedback_buf,
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o_CLKFBOUT=clk_feedback,
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p_CLKOUT0_USE_FINE_PS="TRUE",
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p_CLKOUT0_DIVIDE_F=8,
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p_CLKOUT0_PHASE=45.0,
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p_CLKOUT0_DIVIDE=4,
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p_CLKOUT0_PHASE=0.0,
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p_CLKOUT0_DUTY_CYCLE=0.5,
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o_CLKOUT0=clk_dco2d_45_degree, # 100 MHz <- dco_clk / 2 = 200 MHz / 2
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o_LOCKED=self.locked,
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o_CLKOUT0=clk_dco, # 200 MHz <- dco_clk
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p_CLKOUT1_DIVIDE=2,
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p_CLKOUT1_PHASE=0.0,
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p_CLKOUT1_DUTY_CYCLE=0.5,
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o_CLKOUT1=clk_dco2x, # 400 MHZ <- 2 * dco_clk = 2*200 MHz
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p_CLKOUT2_DIVIDE=8,
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p_CLKOUT2_PHASE=0.0,
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p_CLKOUT2_DUTY_CYCLE=0.5,
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o_CLKOUT2=clk_dco2d, # 100 MHz <- dco_clk / 2 = 200 MHz / 2
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p_CLKOUT3_DIVIDE=4,
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p_CLKOUT3_PHASE=0.0,
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p_CLKOUT3_DUTY_CYCLE=0.5,
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o_CLKOUT3=clk_dco, # 200 MHz <- dco_clk
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i_PSCLK=ClockSignal(),
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i_PSEN=self.ddr_clk_phase_shift_en,
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i_PSINCDEC=self.ddr_clk_phase_incdec,
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o_PSDONE=mmcm_ps_psdone,
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o_LOCKED=self.locked,
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)
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]
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self.specials += Instance("BUFG", i_I=clk_feedback, o_O=clk_feedback_buf)
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self.specials += Instance("BUFG", i_I=clk_dco, o_O=self.cd_dco.clk)
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self.specials += Instance("BUFG", i_I=clk_dco2d, o_O=self.cd_dco2d.clk)
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self.specials += Instance("BUFG", i_I=clk_dco2d_45_degree, o_O=self.cd_dco2d_45_degree.clk)
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self.specials += Instance("BUFG", i_I=clk_dco2x, o_O=self.cd_dco2x.clk)
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# Ignore dco2d to mmcm dco_clk path created by SoC's rst.
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platform.add_false_path_constraints(self.cd_dco2d.clk, dco_clk_buf)
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self.specials += Instance("FD", p_INIT=1, i_D=~self.locked, i_C=self.cd_dco2d.clk, o_Q=self.cd_dco2d.rst)
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class ADC(Module, AutoCSR):
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def __init__(self, platform, dco_freq=200e6):
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adc_pads = platform.request("adc")
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afe_pads = platform.request("adc_afe")
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self.frame_csr = CSRStatus(5)
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self.frame_csr = CSRStatus(4)
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self.data_ch0 = CSRStatus(16)
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self.data_ch1 = CSRStatus(16)
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self.tap_delay = CSRStorage(5)
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self.bitslip_csr = CSRStorage(1)
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self.afe_ctrl = CSRStorage(7)
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self.afe_ctrl = CSRStorage(4)
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tap_delay_val = Signal(5)
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bitslip = Signal()
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@ -131,17 +105,7 @@ class ADC(Module, AutoCSR):
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ch2_shdn = Signal()
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self.data_out = [Signal(16, reset_less=True), Signal(16, reset_less=True)]
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self.data_out_cdc = [Signal(16, reset_less=True), Signal(16, reset_less=True)]
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self.s_frame = Signal(4)
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self.s_frame_cdc = Signal(4)
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self.submodules.cdc_fifo = ClockDomainsRenamer({"write": "dco2d", "read": "sys"})(AsyncFIFO([("data", 36)], 4))
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self.comb += [
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self.cdc_fifo.sink.data.eq(Cat(self.data_out_cdc[0], self.data_out_cdc[1], self.s_frame_cdc)),
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self.cdc_fifo.sink.stb.eq(~ResetSignal("dco2d")),
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Cat(self.data_out[0], self.data_out[1], self.s_frame).eq(self.cdc_fifo.source.data),
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self.cdc_fifo.source.ack.eq(~ResetSignal("sys")),
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]
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###
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@ -153,14 +117,11 @@ class ADC(Module, AutoCSR):
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# dco_clk.n.eq(adc_pads.dco_n),
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tap_delay_val.eq(self.tap_delay.storage),
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Cat(ch1_gain_x10, ch2_gain_x10, ch1_shdn, ch2_shdn).eq(
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self.afe_ctrl.storage[0:4]
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self.afe_ctrl.storage
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),
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]
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self.submodules.crg = CRG(platform, dco_clk, dco_freq)
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self.comb += self.afe_ctrl.storage[4].eq(self.crg.mmcm_rst)
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self.comb += self.afe_ctrl.storage[5].eq(self.crg.ddr_clk_phase_shift_en)
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self.comb += self.afe_ctrl.storage[6].eq(self.crg.ddr_clk_phase_incdec)
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self.submodules._crg = _CRG(platform, dco_clk, dco_freq)
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self.specials += MultiReg(self.bitslip_csr.re, bitslip_re_dco_2d, "dco2d")
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self.sync.dco2d += [
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@ -168,8 +129,7 @@ class ADC(Module, AutoCSR):
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]
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self.comb += [
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self.frame_csr.status[0:4].eq(self.s_frame[0:4]),
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self.frame_csr.status[4].eq(self.crg.locked),
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self.frame_csr.status.eq(self.s_frame),
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self.data_ch0.status.eq(self.data_out[0]),
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self.data_ch1.status.eq(self.data_out[1]),
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]
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@ -186,7 +146,7 @@ class ADC(Module, AutoCSR):
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self.specials += Instance(
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"LTC2195",
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i_rst_in=ResetSignal("dco2d"),
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i_rst_in=ResetSignal("sys"),
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i_clk200=ClockSignal("idelay"),
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i_DCO=ClockSignal("dco"),
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i_DCO_2D=ClockSignal("dco2d"),
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@ -198,9 +158,9 @@ class ADC(Module, AutoCSR):
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i_D1_in_n=adc_pads.data1_n,
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i_bitslip=bitslip,
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i_delay_val=tap_delay_val,
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o_ADC0_out=self.data_out_cdc[1], # LANES swapped on hardware
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o_ADC1_out=self.data_out_cdc[0],
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o_FR_out=self.s_frame_cdc,
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o_ADC0_out=self.data_out[1], # LANES swapped on hardware
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o_ADC1_out=self.data_out[0],
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o_FR_out=self.s_frame,
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o_o_data_from_pins=dummy,
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o_idelay_rdy=dummy_idelay_rdy,
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)
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@ -20,7 +20,6 @@
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from migen import *
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from misoc.interconnect.csr import AutoCSR, CSRStorage
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from migen.genlib.io import DDROutput
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from misoc.interconnect.stream import AsyncFIFO
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class DAC(Module, AutoCSR):
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@ -39,51 +38,37 @@ class DAC(Module, AutoCSR):
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output_data_ch1 = Signal(14)
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self.data_in = [Signal(14, reset_less=True), Signal(14, reset_less=True)]
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self.data_in_csr = [Signal(14, reset_less=True), Signal(14, reset_less=True)]
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self.data_in_cdc = [Signal(14, reset_less=True), Signal(14, reset_less=True)]
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self.data_in_csr_cdc = [Signal(14, reset_less=True), Signal(14, reset_less=True)]
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platform.add_period_constraint(dac_pads.dclkio, 10.0)
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self.submodules.cdc_fifo = ClockDomainsRenamer({"write": "sys", "read": "dco2d"})(AsyncFIFO([("data", 56)], 4))
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self.comb += [
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self.data_in_csr[0].eq(self.output_value_ch0.storage),
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self.data_in_csr[1].eq(self.output_value_ch1.storage),
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self.cdc_fifo.sink.data.eq(Cat(self.data_in[0], self.data_in[1], self.data_in_csr[0], self.data_in_csr[1])),
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self.cdc_fifo.sink.stb.eq(~ResetSignal("sys")),
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Cat(self.data_in_cdc[0], self.data_in_cdc[1], self.data_in_csr_cdc[0], self.data_in_csr_cdc[1]).eq(self.cdc_fifo.source.data),
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self.cdc_fifo.source.ack.eq(~ResetSignal("dco2d")),
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]
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self.comb += [
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Cat(manual_override, ch0_pd, ch1_pd).eq(self.dac_ctrl.storage),
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dac_pads.rst.eq(ResetSignal("dco2d")),
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dac_pads.rst.eq(ResetSignal("sys")),
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dac_afe_pads.ch1_pd_n.eq(~ch0_pd),
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dac_afe_pads.ch2_pd_n.eq(~ch1_pd),
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output_data_ch0.eq(
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Mux(manual_override, self.data_in_csr_cdc[0], self.data_in_cdc[0])
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Mux(manual_override, self.output_value_ch0.storage, self.data_in[0])
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),
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output_data_ch1.eq(
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Mux(manual_override, self.data_in_csr_cdc[1], self.data_in_cdc[1])
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Mux(manual_override, self.output_value_ch1.storage, self.data_in[1])
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),
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]
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self.specials += [
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Instance("ODDR",
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i_C=ClockSignal("dco2d"),
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i_CE=~ResetSignal("dco2d"),
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i_D1=output_data_ch0[lane], # DDR CLK Rising Edge
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i_D2=output_data_ch1[lane], # DDR CLK Falling Edge
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o_Q=dac_pads.data[lane],
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p_DDR_CLK_EDGE="SAME_EDGE")
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for lane in range(14)]
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self.specials += Instance("ODDR",
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i_C=ClockSignal("dco2d_45_degree"),
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i_CE=~ResetSignal("dco2d"),
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i_D1=0,
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i_D2=1,
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o_Q=dac_pads.dclkio,
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p_DDR_CLK_EDGE="SAME_EDGE")
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# data
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for lane in range(14):
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self.specials += DDROutput(
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i1 = output_data_ch0[lane],
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i2 = output_data_ch1[lane],
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o = dac_pads.data[lane],
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clk = ClockSignal("dco2d")
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)
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# clock forwarding
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self.specials += DDROutput(
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i1 = 0b0,
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i2 = 0b1,
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o = dac_pads.dclkio,
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clk = ClockSignal("dco2d"),
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)
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class AUX_DAC_CTRL(Module, AutoCSR):
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|
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@ -147,7 +147,6 @@ class BaseSoC(PS7, AutoCSR):
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# self.add_main_adc(platform)
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self.submodules.adc = ADC(platform)
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self.csr_devices.append("adc")
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platform.add_false_path_constraints(self.crg.cd_sys.clk, self.adc.crg.cd_dco2d.clk)
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# self.add_main_dac(platform)
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self.submodules.dac = DAC(platform)
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|
|
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|
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@ -1,141 +0,0 @@
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# Fix for bus error issues when compiling cpython extensions in pyrp3 v1.2.0+
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# Patch sourced from: https://github.com/linien-org/pyrp3/tree/e6688acf8bd79d2dbe1d192d09c1a1baf1f6c67b (setup.py & monitor/Makefile)
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# Reference: https://github.com/elhep/Fast-Servo-Firmware/blob/master/OS/scripts/linien_install_requirements.sh#L28
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diff --git a/monitor/Makefile b/monitor/Makefile
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new file mode 100644
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index 0000000..044d88e
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--- /dev/null
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+++ b/monitor/Makefile
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@@ -0,0 +1,31 @@
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+# Makefile for libmonitor
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+
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+OBJS = monitor.o
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+SRCS = $(subst .o,.c, $(OBJS))
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+OSOBJS = monitor.os
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+TARGETLIB=libmonitor.so
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+CFLAGS=-g -std=gnu99 -Wall -Werror
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+LIBS=-lm -lpthread
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+
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+# Use CROSS_COMPILE=arm-linux-gnueabi-
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+CC=$(CROSS_COMPILE)gcc
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+INSTALL_DIR ?= .
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+
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+
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+all: $(TARGETLIB)
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+lib: $(TARGETLIB)
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+
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+%.os: %.c
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+ $(CC) -c -fPIC $(CFLAGS) $< -o $@
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+
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+$(TARGETLIB): $(OSOBJS)
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+ $(CC) -o $@ -shared $^ $(CFLAGS) $(LIBS)
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+
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+clean:
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+ rm -f $(TARGETLIB) *.o *.os
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+
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+# Install target - creates 'lib/' sub-directory in $(INSTALL_DIR) and copies all
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+# executables to that location.
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+install:
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+ mkdir -p $(INSTALL_DIR)/lib
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+ cp $(TARGETLIB) $(INSTALL_DIR)/lib
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\ No newline at end of file
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diff --git a/pyrp3/raw_memory.py b/pyrp3/raw_memory.py
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index ce1b28e..233b82a 100644
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--- a/pyrp3/raw_memory.py
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+++ b/pyrp3/raw_memory.py
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@@ -1,12 +1,9 @@
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from ctypes import POINTER, c_uint32, cast, cdll, create_string_buffer, sizeof
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-from importlib.machinery import EXTENSION_SUFFIXES
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from pathlib import Path
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import numpy as np
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|
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-libmonitor_file = str(
|
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- Path(__file__).parent / ".." / "monitor{}".format(EXTENSION_SUFFIXES[0])
|
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-)
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+libmonitor_file = 'libmonitor.so'
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|
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libmonitor = cdll.LoadLibrary(libmonitor_file)
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libmonitor.read_value.restype = c_uint32
|
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diff --git a/setup.py b/setup.py
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index 98bdaee..b0a8af4 100644
|
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--- a/setup.py
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+++ b/setup.py
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@@ -1,5 +1,10 @@
|
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import re
|
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-from distutils.core import Extension, setup
|
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+import os
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+
|
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+from distutils.core import setup
|
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+from distutils.command.build import build
|
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+from distutils.command.install import install
|
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+
|
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from pathlib import Path
|
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|
||||
# from https://stackoverflow.com/a/7071358/2750945
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@@ -11,9 +16,50 @@ if mo:
|
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verstr = mo.group(1)
|
||||
else:
|
||||
raise RuntimeError("Unable to find version string in %s." % (VERSIONFILE,))
|
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+
|
||||
+# Patch from https://github.com/linien-org/pyrp3/blob/e6688acf8bd79d2dbe1d192d09c1a1baf1f6c67b/setup.py#L16-L55
|
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+build_dir = "monitor/"
|
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+
|
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+def compile_libmonitor():
|
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+ cwd = os.getcwd() # get current directory
|
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+ try:
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+ os.chdir(build_dir)
|
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+ os.system("make clean")
|
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+ os.system("make all")
|
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+ finally:
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+ os.chdir(cwd)
|
||||
+
|
||||
+
|
||||
+def install_libmonitor(prefix=""):
|
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+ cwd = os.getcwd() # get current directory
|
||||
+ try:
|
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+ os.chdir(build_dir)
|
||||
+ os.system("make install INSTALL_DIR={prefix}".format(prefix=prefix))
|
||||
+ finally:
|
||||
+ os.chdir(cwd)
|
||||
+
|
||||
+
|
||||
+class lib_build(build):
|
||||
+ def run(self):
|
||||
+ compile_libmonitor()
|
||||
+ build.run(self)
|
||||
+
|
||||
+
|
||||
+class lib_install(install):
|
||||
+ def run(self):
|
||||
+ compile_libmonitor()
|
||||
+ install_libmonitor(self.prefix)
|
||||
+ # install.run(self)
|
||||
+
|
||||
+# Will use nix to install libmonitor
|
||||
+cmdclass = {
|
||||
+ "build": lib_build
|
||||
+}
|
||||
+
|
||||
this_directory = Path(__file__).parent
|
||||
long_description = (this_directory / "README.rst").read_text()
|
||||
|
||||
+
|
||||
setup(
|
||||
name="pyrp3",
|
||||
version=verstr,
|
||||
@@ -32,6 +78,7 @@ setup(
|
||||
"cached_property>=1.5.2",
|
||||
"numpy>=1.11.0",
|
||||
],
|
||||
+ cmdclass=cmdclass,
|
||||
classifiers=[
|
||||
"Intended Audience :: Developers",
|
||||
"Intended Audience :: Education",
|
||||
@@ -45,5 +92,4 @@ setup(
|
||||
"Topic :: Software Development :: Libraries :: Python Modules",
|
||||
],
|
||||
keywords=["redpitaya", "FPGA", "zynq"],
|
||||
- ext_modules=[Extension("monitor", ["monitor/monitor.c"])],
|
||||
)
|
||||
|
|
@ -17,9 +17,11 @@
|
|||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program. If not, see <https://www.gnu.org/licenses/>.
|
||||
|
||||
import time
|
||||
import mmap
|
||||
import os
|
||||
|
||||
import spidev
|
||||
from pyfastservo.common import (
|
||||
from common import (
|
||||
ADC_AFE_CTRL_ADDR,
|
||||
ADC_BITSLIP_ADDR,
|
||||
ADC_CH0_HIGH_ADDR,
|
||||
|
|
@ -31,8 +33,6 @@ from pyfastservo.common import (
|
|||
AUX_ADC_ADDR,
|
||||
MAP_MASK,
|
||||
PAGESIZE,
|
||||
write_to_memory,
|
||||
read_from_memory
|
||||
)
|
||||
|
||||
# /dev/spidev1.0 <=> spidev<BUS>.<DEVICE>
|
||||
|
|
@ -44,181 +44,276 @@ AUX_ADC_PORT_A = 2
|
|||
AUX_ADC_PORT_B = 3
|
||||
|
||||
|
||||
def spi_write(spi, address, value):
|
||||
spi.xfer2([address, value])
|
||||
|
||||
def spi_read(spi, address):
|
||||
rx_buffer = spi.xfer2([0x80 | address, 0x00])
|
||||
return rx_buffer[1]
|
||||
|
||||
def main_adc_config(spi, test_pattern):
|
||||
def main_adc_config(test_pattern):
|
||||
high_word = (test_pattern & 0xFF00) >> 8
|
||||
low_word = test_pattern & 0xFF
|
||||
|
||||
spi_write(spi, 0x00, 0x80) # reset
|
||||
spi_write(spi, 0x01, 0x20) # REGISTER A1: set to Two's complement Data Format
|
||||
spi_write(spi, 0x02, 0x15) # REGISTER A2: set to LVDS output, set 4 data lanes and turn on test mode
|
||||
spi_write(spi, 0x03, high_word) # REGISTER A3: test pattern high word
|
||||
spi_write(spi, 0x04, low_word) # REGISTER A4: test pattern low word
|
||||
|
||||
def main_adc_test_mode(spi, enable):
|
||||
reg_contents = 0x15 if enable else 0x11 # set to LVDS output, set 4 data lanes and turn on or off test mode
|
||||
spi_write(spi, 0x02, reg_contents)
|
||||
|
||||
def verify_adc_registers(spi, reg_to_check):
|
||||
for register, expected_value in reg_to_check.items():
|
||||
value = spi_read(spi, register)
|
||||
print(f"Spi readback register 0x{register:02x}: 0x{value:02x}")
|
||||
if value != expected_value:
|
||||
print(f"Different value read than sent in reg 0x{register:02x}")
|
||||
|
||||
def read_frame():
|
||||
return read_from_memory(ADC_FRAME_ADDR, 1)[0]
|
||||
|
||||
def perform_bitslip():
|
||||
for i in range(4):
|
||||
current_frame = read_frame()
|
||||
if current_frame & 0x0F != 0x0C:
|
||||
print(f"Performing bitslip (iteration: {i}). Current frame: 0x{current_frame:02x}")
|
||||
write_to_memory(ADC_BITSLIP_ADDR, 1)
|
||||
else:
|
||||
print(f"No bitslip required; Current frame: 0x{current_frame:02x}")
|
||||
return
|
||||
|
||||
def mmcm_rst():
|
||||
curr_cfg = read_from_memory(ADC_AFE_CTRL_ADDR, 1)[0] & 0x0F
|
||||
write_to_memory(ADC_AFE_CTRL_ADDR, 0x10 | curr_cfg) # Reset MMCM
|
||||
write_to_memory(ADC_AFE_CTRL_ADDR, 0x00 | curr_cfg) # Release MMCM Reset
|
||||
while not(read_frame() & 0x10):
|
||||
print(f"Waiting for MMCM to lock")
|
||||
time.sleep(0.001)
|
||||
|
||||
def inc_ddr_clk_phase():
|
||||
curr_cfg = read_from_memory(ADC_AFE_CTRL_ADDR, 1)[0] & 0x1F
|
||||
write_to_memory(ADC_AFE_CTRL_ADDR, 0x40 | curr_cfg) # Set MMCM Phase Shift to be INC
|
||||
write_to_memory(ADC_AFE_CTRL_ADDR, 0x60 | curr_cfg) # Assert MMCM Phase Shift EN High
|
||||
write_to_memory(ADC_AFE_CTRL_ADDR, curr_cfg) # Deassert MMCM Phase Shift EN High
|
||||
|
||||
def dec_ddr_clk_phase():
|
||||
curr_cfg = read_from_memory(ADC_AFE_CTRL_ADDR, 1)[0] & 0x1F
|
||||
write_to_memory(ADC_AFE_CTRL_ADDR, 0x00 | curr_cfg) # Set MMCM Phase Shift to be DEC
|
||||
write_to_memory(ADC_AFE_CTRL_ADDR, 0x20 | curr_cfg) # Assert MMCM Phase Shift EN High
|
||||
write_to_memory(ADC_AFE_CTRL_ADDR, curr_cfg) # Deassert MMCM Phase Shift EN High
|
||||
|
||||
def find_edge():
|
||||
prev_frame = read_frame()
|
||||
for tap_delay in range(32):
|
||||
write_to_memory(ADC_DELAY_ADDR, tap_delay)
|
||||
current_frame = read_frame()
|
||||
|
||||
print(f"Tap delay: {tap_delay}, Current frame: 0x{current_frame:02x}")
|
||||
print(f"prev_frame: 0x{prev_frame:02x}")
|
||||
|
||||
if current_frame != prev_frame:
|
||||
final_delay = ((tap_delay+1) // 2) + 2
|
||||
print(f"Edge detected; setting iDelay to: {final_delay}")
|
||||
write_to_memory(ADC_DELAY_ADDR, final_delay)
|
||||
return
|
||||
|
||||
prev_frame = current_frame
|
||||
|
||||
# If no edge detected
|
||||
final_delay = 11
|
||||
print(f"No edge detected; setting iDelay to: {final_delay}")
|
||||
write_to_memory(ADC_DELAY_ADDR, final_delay)
|
||||
|
||||
def read_adc_channel(high_addr, low_addr):
|
||||
return (read_from_memory(high_addr, 1)[0] << 8) | read_from_memory(low_addr, 1)[0]
|
||||
|
||||
def print_adc_channels():
|
||||
adc_ch0 = read_adc_channel(ADC_CH0_HIGH_ADDR, ADC_CH0_LOW_ADDR)
|
||||
adc_ch1 = read_adc_channel(ADC_CH1_HIGH_ADDR, ADC_CH1_LOW_ADDR)
|
||||
print(f"Final ADC_CH0: 0x{adc_ch0:04x}")
|
||||
print(f"Final ADC_CH1: 0x{adc_ch1:04x}")
|
||||
|
||||
def enable_adc_afe(ch1_x10=False, ch2_x10=False):
|
||||
ctrl_value = (ch2_x10 << 1) | ch1_x10
|
||||
write_to_memory(ADC_AFE_CTRL_ADDR, ctrl_value)
|
||||
afe_ctrl = read_from_memory(ADC_AFE_CTRL_ADDR, 1)[0]
|
||||
print(f"ADC_AFE_CTRL: 0x{afe_ctrl:02X}")
|
||||
return afe_ctrl
|
||||
|
||||
def search_edge():
|
||||
for tap_delay in range(32):
|
||||
print(f"iDelay to: {tap_delay}")
|
||||
write_to_memory(ADC_DELAY_ADDR, tap_delay)
|
||||
time.sleep(1)
|
||||
current_frame = read_frame()
|
||||
print(f"Tap delay: {tap_delay}, Current frame: 0x{current_frame:02x}")
|
||||
print_adc_channels()
|
||||
|
||||
def print_adc_channel(ch):
|
||||
if ch == 0:
|
||||
adc_ch0 = read_adc_channel(ADC_CH0_HIGH_ADDR, ADC_CH0_LOW_ADDR)
|
||||
print(f"Final ADC_CH0: 0x{adc_ch0:04x}")
|
||||
if ch == 1:
|
||||
adc_ch1 = read_adc_channel(ADC_CH1_HIGH_ADDR, ADC_CH1_LOW_ADDR)
|
||||
print(f"Final ADC_CH1: 0x{adc_ch1:04x}")
|
||||
|
||||
def find_min_max_ch(ch):
|
||||
test = []
|
||||
for i in range(100):
|
||||
if ch == 0:
|
||||
test.append(read_adc_channel(ADC_CH0_HIGH_ADDR, ADC_CH0_LOW_ADDR))
|
||||
else:
|
||||
test.append(read_adc_channel(ADC_CH1_HIGH_ADDR, ADC_CH1_LOW_ADDR))
|
||||
print("ch", ch, hex(test[-1]))
|
||||
print("Min:", hex(min(test)))
|
||||
print("Max:", hex(max(test)))
|
||||
print("Diff:", hex(max(test)-min(test)))
|
||||
|
||||
|
||||
def configure_ltc2195():
|
||||
spi = spidev.SpiDev()
|
||||
|
||||
try:
|
||||
spi.open(MAIN_ADC_BUS, MAIN_ADC_DEVICE)
|
||||
spi.max_speed_hz = 50000
|
||||
spi.mode = 0b00 # CPOL = 0 CPHA = 0
|
||||
spi.cshigh = False
|
||||
spi.cshigh = True
|
||||
# spi.read0 = False
|
||||
|
||||
test_pattern = 0x811F
|
||||
main_adc_config(spi, test_pattern)
|
||||
spi_buffer = [0x00, 0x80] # reset
|
||||
rx_buffer = [0x00, 0x00]
|
||||
|
||||
verify_adc_registers(spi, {
|
||||
0x01: 0x20,
|
||||
0x02: 0x15,
|
||||
0x03: (test_pattern & 0xFF00) >> 8,
|
||||
0x04: test_pattern & 0xFF
|
||||
})
|
||||
spi.xfer2(spi_buffer)
|
||||
|
||||
# ADC software reset put its PLL to sleep momentarily. Thus, MMCM needs to be reset as well.
|
||||
mmcm_rst()
|
||||
|
||||
# Performing Word Align
|
||||
perform_bitslip()
|
||||
find_edge()
|
||||
|
||||
# Printing it once is not enough to check whether the alignment is correct.
|
||||
for i in range(100):
|
||||
print_adc_channels()
|
||||
# REGISTER A1
|
||||
spi_buffer = [0x01, 0x20] # set to Two's complement Data Format
|
||||
spi.xfer2(spi_buffer)
|
||||
|
||||
main_adc_test_mode(spi, False)
|
||||
verify_adc_registers(spi, {0x02: 0x11}) # Verify test mode is off
|
||||
|
||||
# FIXME: AFE Gain 1x is not functional on that batch of fast servo under development
|
||||
enable_adc_afe(ch1_x10=1, ch2_x10=1)
|
||||
# read values back
|
||||
spi_buffer = [0x81, 0x00]
|
||||
rx_buffer = spi.xfer2(spi_buffer)
|
||||
print(f"Spi readback register 0x01: 0x{rx_buffer[1]:02x}")
|
||||
if rx_buffer[1] != 0x20:
|
||||
print("Different value read than sent in reg 0x02")
|
||||
|
||||
#find_min_max_ch(0)
|
||||
#find_min_max_ch(1)
|
||||
# REGISTER A2
|
||||
spi_buffer = [
|
||||
0x02,
|
||||
0x15,
|
||||
] # set to LVDS output, set 4 data lanes and turn on test mode
|
||||
spi.xfer2(spi_buffer)
|
||||
|
||||
#for i in range(10):
|
||||
# print_adc_channel(0)
|
||||
# read values back
|
||||
spi_buffer = [0x82, 0x00]
|
||||
rx_buffer = spi.xfer2(spi_buffer)
|
||||
print(f"Spi readback register 0x02: 0x{rx_buffer[1]:02x}")
|
||||
if rx_buffer[1] != 0x15:
|
||||
print("Different value read than sent in reg 0x02")
|
||||
|
||||
#for i in range(10):
|
||||
# print_adc_channel(1)
|
||||
# REGISTER A3
|
||||
# test pattern high word
|
||||
spi_buffer = [0x03, high_word]
|
||||
spi.xfer2(spi_buffer)
|
||||
|
||||
# read balues back
|
||||
spi_buffer = [0x83, 0x00]
|
||||
rx_buffer = spi.xfer2(spi_buffer)
|
||||
print(f"Spi readback register 0x03: 0x{rx_buffer[1]:02x}")
|
||||
if rx_buffer[1] != high_word:
|
||||
print("Different value read than sent in reg 0x03")
|
||||
|
||||
# REGISTER A4
|
||||
# test pattern low word
|
||||
spi_buffer = [0x04, low_word]
|
||||
spi.xfer2(spi_buffer)
|
||||
|
||||
# read balues back
|
||||
spi_buffer = [0x84, 0x00]
|
||||
rx_buffer = spi.xfer2(spi_buffer)
|
||||
print(f"Spi readback register 0x04: 0x{rx_buffer[1]:02x}")
|
||||
if rx_buffer[1] != low_word:
|
||||
print("Different value read than sent in reg 0x04")
|
||||
finally:
|
||||
spi.close()
|
||||
|
||||
|
||||
def main_adc_test_mode(enable):
|
||||
spi = spidev.SpiDev()
|
||||
|
||||
try:
|
||||
spi.open(MAIN_ADC_BUS, MAIN_ADC_DEVICE)
|
||||
spi.max_speed_hz = 50000
|
||||
spi.mode = 0b00 # CPOL = 0 CPHA = 0
|
||||
spi.cshigh = True
|
||||
# spi.read0 = True
|
||||
|
||||
reg_contents = (
|
||||
0x15 if enable else 0x11
|
||||
) # set to LVDS output, set 4 data lanes and turn on or off test mode
|
||||
spi_buffer = [0x02, reg_contents]
|
||||
spi.xfer2(spi_buffer)
|
||||
|
||||
# read values back
|
||||
spi_buffer = [0x82, 0x00]
|
||||
rx_buffer = spi.xfer2(spi_buffer)
|
||||
print(f"Spi readback register 0x02: 0x{rx_buffer[1]:02x}")
|
||||
if rx_buffer[1] != reg_contents:
|
||||
print("Different value read than sent in reg 0x02")
|
||||
finally:
|
||||
spi.close()
|
||||
|
||||
|
||||
def read_from_memory(address, n_bytes):
|
||||
assert n_bytes <= 4
|
||||
addr = address
|
||||
|
||||
try:
|
||||
f = os.open("/dev/mem", os.O_SYNC | os.O_RDWR)
|
||||
with mmap.mmap(
|
||||
f,
|
||||
PAGESIZE,
|
||||
mmap.MAP_SHARED,
|
||||
mmap.PROT_READ | mmap.PROT_WRITE,
|
||||
offset=addr & ~MAP_MASK,
|
||||
) as mem:
|
||||
start_addr = addr & MAP_MASK
|
||||
stop_addr = start_addr + 4
|
||||
# print(f"addr: 0x{addr:x}\tstart_addr: 0x{start_addr}\tstop_addr: 0x{stop_addr}")
|
||||
contents = mem[start_addr:stop_addr]
|
||||
read_value = list(contents)[:n_bytes]
|
||||
# print("Read value: ", read_value)
|
||||
finally:
|
||||
os.close(f)
|
||||
|
||||
return read_value
|
||||
|
||||
|
||||
def write_to_memory(address, value):
|
||||
value_bytes = value.to_bytes(4, "little")
|
||||
addr = address
|
||||
|
||||
try:
|
||||
f = os.open("/dev/mem", os.O_SYNC | os.O_RDWR)
|
||||
with mmap.mmap(
|
||||
f,
|
||||
PAGESIZE,
|
||||
mmap.MAP_SHARED,
|
||||
mmap.PROT_READ | mmap.PROT_WRITE,
|
||||
offset=addr & ~MAP_MASK,
|
||||
) as mem:
|
||||
start_addr = addr & MAP_MASK
|
||||
stop_addr = start_addr + 4
|
||||
# print(f"addr: 0x{addr:x}\tstart_addr: 0x{start_addr}\tstop_addr: 0x{stop_addr}")
|
||||
mem[start_addr:stop_addr] = value_bytes
|
||||
contents = mem[start_addr:stop_addr]
|
||||
# print("Read value: ", list(contents), " written value: ", list(value_bytes))
|
||||
finally:
|
||||
os.close(f)
|
||||
|
||||
|
||||
def word_align():
|
||||
|
||||
value = 0
|
||||
edge_detected = False
|
||||
transition = False
|
||||
tap_delay = 0
|
||||
|
||||
for i in range(4):
|
||||
current_frame = read_from_memory(ADC_FRAME_ADDR, 1)[0]
|
||||
if current_frame != 0x0C:
|
||||
print(
|
||||
f"Performing bitslip (bitslip iteration: {i}). Reason: current_frame is 0x{current_frame:02x} instead of 0x0C"
|
||||
)
|
||||
write_to_memory(ADC_BITSLIP_ADDR, 1)
|
||||
else:
|
||||
print(f"No bitslip required; Currernt frame = 0x{current_frame:02x}")
|
||||
break
|
||||
|
||||
current_frame = read_from_memory(ADC_FRAME_ADDR, 1)[0]
|
||||
prev_frame = current_frame
|
||||
|
||||
for i in range(32):
|
||||
write_to_memory(ADC_DELAY_ADDR, tap_delay)
|
||||
if edge_detected == 1:
|
||||
break
|
||||
current_frame = read_from_memory(ADC_FRAME_ADDR, 1)[0]
|
||||
|
||||
print(f"Tap delay: {tap_delay}")
|
||||
print(f"Current frame: 0x{current_frame:02x}")
|
||||
|
||||
if current_frame == prev_frame:
|
||||
tap_delay += 1
|
||||
elif not transition:
|
||||
tap_delay += 1
|
||||
transition = True
|
||||
elif transition:
|
||||
tap_delay = i // 2
|
||||
edge_detected = True
|
||||
|
||||
prev_frame = current_frame
|
||||
|
||||
if not edge_detected:
|
||||
tap_delay = 11 # empirically tested to work best
|
||||
write_to_memory(ADC_DELAY_ADDR, tap_delay)
|
||||
print(f"No edge detected; setting iDelay to: {tap_delay}")
|
||||
if edge_detected:
|
||||
write_to_memory(ADC_DELAY_ADDR, tap_delay + 2)
|
||||
print(f"Edge detected; setting iDelay to (tap_delay + 2): {tap_delay} + 2")
|
||||
|
||||
adc_ch0 = read_from_memory(ADC_CH0_HIGH_ADDR, 4)
|
||||
print(f"ADC_CH0: 0x{adc_ch0}")
|
||||
|
||||
adc_ch0 = (read_from_memory(ADC_CH0_HIGH_ADDR, 1)[0] << 8) | read_from_memory(
|
||||
ADC_CH0_LOW_ADDR, 1
|
||||
)[0]
|
||||
adc_ch1 = (read_from_memory(ADC_CH1_HIGH_ADDR, 1)[0] << 8) | read_from_memory(
|
||||
ADC_CH1_LOW_ADDR, 1
|
||||
)[0]
|
||||
print(f"Final ADC_CH0: 0x{adc_ch0:04x}")
|
||||
print(f"Final ADC_CH1: 0x{adc_ch1:04x}")
|
||||
|
||||
|
||||
def modify_bit(original_value, position, bit_value):
|
||||
mask = 1 << position
|
||||
return (original_value & ~mask) | (bit_value << position)
|
||||
|
||||
|
||||
def adc_aux_config():
|
||||
# MSB to LSB
|
||||
# | RANGE | ADDR [2:0] | DIFF |
|
||||
# DIFF = 0 => configure as single ended (it is negated in gateware)
|
||||
# RANGE = 0 => configure as 0-2.5 Vref
|
||||
to_write = 0b00000
|
||||
write_to_memory(AUX_ADC_ADDR, to_write)
|
||||
|
||||
|
||||
def adc_aux_read(port, type, pin):
|
||||
# port:
|
||||
# 1 - port A
|
||||
# 2 - port B
|
||||
# type:
|
||||
# 0 - single-ended
|
||||
# 1 - differential
|
||||
# pin:
|
||||
# 0b000 - VA1/VB1
|
||||
# 0b001 - VA2/VB2
|
||||
# 0b010 - VA3/VB3
|
||||
# 0b011 - VA4/VB4
|
||||
|
||||
assert type in (0, 1)
|
||||
assert port in (1, 2)
|
||||
|
||||
write_buffer = [0, 0]
|
||||
read_buffer = [0, 0]
|
||||
|
||||
aux_config_reg = read_from_memory(AUX_ADC_ADDR, 1)[0]
|
||||
aux_config = (aux_config_reg & 0b10001) | pin << 1
|
||||
write_to_memory(AUX_ADC_ADDR, aux_config)
|
||||
|
||||
spi = spidev.SpiDev()
|
||||
try:
|
||||
spi.open(1, 3) # AUX ADC 1?
|
||||
spi.max_speed_hz = 5000
|
||||
spi.mode = 0b00
|
||||
spi.cshigh = True
|
||||
|
||||
read_buffer = spi.xfer2(write_buffer)
|
||||
mu_voltage = read_buffer[0] << 8 | read_buffer[1] >> 2
|
||||
print(f"MU_voltage: 0x{mu_voltage:04X}")
|
||||
print(f"Read_buffer[0]: 0x{read_buffer[0]:02X}")
|
||||
print(f"Read_buffer[1]: 0x{read_buffer[1]:02X}")
|
||||
return mu_voltage * 2.5 / 4096
|
||||
|
||||
finally:
|
||||
spi.close()
|
||||
|
||||
|
||||
def main():
|
||||
main_adc_config(0x811F)
|
||||
word_align()
|
||||
|
||||
main_adc_test_mode(False)
|
||||
|
||||
write_to_memory(ADC_AFE_CTRL_ADDR, 0b1100) # {-, -, ch2_X10, ch1_X10}
|
||||
print(read_from_memory(ADC_AFE_CTRL_ADDR, 1)[0])
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
configure_ltc2195()
|
||||
main()
|
||||
|
|
@ -17,16 +17,13 @@
|
|||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program. If not, see <https://www.gnu.org/licenses/>.
|
||||
|
||||
import os
|
||||
import mmap
|
||||
|
||||
CSR_SIZE = 0x800
|
||||
MAP_SIZE = 0x1000
|
||||
MAP_MASK = 0xFFF
|
||||
PAGESIZE = 0x1000
|
||||
|
||||
# LINIEN_OFFSET = 0x0
|
||||
LINIEN_OFFSET = 0x300000
|
||||
LINIEN_OFFSET = 0x0
|
||||
# LINIEN_OFFSET = 0x300000
|
||||
|
||||
# ----------------------------------------------------------------
|
||||
# FRONT PANEL LEDS REGISTER ADDRESSES
|
||||
|
|
@ -74,47 +71,4 @@ CTRL_ADDR = DAC_BASE_ADDR + CTRL_OFFSET
|
|||
CH0_HIGH_WORD_ADDR = DAC_BASE_ADDR + CH0_HIGH_WORD_OFFSET
|
||||
CH0_LOW_WORD_ADDR = DAC_BASE_ADDR + CH0_LOW_WORD_OFFSET
|
||||
CH1_HIGH_WORD_ADDR = DAC_BASE_ADDR + CH1_HIGH_WORD_OFFSET
|
||||
CH1_LOW_WORD_ADDR = DAC_BASE_ADDR + CH1_LOW_WORD_OFFSET
|
||||
|
||||
|
||||
def read_from_memory(address, n_bytes):
|
||||
assert n_bytes <= 4
|
||||
addr = address
|
||||
|
||||
try:
|
||||
f = os.open("/dev/mem", os.O_SYNC | os.O_RDWR)
|
||||
with mmap.mmap(
|
||||
f,
|
||||
PAGESIZE,
|
||||
mmap.MAP_SHARED,
|
||||
mmap.PROT_READ | mmap.PROT_WRITE,
|
||||
offset=addr & ~MAP_MASK,
|
||||
) as mem:
|
||||
start_addr = addr & MAP_MASK
|
||||
stop_addr = start_addr + 4
|
||||
contents = mem[start_addr:stop_addr]
|
||||
read_value = list(contents)[:n_bytes]
|
||||
finally:
|
||||
os.close(f)
|
||||
|
||||
return read_value
|
||||
|
||||
def write_to_memory(address, value):
|
||||
value_bytes = value.to_bytes(4, "little")
|
||||
addr = address
|
||||
|
||||
try:
|
||||
f = os.open("/dev/mem", os.O_SYNC | os.O_RDWR)
|
||||
with mmap.mmap(
|
||||
f,
|
||||
PAGESIZE,
|
||||
mmap.MAP_SHARED,
|
||||
mmap.PROT_READ | mmap.PROT_WRITE,
|
||||
offset=addr & ~MAP_MASK,
|
||||
) as mem:
|
||||
start_addr = addr & MAP_MASK
|
||||
stop_addr = start_addr + 4
|
||||
mem[start_addr:stop_addr] = value_bytes
|
||||
contents = mem[start_addr:stop_addr]
|
||||
finally:
|
||||
os.close(f)
|
||||
CH1_LOW_WORD_ADDR = DAC_BASE_ADDR + CH1_LOW_WORD_OFFSET
|
||||
|
|
@ -17,10 +17,11 @@
|
|||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program. If not, see <https://www.gnu.org/licenses/>.
|
||||
|
||||
import time
|
||||
import mmap
|
||||
import os
|
||||
|
||||
import spidev
|
||||
from pyfastservo.common import (
|
||||
from common import (
|
||||
CH0_HIGH_WORD_ADDR,
|
||||
CH0_LOW_WORD_ADDR,
|
||||
CH1_HIGH_WORD_ADDR,
|
||||
|
|
@ -28,69 +29,117 @@ from pyfastservo.common import (
|
|||
CTRL_ADDR,
|
||||
MAP_MASK,
|
||||
PAGESIZE,
|
||||
write_to_memory,
|
||||
read_from_memory
|
||||
)
|
||||
|
||||
# /dev/spidev2.0 <=> spidev<BUS>.<DEVICE>
|
||||
MAIN_DAC_BUS = 2
|
||||
MAIN_DAC_DEVICE = 0
|
||||
|
||||
DAC_VERSION = 0x0A
|
||||
|
||||
|
||||
def spi_write(spi, address, value):
|
||||
spi.xfer2([address, value])
|
||||
def main_dac_init():
|
||||
spi = spidev.SpiDev()
|
||||
|
||||
def spi_read(spi, address):
|
||||
rx_buffer = spi.xfer2([0x80 | address, 0x00])
|
||||
return rx_buffer[1]
|
||||
try:
|
||||
spi.open(MAIN_DAC_BUS, MAIN_DAC_DEVICE)
|
||||
spi.max_speed_hz = 5000
|
||||
spi.mode = 0b00 # CPOL = 0 CPHA = 0
|
||||
spi.cshigh = True
|
||||
|
||||
def soft_reset(spi):
|
||||
spi_write(spi, 0x00, 0x10) # Software reset
|
||||
spi_write(spi, 0x00, 0x00) # Release software reset
|
||||
spi_read(spi, 0x00) # Read reset address (necessary for reset to take effect)
|
||||
spi_buffer = [0x00, 0x10] # software reset
|
||||
spi.xfer2(spi_buffer)
|
||||
|
||||
def check_version(spi):
|
||||
version = spi_read(spi, 0x1F)
|
||||
print(f"DAC version: 0x{version:02X}")
|
||||
return version == DAC_VERSION
|
||||
spi_buffer = [0x00, 0x00] # release software reset
|
||||
spi.xfer2(spi_buffer)
|
||||
|
||||
def configure_dac(spi):
|
||||
power_down_reg = spi_read(spi, 0x01)
|
||||
spi_write(spi, 0x01, power_down_reg & ~(1 << 0)) # Clear EXTREF bit for internal reference
|
||||
spi_write(spi, 0x0D, 0x00) # Set RREF to 10 kΩ for 1.0V reference
|
||||
spi_write(spi, 0x04, 0xA0) # Enable on-chip IRSET (1.6 kΩ for 20mA output)
|
||||
spi_write(spi, 0x07, 0xA0) # Enable on-chip QRSET (1.6 kΩ for 20mA output)
|
||||
spi_write(spi, 0x05, 0x00) # Disable internal IRCML
|
||||
spi_write(spi, 0x08, 0x00) # Disable internal QRCML
|
||||
spi_write(spi, 0x02, 0xB4) # Enable 2's complement, IFirst: True, IRising: True, DCI_EN: Enabled
|
||||
spi_write(spi, 0x14, 0x00)
|
||||
spi_write(spi, 0x14, 0x08) # Trigger the retimer to reacquire the clock relationship
|
||||
spi_write(spi, 0x14, 0x00)
|
||||
spi_buffer = [
|
||||
0x80,
|
||||
0x00,
|
||||
] # for some reason it is needed to read the reset address for reset to actually reset
|
||||
rx_buffer = spi.xfer2(spi_buffer)
|
||||
|
||||
def dac_self_calibration(spi):
|
||||
spi_write(spi, 0x12, 0x00) # Reset calibration status
|
||||
spi_write(spi, 0x0E, 0x08) # Enable calibration clock, default divide ratio
|
||||
spi_write(spi, 0x0E, 0x38) # CALSELI = 1, CALSELQ = 1, CALCLK = 1
|
||||
spi_write(spi, 0x12, 0x10) # Set CALEN bit
|
||||
spi_buffer = [0x9F, 0x00] # hardware version
|
||||
rx_buffer = spi.xfer2(spi_buffer)
|
||||
if rx_buffer[1] != DAC_VERSION:
|
||||
print(f"Unrecognized device: 0x{rx_buffer[1]:02X}")
|
||||
|
||||
while True:
|
||||
status = spi_read(spi, 0x0F)
|
||||
if status & 0xC0 == 0xC0: # Both CALSTATI and CALSTATQ are 1
|
||||
break
|
||||
time.sleep(0.01)
|
||||
print("=== Contents of spi buffer after DAC VERSION read back: ===")
|
||||
print(f"0x{rx_buffer[0]:02X}{rx_buffer[1]:02X}")
|
||||
|
||||
spi_buffer = [0x82, 00]
|
||||
rx_buffer = spi.xfer2(spi_buffer)
|
||||
print(f"0x{rx_buffer[0]:02X}{rx_buffer[1]:02X}")
|
||||
|
||||
# set to 2's complement and I to be first of pair on data input pads
|
||||
spi_buffer = [0x02, 0xB4]
|
||||
rx_buffer = spi.xfer2(spi_buffer)
|
||||
spi_buffer = [0x82, 00]
|
||||
rx_buffer = spi.xfer2(spi_buffer)
|
||||
print(f"0x{rx_buffer[0]:02X}{rx_buffer[1]:02X}")
|
||||
|
||||
for i in range(10):
|
||||
spi_buffer = [0x94, 0x00]
|
||||
rx_buffer = spi.xfer2(spi_buffer)
|
||||
print(f"0x{rx_buffer[0]:02X}{rx_buffer[1]:02X}")
|
||||
|
||||
finally:
|
||||
spi.close()
|
||||
|
||||
|
||||
def read_from_memory(address, n_bytes):
|
||||
assert n_bytes <= 4
|
||||
addr = address
|
||||
|
||||
try:
|
||||
f = os.open("/dev/mem", os.O_SYNC | os.O_RDWR)
|
||||
with mmap.mmap(
|
||||
f,
|
||||
PAGESIZE,
|
||||
mmap.MAP_SHARED,
|
||||
mmap.PROT_READ | mmap.PROT_WRITE,
|
||||
offset=addr & ~MAP_MASK,
|
||||
) as mem:
|
||||
start_addr = addr & MAP_MASK
|
||||
stop_addr = start_addr + 4
|
||||
# print(f"addr: 0x{addr:x}\tstart_addr: 0x{start_addr}\tstop_addr: 0x{stop_addr}")
|
||||
contents = mem[start_addr:stop_addr]
|
||||
read_value = list(contents)[:n_bytes]
|
||||
finally:
|
||||
os.close(f)
|
||||
|
||||
return read_value
|
||||
|
||||
|
||||
def write_to_memory(address, value):
|
||||
value_bytes = value.to_bytes(4, "little")
|
||||
addr = address
|
||||
|
||||
try:
|
||||
f = os.open("/dev/mem", os.O_SYNC | os.O_RDWR)
|
||||
with mmap.mmap(
|
||||
f,
|
||||
PAGESIZE,
|
||||
mmap.MAP_SHARED,
|
||||
mmap.PROT_READ | mmap.PROT_WRITE,
|
||||
offset=addr & ~MAP_MASK,
|
||||
) as mem:
|
||||
start_addr = addr & MAP_MASK
|
||||
stop_addr = start_addr + 4
|
||||
mem[start_addr:stop_addr] = value_bytes
|
||||
contents = mem[start_addr:stop_addr]
|
||||
finally:
|
||||
os.close(f)
|
||||
|
||||
spi_write(spi, 0x12, 0x00) # Clear calibration bits
|
||||
spi_write(spi, 0x0E, 0x30) # Keep CALSELI and CALSELQ set, clear CALCLK
|
||||
print("DAC self-calibration completed")
|
||||
|
||||
def manual_override(enable=True):
|
||||
reg_contents = read_from_memory(CTRL_ADDR, 1)[0]
|
||||
print(f"REG contents: 0b{reg_contents:03b}")
|
||||
to_write = reg_contents | 0b1 if enable else reg_contents & 0b110
|
||||
write_to_memory(CTRL_ADDR, to_write)
|
||||
print(f"Set DAC Output Manual Override: {enable}")
|
||||
|
||||
def power_down_afe(channel, power_down=True):
|
||||
|
||||
def power_down(channel, power_down=True):
|
||||
assert channel in (0, 1)
|
||||
|
||||
bitmask = 1 << (channel + 1) & 0b111
|
||||
|
|
@ -101,68 +150,33 @@ def power_down_afe(channel, power_down=True):
|
|||
to_write = reg_contents | value
|
||||
write_to_memory(CTRL_ADDR, to_write)
|
||||
reg_contents = read_from_memory(CTRL_ADDR, 1)[0]
|
||||
print(f"Power Down DAC AFE Ch{channel}: {power_down}")
|
||||
print(f"REG contents: 0b{reg_contents:03b}")
|
||||
|
||||
def set_dac_output(value):
|
||||
value = min(value, 0x3FFF)
|
||||
low_word = value & 0xFF
|
||||
high_word = (value >> 8) & 0x3F
|
||||
|
||||
# Note: DAC HIGH word and LOW word output are not updated
|
||||
# at the same time. On scope, you will see more than one step
|
||||
# of value changed.
|
||||
write_to_memory(CH0_HIGH_WORD_ADDR, high_word)
|
||||
write_to_memory(CH0_LOW_WORD_ADDR, low_word)
|
||||
write_to_memory(CH1_HIGH_WORD_ADDR, high_word)
|
||||
write_to_memory(CH1_LOW_WORD_ADDR, low_word)
|
||||
print(f"DAC output set to: 0x{value:04X}")
|
||||
|
||||
def check_clk_relationship(spi):
|
||||
clkmode_reg = spi_read(spi, 0x14)
|
||||
print(f"CLKMODE reg: 0x{clkmode_reg:02X}")
|
||||
if clkmode_reg & 0b00010000:
|
||||
print("Clock relationship is not found")
|
||||
return False
|
||||
def write_sample(channel, sample):
|
||||
assert channel in (0, 1)
|
||||
if channel == 0:
|
||||
addresses = [CH0_HIGH_WORD_ADDR, CH0_LOW_WORD_ADDR]
|
||||
else:
|
||||
print("Clock relationship is found")
|
||||
return True
|
||||
addresses = [CH1_HIGH_WORD_ADDR, CH1_LOW_WORD_ADDR]
|
||||
|
||||
def configure_ad9117():
|
||||
spi = spidev.SpiDev()
|
||||
spi.open(MAIN_DAC_BUS, MAIN_DAC_DEVICE)
|
||||
spi.max_speed_hz = 5000
|
||||
spi.mode = 0b00 # CPOL = 0 CPHA = 0
|
||||
spi.cshigh = False
|
||||
low_word_value = sample & 0xFF
|
||||
high_word_value = (sample >> 8) & 0x3F
|
||||
values = [high_word_value, low_word_value]
|
||||
for addr, value in zip(addresses, values):
|
||||
write_to_memory(addr, value)
|
||||
|
||||
try:
|
||||
soft_reset(spi)
|
||||
if not check_version(spi):
|
||||
print("Unrecognized DAC version")
|
||||
return False
|
||||
|
||||
power_down_afe(0, True)
|
||||
power_down_afe(1, True)
|
||||
def write_ramp():
|
||||
signal = [i for i in range(16384)]
|
||||
|
||||
configure_dac(spi)
|
||||
check_clk_relationship(spi)
|
||||
dac_self_calibration(spi)
|
||||
|
||||
# Enable DAC outputs
|
||||
spi_write(spi, 0x01, spi_read(spi, 0x01) & ~((1 << 4) | (1 << 3)))
|
||||
|
||||
power_down_afe(0, False)
|
||||
power_down_afe(1, False)
|
||||
manual_override(False)
|
||||
|
||||
print("AD9117 configuration completed successfully")
|
||||
return True
|
||||
|
||||
except Exception as e:
|
||||
print(f"Error configuring AD9117: {e}")
|
||||
return False
|
||||
|
||||
finally:
|
||||
spi.close()
|
||||
for value in signal:
|
||||
write_sample(0, value)
|
||||
|
||||
def main():
|
||||
main_dac_init()
|
||||
power_down(0, False)
|
||||
power_down(1, False)
|
||||
|
||||
if __name__ == "__main__":
|
||||
configure_ad9117()
|
||||
main()
|
||||
|
|
@ -21,7 +21,7 @@ import mmap
|
|||
import os
|
||||
import time
|
||||
|
||||
from pyfastservo.common import (
|
||||
from common import (
|
||||
LED0_BASE_ADDR,
|
||||
LED1_BASE_ADDR,
|
||||
LED2_BASE_ADDR,
|
||||
|
|
|
|||
|
|
@ -17,12 +17,14 @@
|
|||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program. If not, see <https://www.gnu.org/licenses/>.
|
||||
|
||||
from pyfastservo import adc, si5340, dac
|
||||
import adc
|
||||
import si5340
|
||||
import dac
|
||||
|
||||
def main():
|
||||
si5340.configure_si5340()
|
||||
adc.configure_ltc2195()
|
||||
dac.configure_ad9117()
|
||||
adc.main()
|
||||
dac.main()
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
|
|
@ -17,264 +17,102 @@
|
|||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program. If not, see <https://www.gnu.org/licenses/>.
|
||||
|
||||
# Additional Reference:
|
||||
# https://github.com/torvalds/linux/blob/master/drivers/clk/clk-si5341.c
|
||||
|
||||
import time
|
||||
from smbus2 import SMBus
|
||||
|
||||
BUS_NO = 0
|
||||
IC_ADDR = 0x74
|
||||
|
||||
DEVICE_READY = 0x00FE
|
||||
PLL_M_DEN = 0x023B
|
||||
STATUS = 0x000C
|
||||
STATUS_STICKY = 0x0011
|
||||
PAGE_ADDR = 0x1
|
||||
|
||||
STATUS_LOSREF = 0x04
|
||||
STATUS_LOL = 0x08
|
||||
OUT0_MUX_SEL_ADDR = 0x15
|
||||
OUT1_MUX_SEL_ADDR = 0x1A
|
||||
OUT2_MUX_SEL_ADDR = 0x29
|
||||
OUT3_MUX_SEL_ADDR = 0x2E
|
||||
|
||||
OUT2_AMPL_ADDR = 0x28
|
||||
|
||||
OUT3_PDN_ADDR = 0x2B
|
||||
OUT3_FORMAT_ADDR = 0x2C
|
||||
OUT3_AMPL_ADDR = 0x2D
|
||||
|
||||
|
||||
def write_register(bus, address, value):
|
||||
page = address >> 8
|
||||
register = address & 0xFF
|
||||
bus.write_byte_data(IC_ADDR, 0x01, page)
|
||||
try:
|
||||
bus.write_byte_data(IC_ADDR, register, value)
|
||||
except Exception as e:
|
||||
raise Exception(f"Write failed 0x{value:02X} at 0x{address:04X}: {e}")
|
||||
N1_DIVIDER_UPDATE_ADDR = 0x17
|
||||
|
||||
def write_preamble(bus):
|
||||
preamble = [
|
||||
(0x0B24, 0xC0),
|
||||
(0x0B25, 0x00),
|
||||
(0x0502, 0x01),
|
||||
(0x0505, 0x03),
|
||||
(0x0957, 0x17),
|
||||
(0x0B4E, 0x1A),
|
||||
]
|
||||
for address, value in preamble:
|
||||
write_register(bus, address, value)
|
||||
|
||||
def write_postamble(bus):
|
||||
postamble = [
|
||||
(0x001C, 0x01), # Soft reset
|
||||
(0x0B24, 0xC3),
|
||||
(0x0B25, 0x02),
|
||||
]
|
||||
for address, value in postamble:
|
||||
write_register(bus, address, value)
|
||||
|
||||
def wait_device_ready(bus):
|
||||
for _ in range(15):
|
||||
if bus.read_byte_data(IC_ADDR, DEVICE_READY) == 0x0F:
|
||||
return True
|
||||
time.sleep(0.02)
|
||||
return False
|
||||
|
||||
def wait_for_lock(bus):
|
||||
for _ in range(10):
|
||||
status = bus.read_byte_data(IC_ADDR, STATUS)
|
||||
if not (status & (STATUS_LOSREF | STATUS_LOL)):
|
||||
return True
|
||||
time.sleep(0.01)
|
||||
return False
|
||||
|
||||
def check_pll_status(bus):
|
||||
pll_status = bus.read_byte_data(IC_ADDR, 0x0C)
|
||||
pll_locked = not (pll_status & STATUS_LOL)
|
||||
print(f"PLL {'locked' if pll_locked else 'unlocked'}")
|
||||
return pll_locked
|
||||
|
||||
def check_los_status(bus):
|
||||
los_status = bus.read_byte_data(IC_ADDR, 0x0D)
|
||||
xaxb_los = (los_status & 0x10) != 0
|
||||
print(f"XA/XB LOS {'asserted' if xaxb_los else 'deasserted'}")
|
||||
return not xaxb_los
|
||||
data_to_write = 0
|
||||
clk_out_addr = [
|
||||
OUT0_MUX_SEL_ADDR,
|
||||
OUT1_MUX_SEL_ADDR,
|
||||
OUT2_MUX_SEL_ADDR,
|
||||
OUT3_MUX_SEL_ADDR,
|
||||
]
|
||||
|
||||
def configure_si5340():
|
||||
with SMBus(BUS_NO) as bus:
|
||||
if not wait_device_ready(bus):
|
||||
print("Device not ready. Aborting.")
|
||||
return
|
||||
|
||||
# Programming sequence from ClockBuilder Pro, default settings
|
||||
# to initialize system using XTAL input
|
||||
main_config = [
|
||||
(0x0006, 0x00), # TOOL_VERSION
|
||||
(0x0007, 0x00), # Not in datasheet
|
||||
(0x0008, 0x00), # Not in datasheet
|
||||
(0x000B, 0x74), # I2C_ADDR
|
||||
(0x0017, 0xD0), # INT mask (disable interrupts)
|
||||
(0x0018, 0xFF), # INT mask
|
||||
(0x0021, 0x0F), # Select XTAL as input
|
||||
(0x0022, 0x00), # Not in datasheet
|
||||
(0x002B, 0x02), # SPI config
|
||||
(0x002C, 0x20), # LOS enable for XTAL
|
||||
(0x002D, 0x00), # LOS timing
|
||||
(0x002E, 0x00), # LOS trigger (thresholds)
|
||||
(0x002F, 0x00),
|
||||
(0x0030, 0x00),
|
||||
(0x0031, 0x00),
|
||||
(0x0032, 0x00),
|
||||
(0x0033, 0x00),
|
||||
(0x0034, 0x00),
|
||||
(0x0035, 0x00), # LOS trigger (thresholds) end
|
||||
(0x0036, 0x00), # LOS clear (thresholds)
|
||||
(0x0037, 0x00),
|
||||
(0x0038, 0x00),
|
||||
(0x0039, 0x00),
|
||||
(0x003A, 0x00),
|
||||
(0x003B, 0x00),
|
||||
(0x003C, 0x00),
|
||||
(0x003D, 0x00), # LOS clear (thresholds) end
|
||||
(0x0041, 0x00), # LOS0_DIV_SEL
|
||||
(0x0042, 0x00), # LOS1_DIV_SEL
|
||||
(0x0043, 0x00), # LOS2_DIV_SEL
|
||||
(0x0044, 0x00), # LOS3_DIV_SEL
|
||||
(0x009E, 0x00), # LOL_SET_THR
|
||||
(0x0102, 0x01), # Enable outputs
|
||||
(0x013F, 0x00), # OUTX_ALWAYS_ON
|
||||
(0x0140, 0x00), # OUTX_ALWAYS_ON
|
||||
(0x0141, 0x40), # OUT_DIS_LOL_MSK, OUT_DIS_MSK_LOS_PFD
|
||||
(0x0202, 0x00), # XAXB_FREQ_OFFSET (=0)
|
||||
bus.write_byte_data(IC_ADDR, PAGE_ADDR, 0x0) # setting page to page 0
|
||||
|
||||
# PLL Configuration
|
||||
(0x0235, 0x00), # M_NUM
|
||||
(0x0236, 0x00),
|
||||
(0x0237, 0x00),
|
||||
(0x0238, 0x80),
|
||||
(0x0239, 0x89),
|
||||
(0x023A, 0x00),
|
||||
(0x023B, 0x00), # M_DEN
|
||||
(0x023C, 0x00),
|
||||
(0x023D, 0x00),
|
||||
(0x023E, 0x80),
|
||||
# read device id
|
||||
low_word = bus.read_byte_data(IC_ADDR, 0x2)
|
||||
high_word = bus.read_byte_data(IC_ADDR, 0x3)
|
||||
|
||||
# Synthesizer configuration
|
||||
(0x0302, 0x00), # N0_NUM
|
||||
(0x0303, 0x00),
|
||||
(0x0304, 0x00),
|
||||
(0x0305, 0x00),
|
||||
(0x0306, 0x21),
|
||||
(0x0307, 0x00),
|
||||
(0x0308, 0x00), # N0_DEN
|
||||
(0x0309, 0x00),
|
||||
(0x030A, 0x00),
|
||||
(0x030B, 0x80),
|
||||
(0x030C, 0x01), # N0_UPDATE
|
||||
print(f"DEV ID: 0x{high_word:2x}{low_word:2x}")
|
||||
|
||||
# N1 Configuration (1:1 ratio)
|
||||
(0x030D, 0x00), # N1_NUM
|
||||
(0x030E, 0x00),
|
||||
(0x030F, 0x00),
|
||||
(0x0310, 0x00),
|
||||
(0x0311, 0x00),
|
||||
(0x0312, 0x01),
|
||||
(0x0313, 0x00), # N1_DEN
|
||||
(0x0314, 0x00),
|
||||
(0x0315, 0x00),
|
||||
(0x0316, 0x01),
|
||||
(0x0317, 0x01), # N1_UPDATE
|
||||
data_to_write = 0x1
|
||||
bus.write_byte_data(
|
||||
IC_ADDR, PAGE_ADDR, data_to_write
|
||||
) # change to page 1 for output settings
|
||||
|
||||
# N2 Configuration (1:1 ratio)
|
||||
(0x0318, 0x00), # N2_NUM
|
||||
(0x0319, 0x00),
|
||||
(0x031A, 0x00),
|
||||
(0x031B, 0x00),
|
||||
(0x031C, 0x00),
|
||||
(0x031D, 0x01),
|
||||
(0x031E, 0x00), # N2_DEN
|
||||
(0x031F, 0x00),
|
||||
(0x0320, 0x00),
|
||||
(0x0321, 0x01),
|
||||
(0x0322, 0x01), # N2_UPDATE
|
||||
readback = bus.read_byte_data(IC_ADDR, PAGE_ADDR)
|
||||
if data_to_write != readback:
|
||||
raise ValueError(f"Failed to set page.")
|
||||
|
||||
# N3 Configuration (1:1 ratio)
|
||||
(0x0323, 0x00), # N3_NUM
|
||||
(0x0324, 0x00),
|
||||
(0x0325, 0x00),
|
||||
(0x0326, 0x00),
|
||||
(0x0327, 0x00),
|
||||
(0x0328, 0x01),
|
||||
(0x0329, 0x00), # N3_DEN
|
||||
(0x032A, 0x00),
|
||||
(0x032B, 0x00),
|
||||
(0x032C, 0x01),
|
||||
(0x032D, 0x01), # N3_UPDATE
|
||||
for addr in clk_out_addr:
|
||||
bus.write_byte_data(IC_ADDR, addr, 1) # set source to N1
|
||||
|
||||
# Output configuration
|
||||
(0x0112, 0x06), # OUT0 config
|
||||
(0x0113, 0x09), # OUT0 format
|
||||
(0x0114, 0x3B), # OUT0 CM/AMPL
|
||||
(0x0115, 0x28), # OUT0 MUX_SEL
|
||||
bus.write_byte_data(IC_ADDR, OUT2_AMPL_ADDR, 13)
|
||||
readback = bus.read_byte_data(IC_ADDR, OUT2_AMPL_ADDR)
|
||||
# if data_to_write != readback:
|
||||
# raise ValueError(f"Problematic read: {readback}.")
|
||||
|
||||
(0x0117, 0x06), # OUT1 config
|
||||
(0x0118, 0x09), # OUT1 format
|
||||
(0x0119, 0x3B), # OUT1 CM/AMPL
|
||||
(0x011A, 0x28), # OUT1 MUX_SEL
|
||||
bus.write_byte_data(IC_ADDR, OUT2_AMPL_ADDR, 0x6B) # setting OUT2 to LVDS25
|
||||
|
||||
(0x0126, 0x06), # OUT2 config
|
||||
(0x0127, 0x09), # OUT2 format
|
||||
(0x0128, 0x3B), # OUT2 CM/AMPL
|
||||
(0x0129, 0x28), # OUT2 MUX_SEL
|
||||
bus.write_byte_data(IC_ADDR, OUT3_FORMAT_ADDR, 0xCC) # SETTING out3 to LVCMOS 18
|
||||
# bus.write_byte_data(IC_ADDR, 0x2E, 0x09) # SETTING out3 to LVCMOS 33
|
||||
|
||||
(0x012B, 0x06), # OUT3 config
|
||||
(0x012C, 0xCC), # OUT3 format
|
||||
(0x012D, 0x00), # OUT3 CM/AMPL
|
||||
(0x012E, 0x58), # OUT3 MUX_SEL
|
||||
readback = bus.read_byte_data(IC_ADDR, OUT3_PDN_ADDR)
|
||||
print(f"Si5340 OUTx_PDN CLK3: 0x{readback}")
|
||||
|
||||
# Miscellaneous configuration
|
||||
(0x090E, 0x02), # XAXB_EXTCLK_EN=0 XAXB_PDNB=1 (use XTAL)
|
||||
(0x091C, 0x04), # ZDM_EN=4 (Normal mode)
|
||||
(0x0943, 0x00), # IO_VDD_SEL
|
||||
(0x0949, 0x00), # IN_EN (disable input clocks)
|
||||
(0x094A, 0x00), # INx_TO_PFD_EN (disabled)
|
||||
(0x094E, 0x49), # REFCLK_HYS_SEL (set by CBPro)
|
||||
(0x094F, 0x02), # Not in datasheet
|
||||
(0x095E, 0x00), # M_INTEGER (set by CBPro)
|
||||
(0x0A02, 0x00), # N_ADD_0P5 (set by CBPro)
|
||||
(0x0A03, 0x01), # N_CLK_TO_OUTX_EN
|
||||
(0x0A04, 0x01), # N_PIBYP
|
||||
(0x0A05, 0x01), # N_PDNB
|
||||
(0x0A14, 0x00), # N0_HIGH_FREQ (set by CBPro)
|
||||
(0x0A1A, 0x00), # N1_HIGH_FREQ (set by CBPro)
|
||||
(0x0A20, 0x00), # N2_HIGH_FREQ (set by CBPro)
|
||||
(0x0A26, 0x00), # N3_HIGH_FREQ (set by CBPro)
|
||||
(0x0B44, 0x0F), # PDIV_ENB (set by CBPro)
|
||||
(0x0B4A, 0x0E), # N_CLK_DIS
|
||||
(0x0B57, 0x0E), # VCO_RESET_CALCODE (set by CBPro)
|
||||
(0x0B58, 0x01), # VCO_RESET_CALCODE (set by CBPro)
|
||||
]
|
||||
readback = bus.read_byte_data(IC_ADDR, OUT3_FORMAT_ADDR)
|
||||
print(f"Si5340 OUTx_FORMAT CLK3: 0x{readback}")
|
||||
|
||||
write_preamble(bus)
|
||||
readback = bus.read_byte_data(IC_ADDR, OUT3_AMPL_ADDR)
|
||||
print(f"Si5340 OUTx_AMPL CLK3: 0x{readback}")
|
||||
|
||||
time.sleep(0.3)
|
||||
readback = bus.read_byte_data(IC_ADDR, OUT3_MUX_SEL_ADDR)
|
||||
print(f"Si5340 OUTx_CM CLK3: 0x{readback}")
|
||||
|
||||
print("Writing main configuration...")
|
||||
for address, value in main_config:
|
||||
write_register(bus, address, value)
|
||||
print("Main configuration written")
|
||||
bus.write_byte_data(
|
||||
IC_ADDR, PAGE_ADDR, 0x3
|
||||
) # setting page to 3 to change dividers values
|
||||
|
||||
write_postamble(bus)
|
||||
n1_numerator = [0x0, 0x0, 0x0, 0x60, 0x22, 0x0]
|
||||
n1_numerator_10M = [0x0, 0x0, 0x0, 0xC0, 0x57, 0x1]
|
||||
n1_num_addr = [0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12]
|
||||
n1_denom_addr = [0x13, 0x14, 0x15, 0x16]
|
||||
for addr, value in zip(n1_num_addr, n1_numerator):
|
||||
bus.write_byte_data(IC_ADDR, addr, value)
|
||||
|
||||
if not wait_for_lock(bus):
|
||||
print("Error waiting for input clock or PLL lock")
|
||||
else:
|
||||
print("Input clock present and PLL locked")
|
||||
bus.write_byte_data(IC_ADDR, N1_DIVIDER_UPDATE_ADDR, 1)
|
||||
|
||||
bus.write_byte_data(IC_ADDR, STATUS_STICKY, 0)
|
||||
for addr in n1_num_addr:
|
||||
readback = bus.read_byte_data(IC_ADDR, addr)
|
||||
print(f"Numerator buffer: 0x{readback:02x}")
|
||||
|
||||
# Final status check
|
||||
pll_locked = check_pll_status(bus)
|
||||
xaxb_signal_present = check_los_status(bus)
|
||||
for addr in n1_denom_addr:
|
||||
readback = bus.read_byte_data(IC_ADDR, addr)
|
||||
print(f"Denominator buffer: 0x{readback:02x}")
|
||||
|
||||
if not pll_locked:
|
||||
print("Error: PLL is not locked")
|
||||
elif not xaxb_signal_present:
|
||||
print("Error: XA/XB signal is lost")
|
||||
else:
|
||||
print("Si5340 configuration completed successfully")
|
||||
bus.write_byte_data(IC_ADDR, PAGE_ADDR, 0x0) # setting page to page 0
|
||||
|
||||
if __name__ == "__main__":
|
||||
configure_si5340()
|
||||
22
flake.lock
22
flake.lock
|
|
@ -18,16 +18,16 @@
|
|||
},
|
||||
"nixpkgs": {
|
||||
"locked": {
|
||||
"lastModified": 1723938990,
|
||||
"narHash": "sha256-9tUadhnZQbWIiYVXH8ncfGXGvkNq3Hag4RCBEMUk7MI=",
|
||||
"lastModified": 1709237383,
|
||||
"narHash": "sha256-cy6ArO4k5qTx+l5o+0mL9f5fa86tYUX3ozE1S+Txlds=",
|
||||
"owner": "NixOS",
|
||||
"repo": "nixpkgs",
|
||||
"rev": "c42fcfbdfeae23e68fc520f9182dde9f38ad1890",
|
||||
"rev": "1536926ef5621b09bba54035ae2bb6d806d72ac8",
|
||||
"type": "github"
|
||||
},
|
||||
"original": {
|
||||
"owner": "NixOS",
|
||||
"ref": "nixos-24.05",
|
||||
"ref": "nixos-unstable",
|
||||
"repo": "nixpkgs",
|
||||
"type": "github"
|
||||
}
|
||||
|
|
@ -64,11 +64,11 @@
|
|||
"src-migen": {
|
||||
"flake": false,
|
||||
"locked": {
|
||||
"lastModified": 1721561053,
|
||||
"narHash": "sha256-z3LRhNmKZrjr6rFD0yxtccSa/SWvFIYmb+G/D5d2Jd8=",
|
||||
"lastModified": 1702942348,
|
||||
"narHash": "sha256-gKIfHZxsv+jcgDFRW9mPqmwqbZXuRvXefkZcSFjOGHw=",
|
||||
"owner": "m-labs",
|
||||
"repo": "migen",
|
||||
"rev": "9279e8623f8433bc4f23ac51e5e2331bfe544417",
|
||||
"rev": "50934ad10a87ade47219b796535978b9bdf24023",
|
||||
"type": "github"
|
||||
},
|
||||
"original": {
|
||||
|
|
@ -80,11 +80,11 @@
|
|||
"src-misoc": {
|
||||
"flake": false,
|
||||
"locked": {
|
||||
"lastModified": 1715647536,
|
||||
"narHash": "sha256-q+USDcaKHABwW56Jzq8u94iGPWlyLXMyVt0j/Gyg+IE=",
|
||||
"lastModified": 1699352904,
|
||||
"narHash": "sha256-SglyTmXOPv8jJOjwAjJrj/WhAkItQfUbvKfUqrynwRg=",
|
||||
"ref": "refs/heads/master",
|
||||
"rev": "fea9de558c730bc394a5936094ae95bb9d6fa726",
|
||||
"revCount": 2455,
|
||||
"rev": "a53859f2167c31ab5225b6c09f30cf05527b94f4",
|
||||
"revCount": 2452,
|
||||
"submodules": true,
|
||||
"type": "git",
|
||||
"url": "https://github.com/m-labs/misoc.git"
|
||||
|
|
|
|||
67
flake.nix
67
flake.nix
|
|
@ -1,7 +1,7 @@
|
|||
{
|
||||
description = "Firmware for Sinara Fast-Servo based on Not-OS and Linien";
|
||||
|
||||
inputs.nixpkgs.url = github:NixOS/nixpkgs/nixos-24.05;
|
||||
inputs.nixpkgs.url = github:NixOS/nixpkgs/nixos-unstable;
|
||||
inputs.not-os.url = github:cleverca22/not-os;
|
||||
inputs.not-os.inputs.nixpkgs.follows = "nixpkgs";
|
||||
|
||||
|
|
@ -110,23 +110,13 @@
|
|||
rev = "v${version}";
|
||||
hash = "sha256-43TTlpJ5SMAjQM71bNVvrWQyciRXM3zpuA/Dw41AEgU=";
|
||||
};
|
||||
patches = ./fast-servo/linien-pyrp3-monitor.patch;
|
||||
nativeBuildInputs = with pkgs-armv7l.python3Packages; [
|
||||
setuptools wheel setuptools-scm
|
||||
] ++ (with pkgs-armv7l; [ gcc gnumake ]);
|
||||
nativeBuildInputs = with pkgs-armv7l.python3Packages; [ setuptools wheel setuptools-scm ];
|
||||
propagatedBuildInputs = with pkgs-armv7l.python3Packages; [
|
||||
myhdl
|
||||
rpyc4
|
||||
cached-property
|
||||
numpy
|
||||
];
|
||||
postInstall = ''
|
||||
cp monitor/libmonitor.so $out/lib
|
||||
'';
|
||||
postFixup = ''
|
||||
substituteInPlace $out/${pkgs.python3.sitePackages}/pyrp3/raw_memory.py \
|
||||
--replace "libmonitor.so" "$out/lib/libmonitor.so"
|
||||
'';
|
||||
};
|
||||
|
||||
linien-server = pkgs-armv7l.python3Packages.buildPythonPackage rec {
|
||||
|
|
@ -135,7 +125,6 @@
|
|||
inherit (pkgs.python3Packages.linien-common) src version;
|
||||
sourceRoot = "source/linien-server";
|
||||
postPatch = ''
|
||||
cp ${fast-servo-gateware}/csrmap.py linien_server/csrmap.py
|
||||
substituteInPlace linien_server/acquisition.py \
|
||||
--replace " start_nginx()" "" \
|
||||
--replace " stop_nginx()" "" \
|
||||
|
|
@ -186,33 +175,11 @@
|
|||
mkdir -p $out $out/nix-support
|
||||
cp gateware/build/top.bit $out
|
||||
cp linien-server/linien_server/gateware.bin $out
|
||||
cp linien-server/linien_server/csrmap.py $out
|
||||
echo file binary-dist $out/top.bit >> $out/nix-support/hydra-build-products
|
||||
echo file binary-dist $out/gateware.bin >> $out/nix-support/hydra-build-products
|
||||
'';
|
||||
};
|
||||
|
||||
pyfastservo = pkgs-armv7l.python3Packages.buildPythonPackage rec {
|
||||
name = "pyfastservo";
|
||||
src = ./fast-servo;
|
||||
preBuild = ''
|
||||
cat > setup.py << EOF
|
||||
from setuptools import setup
|
||||
|
||||
setup(
|
||||
name="pyfastservo",
|
||||
packages=["pyfastservo"],
|
||||
install_requires=["spidev", "smbus2"],
|
||||
entry_points = {"console_scripts": ["fp_leds=pyfastservo.fp_leds:main"]},
|
||||
)
|
||||
EOF
|
||||
'';
|
||||
propagatedBuildInputs = with pkgs-armv7l.python3Packages; [
|
||||
spidev
|
||||
smbus2
|
||||
];
|
||||
};
|
||||
|
||||
mkbootimage = pkgs.stdenv.mkDerivation {
|
||||
pname = "mkbootimage";
|
||||
version = "2.3dev";
|
||||
|
|
@ -242,25 +209,8 @@
|
|||
extraModules = [
|
||||
"${patched-not-os}/zynq_image.nix"
|
||||
] ++ pkgs.lib.optionals (board == "fast-servo") [
|
||||
({ config, pkgs, lib, ... }: {
|
||||
environment.systemPackages = [
|
||||
linien-server
|
||||
(pkgs.python3.withPackages(ps: [ pyfastservo ]))
|
||||
];
|
||||
boot.postBootCommands = lib.mkAfter ''
|
||||
|
||||
# Program the FPGA
|
||||
set +x
|
||||
echo "Loading bitstream into SRAM..."
|
||||
echo 0 > /sys/class/fpga_manager/fpga0/flags
|
||||
mkdir -p /lib/firmware
|
||||
cp ${fast-servo-gateware}/gateware.bin /lib/firmware/
|
||||
echo gateware.bin > /sys/class/fpga_manager/fpga0/firmware
|
||||
|
||||
# Run device init scripts
|
||||
echo "Initializing clock generator, ADC, and DAC..."
|
||||
python3 -m pyfastservo.initialize
|
||||
'';
|
||||
({ config, pkgs, ... }: {
|
||||
environment.systemPackages = [ linien-server ];
|
||||
})];
|
||||
system = "x86_64-linux";
|
||||
inherit crossSystem;
|
||||
|
|
@ -307,7 +257,6 @@
|
|||
};
|
||||
|
||||
u-boot = (pkgs-armv7l.buildUBoot {
|
||||
name = "${board}-u-boot";
|
||||
defconfig = "xilinx_zynq_virt_defconfig";
|
||||
patches = [] ++ pkgs.lib.optional (board == "fast-servo") ./fast-servo/u-boot.patch;
|
||||
preConfigure = ''
|
||||
|
|
@ -361,7 +310,7 @@
|
|||
echo file binary-dist $out/boot.bin >> $out/nix-support/hydra-build-products
|
||||
'';
|
||||
|
||||
dtb = pkgs.runCommand "${board}-dtb"
|
||||
dtb = pkgs.runCommand "dtb"
|
||||
{
|
||||
buildInputs = [ pkgs.gcc pkgs.dtc ];
|
||||
}
|
||||
|
|
@ -388,7 +337,7 @@
|
|||
firmwareSize = 30;
|
||||
firmwarePartitionOffset = 8;
|
||||
in pkgs.stdenv.mkDerivation {
|
||||
name = "${board}-sd-image";
|
||||
name = "sd-image";
|
||||
nativeBuildInputs = with pkgs; [ dosfstools mtools libfaketime util-linux parted ];
|
||||
buildCommand = ''
|
||||
mkdir -p $out/nix-support $out/sd-image
|
||||
|
|
@ -438,7 +387,7 @@
|
|||
BASE=$(realpath $(dirname $0))
|
||||
|
||||
qemu-img convert -O qcow2 -f raw -o preallocation=metadata $BASE/sd-image.img $IMGDIR/sd-sparse.qcow2
|
||||
qemu-img create -F qcow2 -f qcow2 -b $IMGDIR/sd-sparse.qcow2 $IMGDIR/sd-overlay.qcow2 2G
|
||||
qemu-img create -F qcow2 -f qcow2 -b $IMGDIR/sd-sparse.qcow2 $IMGDIR/sd-overlay.qcow2 1G
|
||||
|
||||
# Some command arguments are based from samples in Xilinx QEMU User Documentation
|
||||
# See: https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/821854273/Running+Bare+Metal+Applications+on+QEMU
|
||||
|
|
@ -453,7 +402,7 @@
|
|||
|
||||
rm -rf $IMGDIR
|
||||
'';
|
||||
in pkgs.runCommand "${board}-qemu" {
|
||||
in pkgs.runCommand "not-os-qemu" {
|
||||
inherit qemuScript;
|
||||
passAsFile = [ "qemuScript" ];
|
||||
preferLocalBuild = true;
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
diff --git a/configuration.nix b/configuration.nix
|
||||
index 010c487..2d08009 100644
|
||||
index 010c487..e1e85ba 100644
|
||||
--- a/configuration.nix
|
||||
+++ b/configuration.nix
|
||||
@@ -1,4 +1,4 @@
|
||||
|
|
@ -8,7 +8,7 @@ index 010c487..2d08009 100644
|
|||
|
||||
{
|
||||
imports = [ ./qemu.nix ];
|
||||
@@ -7,10 +7,16 @@
|
||||
@@ -7,10 +7,15 @@
|
||||
environment.etc = {
|
||||
"ssh/authorized_keys.d/root" = {
|
||||
text = ''
|
||||
|
|
@ -18,7 +18,6 @@ index 010c487..2d08009 100644
|
|||
+ ecdsa-sha2-nistp384 AAAAE2VjZHNhLXNoYTItbmlzdHAzODQAAAAIbmlzdHAzODQAAABhBNdIiLvP2hmDUFyyE0oLOIXrjrMdWWpBV9/gPR5m4AiARx4JkufIDZzmptdYQ5FhJORJ4lluPqp7dAmahoSwg4lv9Di0iNQpHMJvNGZLHYKM1H1FWCCFIEDJ8bD4SVfrDg== root
|
||||
+ ecdsa-sha2-nistp384 AAAAE2VjZHNhLXNoYTItbmlzdHAzODQAAAAIbmlzdHAzODQAAABhBF/YybP+fQ0J+bNqM5Vgx5vDmVqVWsgUdF1moUxghv7d73GZAFaM6IFBdrXTAa33AwnWwDPMrTgP1V6SXBkb3ciJo/lD1urJGbydbSI5Ksq9d59wvOeANvyWYrQw6+eqTQ== sb
|
||||
+ ecdsa-sha2-nistp384 AAAAE2VjZHNhLXNoYTItbmlzdHAzODQAAAAIbmlzdHAzODQAAABhBFkmOCQ3BQh3qUjLtfdqyeBsx8rkk/QYlzB0TMrnfn6waLN6yKfPC3WVFv4zN5kNKb/OayvqDa+zfkKe85e/oIPQQKflF7GrCHdssz33DCnW90cz532E6iqG1pjeZjID2A== flo
|
||||
+ ssh-ed25519 AAAAC3NzaC1lZDI1NTE5AAAAICAranL376soiSJ0kxdYNrwElcaZPW1heLFjs8Y7n0jT linuswck
|
||||
'';
|
||||
mode = "0444";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
diff --git a/base.nix b/base.nix
|
||||
index 7eaee32..9aa338e 100644
|
||||
index 7eaee32..3a2a0a9 100644
|
||||
--- a/base.nix
|
||||
+++ b/base.nix
|
||||
@@ -27,6 +27,11 @@ with lib;
|
||||
|
|
@ -14,12 +14,9 @@ index 7eaee32..9aa338e 100644
|
|||
not-os.simpleStaticIp = mkOption {
|
||||
type = types.bool;
|
||||
default = false;
|
||||
@@ -84,17 +89,25 @@ with lib;
|
||||
};
|
||||
environment.etc = {
|
||||
@@ -86,15 +91,25 @@ with lib;
|
||||
"nix/nix.conf".source = pkgs.runCommand "nix.conf" {} ''
|
||||
- extraPaths=$(for i in $(cat ${pkgs.writeReferencesToFile pkgs.runtimeShell}); do if test -d $i; then echo $i; fi; done)
|
||||
+ extraPaths=$(for i in $(cat ${pkgs.writeClosure [ pkgs.bash ]}); do if test -d $i; then echo $i; fi; done)
|
||||
extraPaths=$(for i in $(cat ${pkgs.writeReferencesToFile pkgs.runtimeShell}); do if test -d $i; then echo $i; fi; done)
|
||||
cat > $out << EOF
|
||||
- build-use-sandbox = true
|
||||
+ auto-optimise-store = true
|
||||
|
|
@ -31,6 +28,8 @@ index 7eaee32..9aa338e 100644
|
|||
+ extra-sandbox-paths = /bin/sh=${pkgs.runtimeShell} $(echo $extraPaths)
|
||||
+ max-jobs = auto
|
||||
+ sandbox = true
|
||||
+ substituters = https://cache.armv7l.xyz
|
||||
+ trusted-public-keys = cache.armv7l.xyz-1:kBY/eGnBAYiqYfg0fy0inWhshUo+pGFM3Pj7kIkmlBk=
|
||||
+ trusted-users = root
|
||||
EOF
|
||||
'';
|
||||
|
|
@ -152,7 +151,7 @@ index c61f9d6..fbdf0fd 100644
|
|||
};
|
||||
}
|
||||
diff --git a/zynq_image.nix b/zynq_image.nix
|
||||
index 3fa23ab..069fe89 100644
|
||||
index 3fa23ab..9d1621e 100644
|
||||
--- a/zynq_image.nix
|
||||
+++ b/zynq_image.nix
|
||||
@@ -1,66 +1,89 @@
|
||||
|
|
@ -164,7 +163,7 @@ index 3fa23ab..069fe89 100644
|
|||
- # dont use overlays for the qemu, it causes a lot of wasted time on recompiles
|
||||
- x86pkgs = import pkgs.path { system = "x86_64-linux"; };
|
||||
- customKernel = pkgs.linux.override {
|
||||
+ customKernel = (pkgs.linux_6_6.override {
|
||||
+ customKernel = (pkgs.linux.override {
|
||||
extraConfig = ''
|
||||
OVERLAY_FS y
|
||||
+ MEDIA_SUPPORT n
|
||||
|
|
@ -250,7 +249,7 @@ index 3fa23ab..069fe89 100644
|
|||
- environment.etc."service/getty/run".source = pkgs.writeShellScript "getty" ''
|
||||
- agetty ttyPS0 115200
|
||||
+ environment = {
|
||||
+ systemPackages = with pkgs; [ inetutils wget gnugrep nano vim ];
|
||||
+ systemPackages = with pkgs; [ inetutils wget nano ];
|
||||
+ etc = {
|
||||
+ "service/getty/run".source = pkgs.writeShellScript "getty" ''
|
||||
+ hostname ${config.networking.hostName}
|
||||
|
|
|
|||
|
|
@ -394,10 +394,10 @@ index 0000000..53c5349
|
|||
\ No newline at end of file
|
||||
diff --git a/xilinx-fpga-manager.patch b/xilinx-fpga-manager.patch
|
||||
new file mode 100644
|
||||
index 0000000..33daffe
|
||||
index 0000000..59aa585
|
||||
--- /dev/null
|
||||
+++ b/xilinx-fpga-manager.patch
|
||||
@@ -0,0 +1,676 @@
|
||||
@@ -0,0 +1,663 @@
|
||||
+# Enable user-space interface for PL programming via Linux FPGA manager
|
||||
+# diff cherry-picked from Xilinx/linux-xilinx/tree/xlnx_rebase_v6.6_LTS
|
||||
+# commit IDs: e61c0a9, 0a38712, dc67651, 89a24e3, 8d224b1, 2a9c05f, 4e94580
|
||||
|
|
@ -425,7 +425,7 @@ index 0000000..33daffe
|
|||
+ tristate "Altera SOCFPGA FPGA Manager"
|
||||
+ depends on ARCH_INTEL_SOCFPGA || COMPILE_TEST
|
||||
+diff --git a/drivers/fpga/fpga-mgr.c b/drivers/fpga/fpga-mgr.c
|
||||
+index 0f4035b089a2..3aa9f5f041f6 100644
|
||||
+index 06651389c592..6e8c45974f28 100644
|
||||
+--- a/drivers/fpga/fpga-mgr.c
|
||||
++++ b/drivers/fpga/fpga-mgr.c
|
||||
+@@ -8,6 +8,9 @@
|
||||
|
|
@ -673,7 +673,7 @@ index 0000000..33daffe
|
|||
+ NULL,
|
||||
+ };
|
||||
+ ATTRIBUTE_GROUPS(fpga_mgr);
|
||||
+@@ -739,6 +871,106 @@ void fpga_mgr_put(struct fpga_manager *mgr)
|
||||
+@@ -732,6 +864,106 @@ void fpga_mgr_put(struct fpga_manager *mgr)
|
||||
+ }
|
||||
+ EXPORT_SYMBOL_GPL(fpga_mgr_put);
|
||||
+
|
||||
|
|
@ -780,8 +780,8 @@ index 0000000..33daffe
|
|||
+ /**
|
||||
+ * fpga_mgr_lock - Lock FPGA manager for exclusive use
|
||||
+ * @mgr: fpga manager
|
||||
+@@ -788,6 +1020,9 @@ __fpga_mgr_register_full(struct device *parent, const struct fpga_manager_info *
|
||||
+ struct module *owner)
|
||||
+@@ -779,6 +1011,9 @@ struct fpga_manager *
|
||||
+ fpga_mgr_register_full(struct device *parent, const struct fpga_manager_info *info)
|
||||
+ {
|
||||
+ const struct fpga_manager_ops *mops = info->mops;
|
||||
++#ifdef CONFIG_FPGA_MGR_DEBUG_FS
|
||||
|
|
@ -790,7 +790,7 @@ index 0000000..33daffe
|
|||
+ struct fpga_manager *mgr;
|
||||
+ int id, ret;
|
||||
+
|
||||
+@@ -826,10 +1061,28 @@ __fpga_mgr_register_full(struct device *parent, const struct fpga_manager_info *
|
||||
+@@ -815,10 +1050,28 @@ fpga_mgr_register_full(struct device *parent, const struct fpga_manager_info *in
|
||||
+ mgr->dev.of_node = parent->of_node;
|
||||
+ mgr->dev.id = id;
|
||||
+
|
||||
|
|
@ -819,7 +819,7 @@ index 0000000..33daffe
|
|||
+ /*
|
||||
+ * Initialize framework state by requesting low level driver read state
|
||||
+ * from device. FPGA may be in reset mode or may have been programmed
|
||||
+@@ -843,6 +1096,28 @@ __fpga_mgr_register_full(struct device *parent, const struct fpga_manager_info *
|
||||
+@@ -832,6 +1085,28 @@ fpga_mgr_register_full(struct device *parent, const struct fpga_manager_info *in
|
||||
+ return ERR_PTR(ret);
|
||||
+ }
|
||||
+
|
||||
|
|
@ -848,7 +848,7 @@ index 0000000..33daffe
|
|||
+ return mgr;
|
||||
+
|
||||
+ error_device:
|
||||
+@@ -894,6 +1169,10 @@ void fpga_mgr_unregister(struct fpga_manager *mgr)
|
||||
+@@ -882,6 +1157,10 @@ void fpga_mgr_unregister(struct fpga_manager *mgr)
|
||||
+ {
|
||||
+ dev_info(&mgr->dev, "%s %s\n", __func__, mgr->name);
|
||||
+
|
||||
|
|
@ -881,10 +881,10 @@ index 0000000..33daffe
|
|||
+ &firmware_name)) {
|
||||
+ info->firmware_name = devm_kstrdup(dev, firmware_name,
|
||||
+diff --git a/drivers/fpga/zynqmp-fpga.c b/drivers/fpga/zynqmp-fpga.c
|
||||
+index f3434e2c487b..d2434ed85eff 100644
|
||||
+index f3434e2c487b..db923746cac5 100644
|
||||
+--- a/drivers/fpga/zynqmp-fpga.c
|
||||
++++ b/drivers/fpga/zynqmp-fpga.c
|
||||
+@@ -43,25 +43,47 @@ static int zynqmp_fpga_ops_write(struct fpga_manager *mgr,
|
||||
+@@ -43,25 +43,42 @@ static int zynqmp_fpga_ops_write(struct fpga_manager *mgr,
|
||||
+ struct zynqmp_fpga_priv *priv;
|
||||
+ dma_addr_t dma_addr;
|
||||
+ u32 eemi_flags = 0;
|
||||
|
|
@ -915,11 +915,6 @@ index 0000000..33daffe
|
|||
++
|
||||
+ wmb(); /* ensure all writes are done before initiate FW call */
|
||||
+
|
||||
++ if (priv->flags & FPGA_MGR_DDR_MEM_AUTH_BITSTREAM)
|
||||
++ eemi_flags |= XILINX_ZYNQMP_PM_FPGA_AUTHENTICATION_DDR;
|
||||
++ else if (priv->flags & FPGA_MGR_SECURE_MEM_AUTH_BITSTREAM)
|
||||
++ eemi_flags |= XILINX_ZYNQMP_PM_FPGA_AUTHENTICATION_OCM;
|
||||
++
|
||||
+ if (priv->flags & FPGA_MGR_PARTIAL_RECONFIG)
|
||||
+ eemi_flags |= XILINX_ZYNQMP_PM_FPGA_PARTIAL;
|
||||
+
|
||||
|
|
@ -936,22 +931,20 @@ index 0000000..33daffe
|
|||
+ return ret;
|
||||
+ }
|
||||
+diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
|
||||
+index e8b12ec8b060..ffd2dfdb6abd 100644
|
||||
+index 9dda7d9898ff..edaf77160746 100644
|
||||
+--- a/include/linux/firmware/xlnx-zynqmp.h
|
||||
++++ b/include/linux/firmware/xlnx-zynqmp.h
|
||||
+@@ -83,6 +83,10 @@
|
||||
+@@ -70,6 +70,8 @@
|
||||
+ */
|
||||
+ #define XILINX_ZYNQMP_PM_FPGA_FULL 0x0U
|
||||
+ #define XILINX_ZYNQMP_PM_FPGA_PARTIAL BIT(0)
|
||||
++#define XILINX_ZYNQMP_PM_FPGA_AUTHENTICATION_DDR BIT(1)
|
||||
++#define XILINX_ZYNQMP_PM_FPGA_AUTHENTICATION_OCM BIT(2)
|
||||
++#define XILINX_ZYNQMP_PM_FPGA_ENCRYPTION_USERKEY BIT(3)
|
||||
++#define XILINX_ZYNQMP_PM_FPGA_ENCRYPTION_DEVKEY BIT(4)
|
||||
+
|
||||
+ /* FPGA Status Reg */
|
||||
+ #define XILINX_ZYNQMP_PM_FPGA_CONFIG_STAT_OFFSET 7U
|
||||
+diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h
|
||||
+index 0d4fe068f3d8..f884d268c974 100644
|
||||
+index 54f63459efd6..c96a4405f909 100644
|
||||
+--- a/include/linux/fpga/fpga-mgr.h
|
||||
++++ b/include/linux/fpga/fpga-mgr.h
|
||||
+@@ -9,8 +9,11 @@
|
||||
|
|
@ -966,7 +959,7 @@ index 0000000..33daffe
|
|||
+ struct fpga_manager;
|
||||
+ struct sg_table;
|
||||
+
|
||||
+@@ -66,17 +69,29 @@ enum fpga_mgr_states {
|
||||
+@@ -66,17 +69,25 @@ enum fpga_mgr_states {
|
||||
+ *
|
||||
+ * %FPGA_MGR_EXTERNAL_CONFIG: FPGA has been configured prior to Linux booting
|
||||
+ *
|
||||
|
|
@ -980,10 +973,6 @@ index 0000000..33daffe
|
|||
++ *
|
||||
++ * %FPGA_MGR_USERKEY_ENCRYPTED_BITSTREAM: indicates bitstream is encrypted with
|
||||
++ * user key
|
||||
++ * %FPGA_MGR_DDR_MEM_AUTH_BITSTREAM: do bitstream authentication using DDR
|
||||
++ * memory if supported
|
||||
++ * %FPGA_MGR_SECURE_MEM_AUTH_BITSTREAM: do bitstream authentication using secure
|
||||
++ * memory if supported
|
||||
+ */
|
||||
+ #define FPGA_MGR_PARTIAL_RECONFIG BIT(0)
|
||||
+ #define FPGA_MGR_EXTERNAL_CONFIG BIT(1)
|
||||
|
|
@ -997,7 +986,7 @@ index 0000000..33daffe
|
|||
+
|
||||
+ /**
|
||||
+ * struct fpga_image_info - information specific to an FPGA image
|
||||
+@@ -86,6 +101,7 @@ enum fpga_mgr_states {
|
||||
+@@ -86,6 +97,7 @@ enum fpga_mgr_states {
|
||||
+ * @config_complete_timeout_us: maximum time for FPGA to switch to operating
|
||||
+ * status in the write_complete op.
|
||||
+ * @firmware_name: name of FPGA image firmware file
|
||||
|
|
@ -1005,7 +994,7 @@ index 0000000..33daffe
|
|||
+ * @sgt: scatter/gather table containing FPGA image
|
||||
+ * @buf: contiguous buffer containing FPGA image
|
||||
+ * @count: size of buf
|
||||
+@@ -102,6 +118,7 @@ struct fpga_image_info {
|
||||
+@@ -102,6 +114,7 @@ struct fpga_image_info {
|
||||
+ u32 disable_timeout_us;
|
||||
+ u32 config_complete_timeout_us;
|
||||
+ char *firmware_name;
|
||||
|
|
@ -1013,7 +1002,7 @@ index 0000000..33daffe
|
|||
+ struct sg_table *sgt;
|
||||
+ const char *buf;
|
||||
+ size_t count;
|
||||
+@@ -160,6 +177,7 @@ struct fpga_manager_info {
|
||||
+@@ -160,6 +173,7 @@ struct fpga_manager_info {
|
||||
+ * @write: write count bytes of configuration data to the FPGA
|
||||
+ * @write_sg: write the scatter list of configuration data to the FPGA
|
||||
+ * @write_complete: set FPGA to operating state after writing is done
|
||||
|
|
@ -1021,7 +1010,7 @@ index 0000000..33daffe
|
|||
+ * @fpga_remove: optional: Set FPGA into a specific state during driver remove
|
||||
+ * @groups: optional attribute groups.
|
||||
+ *
|
||||
+@@ -182,6 +200,7 @@ struct fpga_manager_ops {
|
||||
+@@ -182,6 +196,7 @@ struct fpga_manager_ops {
|
||||
+ int (*write_sg)(struct fpga_manager *mgr, struct sg_table *sgt);
|
||||
+ int (*write_complete)(struct fpga_manager *mgr,
|
||||
+ struct fpga_image_info *info);
|
||||
|
|
@ -1029,7 +1018,7 @@ index 0000000..33daffe
|
|||
+ void (*fpga_remove)(struct fpga_manager *mgr);
|
||||
+ const struct attribute_group **groups;
|
||||
+ };
|
||||
+@@ -196,23 +215,37 @@ struct fpga_manager_ops {
|
||||
+@@ -196,21 +211,35 @@ struct fpga_manager_ops {
|
||||
+ /**
|
||||
+ * struct fpga_manager - fpga manager structure
|
||||
+ * @name: name of low level fpga manager
|
||||
|
|
@ -1042,7 +1031,6 @@ index 0000000..33daffe
|
|||
+ * @state: state of fpga manager
|
||||
+ * @compat_id: FPGA manager id for compatibility check.
|
||||
+ * @mops: pointer to struct of fpga manager ops
|
||||
+ * @mops_owner: module containing the mops
|
||||
+ * @priv: low level driver private date
|
||||
++ * @err: low level driver error code
|
||||
++ * @dir: debugfs image directory
|
||||
|
|
@ -1058,7 +1046,6 @@ index 0000000..33daffe
|
|||
+ enum fpga_mgr_states state;
|
||||
+ struct fpga_compat_id *compat_id;
|
||||
+ const struct fpga_manager_ops *mops;
|
||||
+ struct module *mops_owner;
|
||||
+ void *priv;
|
||||
++ int err;
|
||||
++#ifdef CONFIG_FPGA_MGR_DEBUG_FS
|
||||
|
|
@ -1067,21 +1054,21 @@ index 0000000..33daffe
|
|||
+ };
|
||||
+
|
||||
+ #define to_fpga_manager(d) container_of(d, struct fpga_manager, dev)
|
||||
+@@ -258,4 +291,6 @@ __devm_fpga_mgr_register(struct device *parent, const char *name,
|
||||
+ const struct fpga_manager_ops *mops, void *priv,
|
||||
+ struct module *owner);
|
||||
+@@ -244,4 +273,6 @@ struct fpga_manager *
|
||||
+ devm_fpga_mgr_register(struct device *parent, const char *name,
|
||||
+ const struct fpga_manager_ops *mops, void *priv);
|
||||
+
|
||||
++#define FPGA_IOCTL_LOAD_DMA_BUFF _IOWR('R', 1, __u32)
|
||||
++
|
||||
+ #endif /*_LINUX_FPGA_MGR_H */
|
||||
diff --git a/zynq_image.nix b/zynq_image.nix
|
||||
index d5c5eda..7ede584 100644
|
||||
index 9d1621e..012e50c 100644
|
||||
--- a/zynq_image.nix
|
||||
+++ b/zynq_image.nix
|
||||
@@ -3,6 +3,16 @@
|
||||
with lib;
|
||||
let
|
||||
customKernel = (pkgs.linux_6_6.override {
|
||||
customKernel = (pkgs.linux.override {
|
||||
+ kernelPatches = [
|
||||
+ ({
|
||||
+ name = "xilinx-configfs-overlays";
|
||||
|
|
|
|||
Loading…
Reference in New Issue