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@ -1,141 +0,0 @@
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|||
# Fix for bus error issues when compiling cpython extensions in pyrp3 v1.2.0+
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# Patch sourced from: https://github.com/linien-org/pyrp3/tree/e6688acf8bd79d2dbe1d192d09c1a1baf1f6c67b (setup.py & monitor/Makefile)
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# Reference: https://github.com/elhep/Fast-Servo-Firmware/blob/master/OS/scripts/linien_install_requirements.sh#L28
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diff --git a/monitor/Makefile b/monitor/Makefile
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new file mode 100644
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index 0000000..044d88e
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--- /dev/null
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+++ b/monitor/Makefile
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@@ -0,0 +1,31 @@
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+# Makefile for libmonitor
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+
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+OBJS = monitor.o
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+SRCS = $(subst .o,.c, $(OBJS))
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+OSOBJS = monitor.os
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+TARGETLIB=libmonitor.so
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+CFLAGS=-g -std=gnu99 -Wall -Werror
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+LIBS=-lm -lpthread
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+
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+# Use CROSS_COMPILE=arm-linux-gnueabi-
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+CC=$(CROSS_COMPILE)gcc
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+INSTALL_DIR ?= .
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+
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+
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+all: $(TARGETLIB)
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+lib: $(TARGETLIB)
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+
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+%.os: %.c
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+ $(CC) -c -fPIC $(CFLAGS) $< -o $@
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+
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+$(TARGETLIB): $(OSOBJS)
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+ $(CC) -o $@ -shared $^ $(CFLAGS) $(LIBS)
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+
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+clean:
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+ rm -f $(TARGETLIB) *.o *.os
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+
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+# Install target - creates 'lib/' sub-directory in $(INSTALL_DIR) and copies all
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+# executables to that location.
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+install:
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+ mkdir -p $(INSTALL_DIR)/lib
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+ cp $(TARGETLIB) $(INSTALL_DIR)/lib
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\ No newline at end of file
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diff --git a/pyrp3/raw_memory.py b/pyrp3/raw_memory.py
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index ce1b28e..233b82a 100644
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--- a/pyrp3/raw_memory.py
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+++ b/pyrp3/raw_memory.py
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@@ -1,12 +1,9 @@
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from ctypes import POINTER, c_uint32, cast, cdll, create_string_buffer, sizeof
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-from importlib.machinery import EXTENSION_SUFFIXES
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from pathlib import Path
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import numpy as np
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-libmonitor_file = str(
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- Path(__file__).parent / ".." / "monitor{}".format(EXTENSION_SUFFIXES[0])
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-)
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+libmonitor_file = 'libmonitor.so'
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libmonitor = cdll.LoadLibrary(libmonitor_file)
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libmonitor.read_value.restype = c_uint32
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diff --git a/setup.py b/setup.py
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index 98bdaee..b0a8af4 100644
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--- a/setup.py
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+++ b/setup.py
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@@ -1,5 +1,10 @@
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import re
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-from distutils.core import Extension, setup
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+import os
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+
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+from distutils.core import setup
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+from distutils.command.build import build
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+from distutils.command.install import install
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+
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from pathlib import Path
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# from https://stackoverflow.com/a/7071358/2750945
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@@ -11,9 +16,50 @@ if mo:
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verstr = mo.group(1)
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else:
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raise RuntimeError("Unable to find version string in %s." % (VERSIONFILE,))
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+
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+# Patch from https://github.com/linien-org/pyrp3/blob/e6688acf8bd79d2dbe1d192d09c1a1baf1f6c67b/setup.py#L16-L55
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+build_dir = "monitor/"
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+
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+def compile_libmonitor():
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+ cwd = os.getcwd() # get current directory
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+ try:
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+ os.chdir(build_dir)
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+ os.system("make clean")
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+ os.system("make all")
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+ finally:
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+ os.chdir(cwd)
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+
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+
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+def install_libmonitor(prefix=""):
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+ cwd = os.getcwd() # get current directory
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+ try:
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+ os.chdir(build_dir)
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+ os.system("make install INSTALL_DIR={prefix}".format(prefix=prefix))
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+ finally:
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+ os.chdir(cwd)
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+
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+
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+class lib_build(build):
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+ def run(self):
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+ compile_libmonitor()
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+ build.run(self)
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+
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+
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+class lib_install(install):
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+ def run(self):
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+ compile_libmonitor()
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+ install_libmonitor(self.prefix)
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+ # install.run(self)
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+
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+# Will use nix to install libmonitor
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+cmdclass = {
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+ "build": lib_build
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+}
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+
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this_directory = Path(__file__).parent
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long_description = (this_directory / "README.rst").read_text()
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+
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setup(
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name="pyrp3",
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version=verstr,
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@@ -32,6 +78,7 @@ setup(
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"cached_property>=1.5.2",
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"numpy>=1.11.0",
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],
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+ cmdclass=cmdclass,
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classifiers=[
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"Intended Audience :: Developers",
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"Intended Audience :: Education",
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@@ -45,5 +92,4 @@ setup(
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"Topic :: Software Development :: Libraries :: Python Modules",
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],
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keywords=["redpitaya", "FPGA", "zynq"],
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- ext_modules=[Extension("monitor", ["monitor/monitor.c"])],
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)
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@ -54,7 +54,7 @@ def main_adc_config(test_pattern):
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spi.open(MAIN_ADC_BUS, MAIN_ADC_DEVICE)
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spi.max_speed_hz = 50000
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spi.mode = 0b00 # CPOL = 0 CPHA = 0
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spi.cshigh = False
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spi.cshigh = True
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# spi.read0 = False
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spi_buffer = [0x00, 0x80] # reset
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@ -121,7 +121,7 @@ def main_adc_test_mode(enable):
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spi.open(MAIN_ADC_BUS, MAIN_ADC_DEVICE)
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spi.max_speed_hz = 50000
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spi.mode = 0b00 # CPOL = 0 CPHA = 0
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spi.cshigh = False
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spi.cshigh = True
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# spi.read0 = True
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reg_contents = (
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@ -292,7 +292,7 @@ def adc_aux_read(port, type, pin):
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spi.open(1, 3) # AUX ADC 1?
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spi.max_speed_hz = 5000
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spi.mode = 0b00
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spi.cshigh = False
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spi.cshigh = True
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read_buffer = spi.xfer2(write_buffer)
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mu_voltage = read_buffer[0] << 8 | read_buffer[1] >> 2
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|
|
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@ -45,7 +45,7 @@ def main_dac_init():
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spi.open(MAIN_DAC_BUS, MAIN_DAC_DEVICE)
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spi.max_speed_hz = 5000
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spi.mode = 0b00 # CPOL = 0 CPHA = 0
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spi.cshigh = False
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spi.cshigh = True
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spi_buffer = [0x00, 0x10] # software reset
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spi.xfer2(spi_buffer)
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@ -17,255 +17,102 @@
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# You should have received a copy of the GNU General Public License
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# along with this program. If not, see <https://www.gnu.org/licenses/>.
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# Additional Reference:
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# https://github.com/torvalds/linux/blob/master/drivers/clk/clk-si5341.c
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import time
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from smbus2 import SMBus
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BUS_NO = 0
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IC_ADDR = 0x74
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DEVICE_READY = 0x00FE
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PLL_M_DEN = 0x023B
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STATUS = 0x000C
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STATUS_STICKY = 0x0011
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PAGE_ADDR = 0x1
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STATUS_LOSREF = 0x04
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STATUS_LOL = 0x08
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OUT0_MUX_SEL_ADDR = 0x15
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OUT1_MUX_SEL_ADDR = 0x1A
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OUT2_MUX_SEL_ADDR = 0x29
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OUT3_MUX_SEL_ADDR = 0x2E
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OUT2_AMPL_ADDR = 0x28
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OUT3_PDN_ADDR = 0x2B
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OUT3_FORMAT_ADDR = 0x2C
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OUT3_AMPL_ADDR = 0x2D
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def write_preamble(bus):
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preamble = [
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(0x0B24, 0xC0),
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(0x0B25, 0x00),
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(0x0502, 0x01),
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(0x0505, 0x03),
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(0x0957, 0x17),
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(0x0B4E, 0x1A),
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]
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for address, value in preamble:
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bus.write_byte_data(IC_ADDR, address, value)
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N1_DIVIDER_UPDATE_ADDR = 0x17
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def write_postamble(bus):
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postamble = [
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(0x001C, 0x01), # Soft reset
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(0x0B24, 0xC3),
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(0x0B25, 0x02),
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]
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for address, value in postamble:
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bus.write_byte_data(IC_ADDR, address, value)
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def wait_device_ready(bus):
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for _ in range(15):
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if bus.read_byte_data(IC_ADDR, DEVICE_READY) == 0x0F:
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return True
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time.sleep(0.02)
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return False
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def wait_for_lock(bus):
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for _ in range(10):
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status = bus.read_byte_data(IC_ADDR, STATUS)
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if not (status & (STATUS_LOSREF | STATUS_LOL)):
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return True
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time.sleep(0.01)
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return False
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def check_pll_status(bus):
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pll_status = bus.read_byte_data(IC_ADDR, 0x0C)
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pll_locked = not (pll_status & STATUS_LOL)
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print(f"PLL {'locked' if pll_locked else 'unlocked'}")
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return pll_locked
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def check_los_status(bus):
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los_status = bus.read_byte_data(IC_ADDR, 0x0D)
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xaxb_los = (los_status & 0x10) != 0
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print(f"XA/XB LOS {'asserted' if xaxb_los else 'deasserted'}")
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return not xaxb_los
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data_to_write = 0
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clk_out_addr = [
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OUT0_MUX_SEL_ADDR,
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OUT1_MUX_SEL_ADDR,
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OUT2_MUX_SEL_ADDR,
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OUT3_MUX_SEL_ADDR,
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]
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def configure_si5340():
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with SMBus(BUS_NO) as bus:
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if not wait_device_ready(bus):
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print("Device not ready. Aborting.")
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return
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# Programming sequence from ClockBuilder Pro, default settings
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# to initialize system using XTAL input
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main_config = [
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(0x0006, 0x00), # TOOL_VERSION
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(0x0007, 0x00), # Not in datasheet
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(0x0008, 0x00), # Not in datasheet
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(0x000B, 0x74), # I2C_ADDR
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(0x0017, 0xD0), # INT mask (disable interrupts)
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(0x0018, 0xFF), # INT mask
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(0x0021, 0x0F), # Select XTAL as input
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(0x0022, 0x00), # Not in datasheet
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(0x002B, 0x02), # SPI config
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(0x002C, 0x20), # LOS enable for XTAL
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(0x002D, 0x00), # LOS timing
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(0x002E, 0x00), # LOS trigger (thresholds)
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(0x002F, 0x00),
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(0x0030, 0x00),
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(0x0031, 0x00),
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(0x0032, 0x00),
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(0x0033, 0x00),
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(0x0034, 0x00),
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(0x0035, 0x00), # LOS trigger (thresholds) end
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(0x0036, 0x00), # LOS clear (thresholds)
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(0x0037, 0x00),
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(0x0038, 0x00),
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(0x0039, 0x00),
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(0x003A, 0x00),
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(0x003B, 0x00),
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(0x003C, 0x00),
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(0x003D, 0x00), # LOS clear (thresholds) end
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(0x0041, 0x00), # LOS0_DIV_SEL
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(0x0042, 0x00), # LOS1_DIV_SEL
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(0x0043, 0x00), # LOS2_DIV_SEL
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(0x0044, 0x00), # LOS3_DIV_SEL
|
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(0x009E, 0x00), # LOL_SET_THR
|
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(0x0102, 0x01), # Enable outputs
|
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(0x013F, 0x00), # OUTX_ALWAYS_ON
|
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(0x0140, 0x00), # OUTX_ALWAYS_ON
|
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(0x0141, 0x40), # OUT_DIS_LOL_MSK, OUT_DIS_MSK_LOS_PFD
|
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(0x0202, 0x00), # XAXB_FREQ_OFFSET (=0)
|
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bus.write_byte_data(IC_ADDR, PAGE_ADDR, 0x0) # setting page to page 0
|
||||
|
||||
# PLL Configuration
|
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(0x0235, 0x00), # M_NUM
|
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(0x0236, 0x00),
|
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(0x0237, 0x00),
|
||||
(0x0238, 0x80),
|
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(0x0239, 0x89),
|
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(0x023A, 0x00),
|
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(0x023B, 0x00), # M_DEN
|
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(0x023C, 0x00),
|
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(0x023D, 0x00),
|
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(0x023E, 0x80),
|
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# read device id
|
||||
low_word = bus.read_byte_data(IC_ADDR, 0x2)
|
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high_word = bus.read_byte_data(IC_ADDR, 0x3)
|
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|
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# Synthesizer configuration
|
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(0x0302, 0x00), # N0_NUM
|
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(0x0303, 0x00),
|
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(0x0304, 0x00),
|
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(0x0305, 0x00),
|
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(0x0306, 0x21),
|
||||
(0x0307, 0x00),
|
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(0x0308, 0x00), # N0_DEN
|
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(0x0309, 0x00),
|
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(0x030A, 0x00),
|
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(0x030B, 0x80),
|
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(0x030C, 0x01), # N0_UPDATE
|
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print(f"DEV ID: 0x{high_word:2x}{low_word:2x}")
|
||||
|
||||
# N1 Configuration (1:1 ratio)
|
||||
(0x030D, 0x00), # N1_NUM
|
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(0x030E, 0x00),
|
||||
(0x030F, 0x00),
|
||||
(0x0310, 0x00),
|
||||
(0x0311, 0x00),
|
||||
(0x0312, 0x01),
|
||||
(0x0313, 0x00), # N1_DEN
|
||||
(0x0314, 0x00),
|
||||
(0x0315, 0x00),
|
||||
(0x0316, 0x01),
|
||||
(0x0317, 0x01), # N1_UPDATE
|
||||
data_to_write = 0x1
|
||||
bus.write_byte_data(
|
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IC_ADDR, PAGE_ADDR, data_to_write
|
||||
) # change to page 1 for output settings
|
||||
|
||||
# N2 Configuration (1:1 ratio)
|
||||
(0x0318, 0x00), # N2_NUM
|
||||
(0x0319, 0x00),
|
||||
(0x031A, 0x00),
|
||||
(0x031B, 0x00),
|
||||
(0x031C, 0x00),
|
||||
(0x031D, 0x01),
|
||||
(0x031E, 0x00), # N2_DEN
|
||||
(0x031F, 0x00),
|
||||
(0x0320, 0x00),
|
||||
(0x0321, 0x01),
|
||||
(0x0322, 0x01), # N2_UPDATE
|
||||
readback = bus.read_byte_data(IC_ADDR, PAGE_ADDR)
|
||||
if data_to_write != readback:
|
||||
raise ValueError(f"Failed to set page.")
|
||||
|
||||
# N3 Configuration (1:1 ratio)
|
||||
(0x0323, 0x00), # N3_NUM
|
||||
(0x0324, 0x00),
|
||||
(0x0325, 0x00),
|
||||
(0x0326, 0x00),
|
||||
(0x0327, 0x00),
|
||||
(0x0328, 0x01),
|
||||
(0x0329, 0x00), # N3_DEN
|
||||
(0x032A, 0x00),
|
||||
(0x032B, 0x00),
|
||||
(0x032C, 0x01),
|
||||
(0x032D, 0x01), # N3_UPDATE
|
||||
for addr in clk_out_addr:
|
||||
bus.write_byte_data(IC_ADDR, addr, 1) # set source to N1
|
||||
|
||||
# Output configuration
|
||||
(0x0112, 0x06), # OUT0 config
|
||||
(0x0113, 0x09), # OUT0 format
|
||||
(0x0114, 0x3B), # OUT0 CM/AMPL
|
||||
(0x0115, 0x28), # OUT0 MUX_SEL
|
||||
bus.write_byte_data(IC_ADDR, OUT2_AMPL_ADDR, 13)
|
||||
readback = bus.read_byte_data(IC_ADDR, OUT2_AMPL_ADDR)
|
||||
# if data_to_write != readback:
|
||||
# raise ValueError(f"Problematic read: {readback}.")
|
||||
|
||||
(0x0117, 0x06), # OUT1 config
|
||||
(0x0118, 0x09), # OUT1 format
|
||||
(0x0119, 0x3B), # OUT1 CM/AMPL
|
||||
(0x011A, 0x28), # OUT1 MUX_SEL
|
||||
bus.write_byte_data(IC_ADDR, OUT2_AMPL_ADDR, 0x6B) # setting OUT2 to LVDS25
|
||||
|
||||
(0x0126, 0x06), # OUT2 config
|
||||
(0x0127, 0x09), # OUT2 format
|
||||
(0x0128, 0x3B), # OUT2 CM/AMPL
|
||||
(0x0129, 0x28), # OUT2 MUX_SEL
|
||||
bus.write_byte_data(IC_ADDR, OUT3_FORMAT_ADDR, 0xCC) # SETTING out3 to LVCMOS 18
|
||||
# bus.write_byte_data(IC_ADDR, 0x2E, 0x09) # SETTING out3 to LVCMOS 33
|
||||
|
||||
(0x012B, 0x06), # OUT3 config
|
||||
(0x012C, 0xCC), # OUT3 format
|
||||
(0x012D, 0x00), # OUT3 CM/AMPL
|
||||
(0x012E, 0x58), # OUT3 MUX_SEL
|
||||
readback = bus.read_byte_data(IC_ADDR, OUT3_PDN_ADDR)
|
||||
print(f"Si5340 OUTx_PDN CLK3: 0x{readback}")
|
||||
|
||||
# Miscellaneous configuration
|
||||
(0x090E, 0x02), # XAXB_EXTCLK_EN=0 XAXB_PDNB=1 (use XTAL)
|
||||
(0x091C, 0x04), # ZDM_EN=4 (Normal mode)
|
||||
(0x0943, 0x00), # IO_VDD_SEL
|
||||
(0x0949, 0x00), # IN_EN (disable input clocks)
|
||||
(0x094A, 0x00), # INx_TO_PFD_EN (disabled)
|
||||
(0x094E, 0x49), # REFCLK_HYS_SEL (set by CBPro)
|
||||
(0x094F, 0x02), # Not in datasheet
|
||||
(0x095E, 0x00), # M_INTEGER (set by CBPro)
|
||||
(0x0A02, 0x00), # N_ADD_0P5 (set by CBPro)
|
||||
(0x0A03, 0x01), # N_CLK_TO_OUTX_EN
|
||||
(0x0A04, 0x01), # N_PIBYP
|
||||
(0x0A05, 0x01), # N_PDNB
|
||||
(0x0A14, 0x00), # N0_HIGH_FREQ (set by CBPro)
|
||||
(0x0A1A, 0x00), # N1_HIGH_FREQ (set by CBPro)
|
||||
(0x0A20, 0x00), # N2_HIGH_FREQ (set by CBPro)
|
||||
(0x0A26, 0x00), # N3_HIGH_FREQ (set by CBPro)
|
||||
(0x0B44, 0x0F), # PDIV_ENB (set by CBPro)
|
||||
(0x0B4A, 0x0E), # N_CLK_DIS
|
||||
(0x0B57, 0x0E), # VCO_RESET_CALCODE (set by CBPro)
|
||||
(0x0B58, 0x01), # VCO_RESET_CALCODE (set by CBPro)
|
||||
]
|
||||
readback = bus.read_byte_data(IC_ADDR, OUT3_FORMAT_ADDR)
|
||||
print(f"Si5340 OUTx_FORMAT CLK3: 0x{readback}")
|
||||
|
||||
write_preamble(bus)
|
||||
readback = bus.read_byte_data(IC_ADDR, OUT3_AMPL_ADDR)
|
||||
print(f"Si5340 OUTx_AMPL CLK3: 0x{readback}")
|
||||
|
||||
time.sleep(0.3)
|
||||
readback = bus.read_byte_data(IC_ADDR, OUT3_MUX_SEL_ADDR)
|
||||
print(f"Si5340 OUTx_CM CLK3: 0x{readback}")
|
||||
|
||||
print("Writing main configuration...")
|
||||
for address, value in main_config:
|
||||
bus.write_byte_data(IC_ADDR, address, value)
|
||||
print("Main configuration written")
|
||||
bus.write_byte_data(
|
||||
IC_ADDR, PAGE_ADDR, 0x3
|
||||
) # setting page to 3 to change dividers values
|
||||
|
||||
write_postamble(bus)
|
||||
n1_numerator = [0x0, 0x0, 0x0, 0x60, 0x22, 0x0]
|
||||
n1_numerator_10M = [0x0, 0x0, 0x0, 0xC0, 0x57, 0x1]
|
||||
n1_num_addr = [0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12]
|
||||
n1_denom_addr = [0x13, 0x14, 0x15, 0x16]
|
||||
for addr, value in zip(n1_num_addr, n1_numerator):
|
||||
bus.write_byte_data(IC_ADDR, addr, value)
|
||||
|
||||
if not wait_for_lock(bus):
|
||||
print("Error waiting for input clock or PLL lock")
|
||||
else:
|
||||
print("Input clock present and PLL locked")
|
||||
bus.write_byte_data(IC_ADDR, N1_DIVIDER_UPDATE_ADDR, 1)
|
||||
|
||||
bus.write_byte_data(IC_ADDR, STATUS_STICKY, 0)
|
||||
for addr in n1_num_addr:
|
||||
readback = bus.read_byte_data(IC_ADDR, addr)
|
||||
print(f"Numerator buffer: 0x{readback:02x}")
|
||||
|
||||
# Final status check
|
||||
pll_locked = check_pll_status(bus)
|
||||
xaxb_signal_present = check_los_status(bus)
|
||||
for addr in n1_denom_addr:
|
||||
readback = bus.read_byte_data(IC_ADDR, addr)
|
||||
print(f"Denominator buffer: 0x{readback:02x}")
|
||||
|
||||
if not pll_locked:
|
||||
print("Error: PLL is not locked")
|
||||
elif not xaxb_signal_present:
|
||||
print("Error: XA/XB signal is lost")
|
||||
else:
|
||||
print("Si5340 configuration completed successfully")
|
||||
bus.write_byte_data(IC_ADDR, PAGE_ADDR, 0x0) # setting page to page 0
|
||||
|
||||
if __name__ == "__main__":
|
||||
configure_si5340()
|
12
flake.nix
12
flake.nix
|
@ -110,23 +110,13 @@
|
|||
rev = "v${version}";
|
||||
hash = "sha256-43TTlpJ5SMAjQM71bNVvrWQyciRXM3zpuA/Dw41AEgU=";
|
||||
};
|
||||
patches = ./fast-servo/linien-pyrp3-monitor.patch;
|
||||
nativeBuildInputs = with pkgs-armv7l.python3Packages; [
|
||||
setuptools wheel setuptools-scm
|
||||
] ++ (with pkgs-armv7l; [ gcc gnumake ]);
|
||||
nativeBuildInputs = with pkgs-armv7l.python3Packages; [ setuptools wheel setuptools-scm ];
|
||||
propagatedBuildInputs = with pkgs-armv7l.python3Packages; [
|
||||
myhdl
|
||||
rpyc4
|
||||
cached-property
|
||||
numpy
|
||||
];
|
||||
postInstall = ''
|
||||
cp monitor/libmonitor.so $out/lib
|
||||
'';
|
||||
postFixup = ''
|
||||
substituteInPlace $out/${pkgs.python3.sitePackages}/pyrp3/raw_memory.py \
|
||||
--replace "libmonitor.so" "$out/lib/libmonitor.so"
|
||||
'';
|
||||
};
|
||||
|
||||
linien-server = pkgs-armv7l.python3Packages.buildPythonPackage rec {
|
||||
|
|
Loading…
Reference in New Issue