use previous working dac code + set linien off

fast-servo/linien-gateware/cores/adc.py

@@ -22,12 +22,11 @@ from migen.genlib.cdc import MultiReg
 from misoc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage
 
 
-class CRG(Module):
+class _CRG(Module):
     def __init__(self, platform, dco_clk, dco_freq=200e6):
         self.clock_domains.cd_dco = ClockDomain()
         self.clock_domains.cd_dco2x = ClockDomain()
         self.clock_domains.cd_dco2d = ClockDomain()
-        self.clock_domains.cd_dco2d_45_degree = ClockDomain()
         dco_clk_p, dco_clk_n = dco_clk
 
         dco_clk_buf = Signal()
@@ -42,83 +41,59 @@ class CRG(Module):
         clk_dco = Signal()
         clk_dco2x = Signal()
         clk_dco2d = Signal()
-        clk_dco2d_45_degree = Signal()
-        mmcm_ps_psdone = Signal()
-
         self.locked = Signal()
-        self.mmcm_rst = Signal()
-        self.ddr_clk_phase_shift_en = Signal()
-        self.ddr_clk_phase_incdec = Signal()
 
         platform.add_period_constraint(dco_clk_p, 1e9 / dco_freq)
         self.specials += [
             Instance(
-                "MMCME2_ADV",
+                "PLLE2_BASE",
                 p_BANDWIDTH="OPTIMIZED",
                 p_DIVCLK_DIVIDE=1,
                 p_CLKFBOUT_PHASE=0.0,
-                p_CLKFBOUT_MULT_F=4,  # VCO @ 800 MHz
+                p_CLKFBOUT_MULT=4,  # VCO @ 800 MHz
                 p_CLKIN1_PERIOD=(1e9 / dco_freq),
                 p_REF_JITTER1=0.01,
                 p_STARTUP_WAIT="FALSE",
                 i_CLKIN1=dco_clk_buf,
                 i_PWRDWN=0,
-                i_RST=ResetSignal("sys") | self.mmcm_rst,
+                i_RST=ResetSignal("sys"),
                 i_CLKFBIN=clk_feedback_buf,
                 o_CLKFBOUT=clk_feedback,
-
-                p_CLKOUT0_USE_FINE_PS="TRUE",
-                p_CLKOUT0_DIVIDE_F=8,
-                p_CLKOUT0_PHASE=45.0,
+                p_CLKOUT0_DIVIDE=4,
+                p_CLKOUT0_PHASE=0.0,
                 p_CLKOUT0_DUTY_CYCLE=0.5,
-                o_CLKOUT0=clk_dco2d_45_degree,  # 100 MHz <- dco_clk / 2 = 200 MHz / 2
-                o_LOCKED=self.locked,
-
+                o_CLKOUT0=clk_dco,  # 200 MHz <- dco_clk
                 p_CLKOUT1_DIVIDE=2,
                 p_CLKOUT1_PHASE=0.0,
                 p_CLKOUT1_DUTY_CYCLE=0.5,
                 o_CLKOUT1=clk_dco2x,  # 400 MHZ <- 2 * dco_clk = 2*200 MHz
-                
                 p_CLKOUT2_DIVIDE=8,
                 p_CLKOUT2_PHASE=0.0,
                 p_CLKOUT2_DUTY_CYCLE=0.5,
                 o_CLKOUT2=clk_dco2d,  # 100 MHz <- dco_clk / 2 = 200 MHz / 2
-                
-                p_CLKOUT3_DIVIDE=4,
-                p_CLKOUT3_PHASE=0.0,
-                p_CLKOUT3_DUTY_CYCLE=0.5,
-                o_CLKOUT3=clk_dco,  # 200 MHz <- dco_clk
-
-                i_PSCLK=ClockSignal(),
-                i_PSEN=self.ddr_clk_phase_shift_en,
-                i_PSINCDEC=self.ddr_clk_phase_incdec,
-                o_PSDONE=mmcm_ps_psdone,
+                o_LOCKED=self.locked,
             )
         ]
 
         self.specials += Instance("BUFG", i_I=clk_feedback, o_O=clk_feedback_buf)
         self.specials += Instance("BUFG", i_I=clk_dco, o_O=self.cd_dco.clk)
         self.specials += Instance("BUFG", i_I=clk_dco2d, o_O=self.cd_dco2d.clk)
-        self.specials += Instance("BUFG", i_I=clk_dco2d_45_degree, o_O=self.cd_dco2d_45_degree.clk)
         self.specials += Instance("BUFG", i_I=clk_dco2x, o_O=self.cd_dco2x.clk)
 
-        # Ignore dco2d to mmcm dco_clk path created by SoC's rst.
-        platform.add_false_path_constraints(self.cd_dco2d.clk, dco_clk_buf)
-        self.specials += Instance("FD", p_INIT=1, i_D=~self.locked, i_C=self.cd_dco2d.clk, o_Q=self.cd_dco2d.rst)
 
 class ADC(Module, AutoCSR):
     def __init__(self, platform, dco_freq=200e6):
         adc_pads = platform.request("adc")
         afe_pads = platform.request("adc_afe")
 
-        self.frame_csr = CSRStatus(5)
+        self.frame_csr = CSRStatus(4)
         self.data_ch0 = CSRStatus(16)
         self.data_ch1 = CSRStatus(16)
 
         self.tap_delay = CSRStorage(5)
         self.bitslip_csr = CSRStorage(1)
 
-        self.afe_ctrl = CSRStorage(7)
+        self.afe_ctrl = CSRStorage(4)
 
         tap_delay_val = Signal(5)
         bitslip = Signal()
@@ -142,14 +117,11 @@ class ADC(Module, AutoCSR):
             # dco_clk.n.eq(adc_pads.dco_n),
             tap_delay_val.eq(self.tap_delay.storage),
             Cat(ch1_gain_x10, ch2_gain_x10, ch1_shdn, ch2_shdn).eq(
-                self.afe_ctrl.storage[0:4]
+                self.afe_ctrl.storage
             ),
         ]
 
-        self.submodules.crg = CRG(platform, dco_clk, dco_freq)
-        self.comb += self.afe_ctrl.storage[4].eq(self.crg.mmcm_rst)
-        self.comb += self.afe_ctrl.storage[5].eq(self.crg.ddr_clk_phase_shift_en)
-        self.comb += self.afe_ctrl.storage[6].eq(self.crg.ddr_clk_phase_incdec)
+        self.submodules._crg = _CRG(platform, dco_clk, dco_freq)
 
         self.specials += MultiReg(self.bitslip_csr.re, bitslip_re_dco_2d, "dco2d")
         self.sync.dco2d += [
@@ -157,8 +129,7 @@ class ADC(Module, AutoCSR):
         ]
 
         self.comb += [
-            self.frame_csr.status[0:4].eq(self.s_frame[0:4]),
-            self.frame_csr.status[4].eq(self.crg.locked),
+            self.frame_csr.status.eq(self.s_frame),
             self.data_ch0.status.eq(self.data_out[0]),
             self.data_ch1.status.eq(self.data_out[1]),
         ]
@@ -175,7 +146,7 @@ class ADC(Module, AutoCSR):
 
         self.specials += Instance(
             "LTC2195",
-            i_rst_in=ResetSignal("dco2d"),
+            i_rst_in=ResetSignal("sys"),
             i_clk200=ClockSignal("idelay"),
             i_DCO=ClockSignal("dco"),
             i_DCO_2D=ClockSignal("dco2d"),

fast-servo/linien-gateware/cores/dac.py

@@ -42,7 +42,7 @@ class DAC(Module, AutoCSR):
 
         self.comb += [
             Cat(manual_override, ch0_pd, ch1_pd).eq(self.dac_ctrl.storage),
-            dac_pads.rst.eq(ResetSignal("dco2d")),
+            dac_pads.rst.eq(ResetSignal("sys")),
             dac_afe_pads.ch1_pd_n.eq(~ch0_pd),
             dac_afe_pads.ch2_pd_n.eq(~ch1_pd),
             output_data_ch0.eq(
@@ -53,22 +53,22 @@ class DAC(Module, AutoCSR):
             ),
         ]
 
-        self.specials += [
-            Instance("ODDR", 
-                i_C=ClockSignal("dco2d"), 
-                i_CE=~ResetSignal("dco2d"), 
-                i_D1=output_data_ch0[lane], # DDR CLK Rising Edge
-                i_D2=output_data_ch1[lane], # DDR CLK Falling Edge
-                o_Q=dac_pads.data[lane],
-                p_DDR_CLK_EDGE="SAME_EDGE") 
-            for lane in range(14)]
-        self.specials += Instance("ODDR", 
-                i_C=ClockSignal("dco2d_45_degree"), 
-                i_CE=~ResetSignal("dco2d"), 
-                i_D1=0, 
-                i_D2=1, 
-                o_Q=dac_pads.dclkio,
-                p_DDR_CLK_EDGE="SAME_EDGE")
+        # data
+        for lane in range(14):
+            self.specials += DDROutput(
+                i1 = output_data_ch0[lane], 
+                i2 = output_data_ch1[lane], 
+                o = dac_pads.data[lane], 
+                clk = ClockSignal("dco2d")
+            )
+        
+        # clock forwarding
+        self.specials += DDROutput(
+            i1 = 0b0,
+            i2 = 0b1,
+            o = dac_pads.dclkio,
+            clk = ClockSignal("dco2d"),
+        )
 
 
 class AUX_DAC_CTRL(Module, AutoCSR):

fast-servo/pyfastservo/adc.py

@@ -17,7 +17,9 @@
 # You should have received a copy of the GNU General Public License
 # along with this program. If not, see <https://www.gnu.org/licenses/>.
 
-import time
+import mmap
+import os
+
 import spidev
 from pyfastservo.common import (
     ADC_AFE_CTRL_ADDR,
@@ -31,8 +33,6 @@ from pyfastservo.common import (
     AUX_ADC_ADDR,
     MAP_MASK,
     PAGESIZE,
-    write_to_memory,
-    read_from_memory
 )
 
 # /dev/spidev1.0  <=> spidev<BUS>.<DEVICE>
@@ -44,181 +44,270 @@ AUX_ADC_PORT_A = 2
 AUX_ADC_PORT_B = 3
 
 
-def spi_write(spi, address, value):
-    spi.xfer2([address, value])
-
-def spi_read(spi, address):
-    rx_buffer = spi.xfer2([0x80 | address, 0x00])
-    return rx_buffer[1]
-
-def main_adc_config(spi, test_pattern):
+def main_adc_config(test_pattern):
     high_word = (test_pattern & 0xFF00) >> 8
     low_word = test_pattern & 0xFF
 
-    spi_write(spi, 0x00, 0x80)              # reset
-    spi_write(spi, 0x01, 0x20)              # REGISTER A1: set to Two's complement Data Format
-    spi_write(spi, 0x02, 0x15)              # REGISTER A2: set to LVDS output, set 4 data lanes and turn on test mode
-    spi_write(spi, 0x03, high_word)         # REGISTER A3: test pattern high word
-    spi_write(spi, 0x04, low_word)          # REGISTER A4: test pattern low word
-
-def main_adc_test_mode(spi, enable):
-    reg_contents = 0x15 if enable else 0x11 # set to LVDS output, set 4 data lanes and turn on or off test mode
-    spi_write(spi, 0x02, reg_contents)
-
-def verify_adc_registers(spi, reg_to_check):
-    for register, expected_value in reg_to_check.items():
-        value = spi_read(spi, register)
-        print(f"Spi readback register 0x{register:02x}: 0x{value:02x}")
-        if value != expected_value:
-            print(f"Different value read than sent in reg 0x{register:02x}")
-
-def read_frame():
-    return read_from_memory(ADC_FRAME_ADDR, 1)[0]
-
-def perform_bitslip():
-    for i in range(4):
-        current_frame = read_frame()
-        if current_frame & 0x0F != 0x0C:
-            print(f"Performing bitslip (iteration: {i}). Current frame: 0x{current_frame:02x}")
-            write_to_memory(ADC_BITSLIP_ADDR, 1)
-        else:
-            print(f"No bitslip required; Current frame: 0x{current_frame:02x}")
-            return
-
-def mmcm_rst():
-    curr_cfg = read_from_memory(ADC_AFE_CTRL_ADDR, 1)[0] & 0x0F
-    write_to_memory(ADC_AFE_CTRL_ADDR, 0x10 | curr_cfg) # Reset MMCM
-    write_to_memory(ADC_AFE_CTRL_ADDR, 0x00 | curr_cfg) # Release MMCM Reset
-    while not(read_frame() & 0x10):
-        print(f"Waiting for MMCM to lock")
-        time.sleep(0.001)
-
-def inc_ddr_clk_phase():
-    curr_cfg = read_from_memory(ADC_AFE_CTRL_ADDR, 1)[0] & 0x1F
-    write_to_memory(ADC_AFE_CTRL_ADDR, 0x40 | curr_cfg) # Set MMCM Phase Shift to be INC
-    write_to_memory(ADC_AFE_CTRL_ADDR, 0x60 | curr_cfg) # Assert MMCM Phase Shift EN High
-    write_to_memory(ADC_AFE_CTRL_ADDR, curr_cfg)        # Deassert MMCM Phase Shift EN High
-
-def dec_ddr_clk_phase():
-    curr_cfg = read_from_memory(ADC_AFE_CTRL_ADDR, 1)[0] & 0x1F
-    write_to_memory(ADC_AFE_CTRL_ADDR, 0x00 | curr_cfg) # Set MMCM Phase Shift to be DEC
-    write_to_memory(ADC_AFE_CTRL_ADDR, 0x20 | curr_cfg) # Assert MMCM Phase Shift EN High
-    write_to_memory(ADC_AFE_CTRL_ADDR, curr_cfg)        # Deassert MMCM Phase Shift EN High
-
-def find_edge():
-    prev_frame = read_frame()
-    for tap_delay in range(32):
-        write_to_memory(ADC_DELAY_ADDR, tap_delay)
-        current_frame = read_frame()
-
-        print(f"Tap delay: {tap_delay}, Current frame: 0x{current_frame:02x}")
-        print(f"prev_frame: 0x{prev_frame:02x}")
-
-        if current_frame != prev_frame:
-            final_delay = ((tap_delay+1) // 2) + 2
-            print(f"Edge detected; setting iDelay to: {final_delay}")
-            write_to_memory(ADC_DELAY_ADDR, final_delay)
-            return
-
-        prev_frame = current_frame
-
-    # If no edge detected
-    final_delay = 11
-    print(f"No edge detected; setting iDelay to: {final_delay}")
-    write_to_memory(ADC_DELAY_ADDR, final_delay)
-
-def read_adc_channel(high_addr, low_addr):
-    return (read_from_memory(high_addr, 1)[0] << 8) | read_from_memory(low_addr, 1)[0]
-
-def print_adc_channels():
-    adc_ch0 = read_adc_channel(ADC_CH0_HIGH_ADDR, ADC_CH0_LOW_ADDR)
-    adc_ch1 = read_adc_channel(ADC_CH1_HIGH_ADDR, ADC_CH1_LOW_ADDR)
-    print(f"Final ADC_CH0: 0x{adc_ch0:04x}")
-    print(f"Final ADC_CH1: 0x{adc_ch1:04x}")
-
-def enable_adc_afe(ch1_x10=False, ch2_x10=False):
-    ctrl_value = (ch2_x10 << 1) | ch1_x10
-    write_to_memory(ADC_AFE_CTRL_ADDR, ctrl_value)
-    afe_ctrl = read_from_memory(ADC_AFE_CTRL_ADDR, 1)[0]
-    print(f"ADC_AFE_CTRL: 0x{afe_ctrl:02X}")
-    return afe_ctrl
-
-def search_edge():
-    for tap_delay in range(32):
-        print(f"iDelay to: {tap_delay}")
-        write_to_memory(ADC_DELAY_ADDR, tap_delay)
-        time.sleep(1)
-        current_frame = read_frame()
-        print(f"Tap delay: {tap_delay}, Current frame: 0x{current_frame:02x}")
-        print_adc_channels()
-
-def print_adc_channel(ch):
-    if ch == 0:
-        adc_ch0 = read_adc_channel(ADC_CH0_HIGH_ADDR, ADC_CH0_LOW_ADDR)
-        print(f"Final ADC_CH0: 0x{adc_ch0:04x}")
-    if ch == 1:
-        adc_ch1 = read_adc_channel(ADC_CH1_HIGH_ADDR, ADC_CH1_LOW_ADDR)
-        print(f"Final ADC_CH1: 0x{adc_ch1:04x}")
-
-def find_min_max_ch(ch):
-    test = []
-    for i in range(100):
-        if ch == 0:
-            test.append(read_adc_channel(ADC_CH0_HIGH_ADDR, ADC_CH0_LOW_ADDR))
-        else:
-            test.append(read_adc_channel(ADC_CH1_HIGH_ADDR, ADC_CH1_LOW_ADDR)) 
-        print("ch", ch, hex(test[-1]))
-    print("Min:", hex(min(test)))
-    print("Max:", hex(max(test)))
-    print("Diff:", hex(max(test)-min(test)))
-
-
-def configure_ltc2195():
     spi = spidev.SpiDev()
+
     try:
         spi.open(MAIN_ADC_BUS, MAIN_ADC_DEVICE)
         spi.max_speed_hz = 50000
         spi.mode = 0b00  # CPOL = 0 CPHA = 0
         spi.cshigh = False
+        # spi.read0 = False
 
-        test_pattern = 0x811F
-        main_adc_config(spi, test_pattern)
+        spi_buffer = [0x00, 0x80]  # reset
+        rx_buffer = [0x00, 0x00]
 
-        verify_adc_registers(spi, {
-            0x01: 0x20,
-            0x02: 0x15,
-            0x03: (test_pattern & 0xFF00) >> 8,
-            0x04: test_pattern & 0xFF
-        })
+        spi.xfer2(spi_buffer)
 
-        # ADC software reset put its PLL to sleep momentarily. Thus, MMCM needs to be reset as well.
-        mmcm_rst()
+        # REGISTER A1
+        spi_buffer = [0x01, 0x20]  # set to Two's complement Data Format
+        spi.xfer2(spi_buffer)
+
+        # read values back
+        spi_buffer = [0x81, 0x00]
+        rx_buffer = spi.xfer2(spi_buffer)
+        print(f"Spi readback register 0x01: 0x{rx_buffer[1]:02x}")
+        if rx_buffer[1] != 0x20:
+            print("Different value read than sent in reg 0x02")
+
+        # REGISTER A2
+        spi_buffer = [
+            0x02,
+            0x15,
+        ]  # set to LVDS output, set 4 data lanes and turn on test mode
+        spi.xfer2(spi_buffer)
+
+        # read values back
+        spi_buffer = [0x82, 0x00]
+        rx_buffer = spi.xfer2(spi_buffer)
+        print(f"Spi readback register 0x02: 0x{rx_buffer[1]:02x}")
+        if rx_buffer[1] != 0x15:
+            print("Different value read than sent in reg 0x02")
+
+        # REGISTER A3
+        # test pattern high word
+        spi_buffer = [0x03, high_word]
+        spi.xfer2(spi_buffer)
+
+        # read balues back
+        spi_buffer = [0x83, 0x00]
+        rx_buffer = spi.xfer2(spi_buffer)
+        print(f"Spi readback register 0x03: 0x{rx_buffer[1]:02x}")
+        if rx_buffer[1] != high_word:
+            print("Different value read than sent in reg 0x03")
+
+        # REGISTER A4
+        # test pattern low word
+        spi_buffer = [0x04, low_word]
+        spi.xfer2(spi_buffer)
+
+        # read balues back
+        spi_buffer = [0x84, 0x00]
+        rx_buffer = spi.xfer2(spi_buffer)
+        print(f"Spi readback register 0x04: 0x{rx_buffer[1]:02x}")
+        if rx_buffer[1] != low_word:
+            print("Different value read than sent in reg 0x04")
+    finally:
+        spi.close()
+
+
+def main_adc_test_mode(enable):
+    spi = spidev.SpiDev()
+
+    try:
+        spi.open(MAIN_ADC_BUS, MAIN_ADC_DEVICE)
+        spi.max_speed_hz = 50000
+        spi.mode = 0b00  # CPOL = 0 CPHA = 0
+        spi.cshigh = False
+        # spi.read0 = True
+
+        reg_contents = (
+            0x15 if enable else 0x11
+        )  # set to LVDS output, set 4 data lanes and turn on or off test mode
+        spi_buffer = [0x02, reg_contents]
+        spi.xfer2(spi_buffer)
+
+        # read values back
+        spi_buffer = [0x82, 0x00]
+        rx_buffer = spi.xfer2(spi_buffer)
+        print(f"Spi readback register 0x02: 0x{rx_buffer[1]:02x}")
+        if rx_buffer[1] != reg_contents:
+            print("Different value read than sent in reg 0x02")
+    finally:
+        spi.close()
+
+
+def read_from_memory(address, n_bytes):
+    assert n_bytes <= 4
+    addr = address
+
+    try:
+        f = os.open("/dev/mem", os.O_SYNC | os.O_RDWR)
+        with mmap.mmap(
+            f,
+            PAGESIZE,
+            mmap.MAP_SHARED,
+            mmap.PROT_READ | mmap.PROT_WRITE,
+            offset=addr & ~MAP_MASK,
+        ) as mem:
+            start_addr = addr & MAP_MASK
+            stop_addr = start_addr + 4
+            # print(f"addr: 0x{addr:x}\tstart_addr: 0x{start_addr}\tstop_addr: 0x{stop_addr}")
+            contents = mem[start_addr:stop_addr]
+            read_value = list(contents)[:n_bytes]
+            # print("Read value: ", read_value)
+    finally:
+        os.close(f)
+
+    return read_value
+
+
+def write_to_memory(address, value):
+    value_bytes = value.to_bytes(4, "little")
+    addr = address
+
+    try:
+        f = os.open("/dev/mem", os.O_SYNC | os.O_RDWR)
+        with mmap.mmap(
+            f,
+            PAGESIZE,
+            mmap.MAP_SHARED,
+            mmap.PROT_READ | mmap.PROT_WRITE,
+            offset=addr & ~MAP_MASK,
+        ) as mem:
+            start_addr = addr & MAP_MASK
+            stop_addr = start_addr + 4
+            # print(f"addr: 0x{addr:x}\tstart_addr: 0x{start_addr}\tstop_addr: 0x{stop_addr}")
+            mem[start_addr:stop_addr] = value_bytes
+            contents = mem[start_addr:stop_addr]
+            # print("Read value: ", list(contents), " written value: ", list(value_bytes))
+    finally:
+        os.close(f)
+
+
+def word_align():
+    value = 0
+    edge_start = None
+    edge_end = None
+    tap_delay = 0
+
+    # Perform initial bitslip if necessary
+    for i in range(4):
+        current_frame = read_from_memory(ADC_FRAME_ADDR, 1)[0]
+        if current_frame != 0x0C:
+            print(f"Performing bitslip (iteration: {i}). Current frame: 0x{current_frame:02x}")
+            write_to_memory(ADC_BITSLIP_ADDR, 1)
+        else:
+            print(f"No bitslip required; Current frame = 0x{current_frame:02x}")
+            break
+
+    # Sweep through all possible delay values
+    for tap_delay in range(32):
+        write_to_memory(ADC_DELAY_ADDR, tap_delay)
+        current_frame = read_from_memory(ADC_FRAME_ADDR, 1)[0]
         
-        # Performing Word Align
-        perform_bitslip()
-        find_edge()
-        
-        # Printing it once is not enough to check whether the alignment is correct.
-        for i in range(100):
-            print_adc_channels()
+        print(f"Tap delay: {tap_delay}, Current frame: 0x{current_frame:02x}")
 
-        main_adc_test_mode(spi, False)
-        verify_adc_registers(spi, {0x02: 0x11})  # Verify test mode is off
-      
-        # FIXME: AFE Gain 1x is not functional on that batch of fast servo under development
-        enable_adc_afe(ch1_x10=1, ch2_x10=1)
+        if current_frame == 0x0C:
+            if edge_start is None:
+                edge_start = tap_delay
+        elif edge_start is not None and edge_end is None:
+            edge_end = tap_delay - 1
+            break
 
-        #find_min_max_ch(0)
-        #find_min_max_ch(1)
+    # Analyze the sweep results
+    if edge_start is None:
+        print("No stable region found. Using default delay.")
+        optimal_delay = 11  # Default value
+    elif edge_end is None:
+        print("Stable region extends to the end. Using middle of detected stable region.")
+        optimal_delay = (edge_start + 31) // 2
+    else:
+        print(f"Stable region detected from {edge_start} to {edge_end}")
+        optimal_delay = (edge_start + edge_end) // 2
 
-        #for i in range(10):
-        #    print_adc_channel(0)
+    # Set the optimal delay
+    write_to_memory(ADC_DELAY_ADDR, optimal_delay)
+    print(f"Setting optimal delay to: {optimal_delay}")
 
-        #for i in range(10):
-        #    print_adc_channel(1)
+    # Verify final setup
+    adc_ch0 = (read_from_memory(ADC_CH0_HIGH_ADDR, 1)[0] << 8) | read_from_memory(ADC_CH0_LOW_ADDR, 1)[0]
+    adc_ch1 = (read_from_memory(ADC_CH1_HIGH_ADDR, 1)[0] << 8) | read_from_memory(ADC_CH1_LOW_ADDR, 1)[0]
+    print(f"Final ADC_CH0: 0x{adc_ch0:04x}")
+    print(f"Final ADC_CH1: 0x{adc_ch1:04x}")
+
+    return optimal_delay
+
+
+def modify_bit(original_value, position, bit_value):
+    mask = 1 << position
+    return (original_value & ~mask) | (bit_value << position)
+
+
+def adc_aux_config():
+    # MSB to LSB
+    # | RANGE | ADDR [2:0] | DIFF |
+    #       DIFF = 0    =>  configure as single ended (it is negated in gateware)
+    #       RANGE = 0   =>  configure as 0-2.5 Vref
+    to_write = 0b00000
+    write_to_memory(AUX_ADC_ADDR, to_write)
+
+
+def adc_aux_read(port, type, pin):
+    # port:
+    #   1 - port A
+    #   2 - port B
+    # type:
+    #   0 - single-ended
+    #   1 - differential
+    # pin:
+    #   0b000   - VA1/VB1
+    #   0b001   - VA2/VB2
+    #   0b010   - VA3/VB3
+    #   0b011   - VA4/VB4
+
+    assert type in (0, 1)
+    assert port in (1, 2)
+
+    write_buffer = [0, 0]
+    read_buffer = [0, 0]
+
+    aux_config_reg = read_from_memory(AUX_ADC_ADDR, 1)[0]
+    aux_config = (aux_config_reg & 0b10001) | pin << 1
+    write_to_memory(AUX_ADC_ADDR, aux_config)
+
+    spi = spidev.SpiDev()
+    try:
+        spi.open(1, 3)  # AUX ADC 1?
+        spi.max_speed_hz = 5000
+        spi.mode = 0b00
+        spi.cshigh = False
+
+        read_buffer = spi.xfer2(write_buffer)
+        mu_voltage = read_buffer[0] << 8 | read_buffer[1] >> 2
+        print(f"MU_voltage: 0x{mu_voltage:04X}")
+        print(f"Read_buffer[0]: 0x{read_buffer[0]:02X}")
+        print(f"Read_buffer[1]: 0x{read_buffer[1]:02X}")
+        return mu_voltage * 2.5 / 4096
 
     finally:
         spi.close()
 
+
+def main():
+    main_adc_config(0x811F)
+    optimal_delay = word_align()
+
+    main_adc_test_mode(False)
+
+    write_to_memory(ADC_AFE_CTRL_ADDR, 0b1100) # {-, -, ch2_X10, ch1_X10}
+    print(read_from_memory(ADC_AFE_CTRL_ADDR, 1)[0])
+
+    print(f"Optimal delay used: {optimal_delay}")
+
+
 if __name__ == "__main__":
-    configure_ltc2195()
+    main()

fast-servo/pyfastservo/common.py

@@ -17,16 +17,13 @@
 # You should have received a copy of the GNU General Public License
 # along with this program. If not, see <https://www.gnu.org/licenses/>.
 
-import os
-import mmap
-
 CSR_SIZE = 0x800
 MAP_SIZE = 0x1000
 MAP_MASK = 0xFFF
 PAGESIZE = 0x1000
 
-# LINIEN_OFFSET = 0x0
-LINIEN_OFFSET = 0x300000
+LINIEN_OFFSET = 0x0
+# LINIEN_OFFSET = 0x300000
 
 # ----------------------------------------------------------------
 # FRONT PANEL LEDS REGISTER ADDRESSES
@@ -74,47 +71,4 @@ CTRL_ADDR               =   DAC_BASE_ADDR + CTRL_OFFSET
 CH0_HIGH_WORD_ADDR      =   DAC_BASE_ADDR + CH0_HIGH_WORD_OFFSET
 CH0_LOW_WORD_ADDR       =   DAC_BASE_ADDR + CH0_LOW_WORD_OFFSET
 CH1_HIGH_WORD_ADDR      =   DAC_BASE_ADDR + CH1_HIGH_WORD_OFFSET
-CH1_LOW_WORD_ADDR       =   DAC_BASE_ADDR + CH1_LOW_WORD_OFFSET
-
-
-def read_from_memory(address, n_bytes):
-    assert n_bytes <= 4
-    addr = address
-
-    try:
-        f = os.open("/dev/mem", os.O_SYNC | os.O_RDWR)
-        with mmap.mmap(
-            f,
-            PAGESIZE,
-            mmap.MAP_SHARED,
-            mmap.PROT_READ | mmap.PROT_WRITE,
-            offset=addr & ~MAP_MASK,
-        ) as mem:
-            start_addr = addr & MAP_MASK
-            stop_addr = start_addr + 4
-            contents = mem[start_addr:stop_addr]
-            read_value = list(contents)[:n_bytes]
-    finally:
-        os.close(f)
-
-    return read_value
-
-def write_to_memory(address, value):
-    value_bytes = value.to_bytes(4, "little")
-    addr = address
-
-    try:
-        f = os.open("/dev/mem", os.O_SYNC | os.O_RDWR)
-        with mmap.mmap(
-            f,
-            PAGESIZE,
-            mmap.MAP_SHARED,
-            mmap.PROT_READ | mmap.PROT_WRITE,
-            offset=addr & ~MAP_MASK,
-        ) as mem:
-            start_addr = addr & MAP_MASK
-            stop_addr = start_addr + 4
-            mem[start_addr:stop_addr] = value_bytes
-            contents = mem[start_addr:stop_addr]
-    finally:
-        os.close(f)
+CH1_LOW_WORD_ADDR       =   DAC_BASE_ADDR + CH1_LOW_WORD_OFFSET

fast-servo/pyfastservo/dac.py

@@ -1,24 +1,11 @@
-# This file is part of Fast Servo Software Package.
-#
-# Copyright (C) 2023 Jakub Matyas
-# Warsaw University of Technology <jakubk.m@gmail.com>
-# SPDX-License-Identifier: GPL-3.0-or-later
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-# 
-# This program is distributed in the hope that it will be useful, 
-# but WITHOUT ANY WARRANTY; without even the implied warranty of 
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <https://www.gnu.org/licenses/>.
-
+import mmap
+import os
+import logging
 import time
 
+logging.basicConfig(level=logging.INFO)
+logger = logging.getLogger(__name__)
+
 import spidev
 from pyfastservo.common import (
     CH0_HIGH_WORD_ADDR,
@@ -28,13 +15,12 @@ from pyfastservo.common import (
     CTRL_ADDR,
     MAP_MASK,
     PAGESIZE,
-    write_to_memory,
-    read_from_memory
 )
 
 # /dev/spidev2.0  <=> spidev<BUS>.<DEVICE>
 MAIN_DAC_BUS = 2
 MAIN_DAC_DEVICE = 0
+
 DAC_VERSION = 0x0A
 
 
@@ -45,52 +31,200 @@ def spi_read(spi, address):
     rx_buffer = spi.xfer2([0x80 | address, 0x00])
     return rx_buffer[1]
 
-def soft_reset(spi):
+def hard_reset(spi):
     spi_write(spi, 0x00, 0x10)  # Software reset
     spi_write(spi, 0x00, 0x00)  # Release software reset
     spi_read(spi, 0x00)         # Read reset address (necessary for reset to take effect)
 
 def check_version(spi):
     version = spi_read(spi, 0x1F)
-    print(f"DAC version: 0x{version:02X}")
-    return version == DAC_VERSION
+    if version == DAC_VERSION:
+        print(f"Verified DAC version: 0x{version:02X}")
+    else:
+        print(f"Unrecognized device version: 0x{version:02X}")
 
-def configure_dac(spi):
-    power_down_reg = spi_read(spi, 0x01)
-    spi_write(spi, 0x01, power_down_reg & ~(1 << 0))  # Clear EXTREF bit for internal reference
-    spi_write(spi, 0x0D, 0x00)      # Set RREF to 10 kΩ for 1.0V reference
-    spi_write(spi, 0x04, 0xA0)      # Enable on-chip IRSET (1.6 kΩ for 20mA output)
-    spi_write(spi, 0x07, 0xA0)      # Enable on-chip QRSET (1.6 kΩ for 20mA output)
-    spi_write(spi, 0x05, 0x00)      # Disable internal IRCML
-    spi_write(spi, 0x08, 0x00)      # Disable internal QRCML
-    spi_write(spi, 0x02, 0xB4)      # Enable 2's complement, IFirst: True, IRising: True, DCI_EN: Enabled
-    spi_write(spi, 0x14, 0x00)      
-    spi_write(spi, 0x14, 0x08)      # Trigger the retimer to reacquire the clock relationship
-    spi_write(spi, 0x14, 0x00)
+def set_data_control_and_output_mode(spi, mode='differential'):
+    try:
+        current_reg = spi_read(spi, 0x02)
+        logger.info(f"Current data control register value: 0x{current_reg:02X}")
 
-def dac_self_calibration(spi):
-    spi_write(spi, 0x12, 0x00)      # Reset calibration status
-    spi_write(spi, 0x0E, 0x08)      # Enable calibration clock, default divide ratio
-    spi_write(spi, 0x0E, 0x38)      # CALSELI = 1, CALSELQ = 1, CALCLK = 1
-    spi_write(spi, 0x12, 0x10)      # Set CALEN bit
+        new_reg = 0xB4
 
-    while True:
-        status = spi_read(spi, 0x0F)
-        if status & 0xC0 == 0xC0:   # Both CALSTATI and CALSTATQ are 1
+        if mode == 'differential':
+            new_reg &= ~0x03
+        elif mode == 'single_ended':
+            new_reg = (new_reg & ~0x01) | 0x02
+        else:
+            logger.error(f"Invalid output mode: {mode}")
+            return
+
+        spi_write(spi, 0x02, new_reg)
+
+        verify_reg = spi_read(spi, 0x02)
+        if verify_reg == new_reg:
+            logger.info(f"Data control set and output mode successfully set to {mode}")
+            logger.info(f"New data control register value: 0x{verify_reg:02X}")
+        else:
+            logger.error(f"Failed to set data control and output mode. Expected: 0x{new_reg:02X}, Got: 0x{verify_reg:02X}")
+    except Exception as e:
+        logger.error(f"Error setting data control and output mode: {e}")
+
+
+def wait_for_clock_sync(spi):
+    max_attempts = 10
+    for attempt in range(max_attempts):
+        clkmode = spi_read(spi, 0x14)
+        if not clkmode & 0x10:
+            print(f"Clock synchronized after {attempt + 1} attempts")
             break
-        time.sleep(0.01)
+        if attempt == max_attempts - 1:
+            print("Warning: Clock synchronization not achieved")
+        time.sleep(0.001)
+
+
+def enable_dac_outputs(spi):
+    try:
+        # Read current power-down register value
+        power_down_reg = spi_read(spi, 0x01)
+        logger.info(f"Current power-down register value: 0x{power_down_reg:02X}")
+
+        if not (power_down_reg & ((1 << 4) | (1 << 3))):
+            logger.info("DAC outputs are already enabled")
+            return
+
+        new_power_down_reg = power_down_reg & ~((1 << 4) | (1 << 3))
+        spi_write(spi, 0x01, new_power_down_reg)
+
+        # Verify the write operation
+        verify_power_down_reg = spi_read(spi, 0x01)
+        if verify_power_down_reg == new_power_down_reg:
+            logger.info("DAC outputs successfully enabled")
+        else:
+            logger.error(f"Failed to enable DAC outputs. Expected: 0x{new_power_down_reg:02X}, Got: 0x{verify_power_down_reg:02X}")
+    except Exception as e:
+        logger.error(f"Error enabling DAC outputs: {e}")
+
+
+def set_dac_constant_output(value=0xFFFF):
+    try:
+        max_value = 0x3FFF  # 14-bit maximum (2^14 - 1)
+        value = min(value, max_value)
+        
+        # Split the value into high and low words
+        low_word_value = value & 0xFF
+        high_word_value = (value >> 8) & 0x3F
+        
+        # Write to Channel 0
+        write_to_memory(CH0_HIGH_WORD_ADDR, high_word_value)
+        write_to_memory(CH0_LOW_WORD_ADDR, low_word_value)
+        
+        # Write to Channel 1
+        write_to_memory(CH1_HIGH_WORD_ADDR, high_word_value)
+        write_to_memory(CH1_LOW_WORD_ADDR, low_word_value)
+        
+        logger.info(f"DAC outputs set to constant value: 0x{value:04X}")
+        logger.info("Please verify the output using an oscilloscope")
+        
+    except Exception as e:
+        logger.error(f"Error setting DAC constant output: {e}")
+
+
+def configure_dac_for_hardware(spi):
+    try:
+        # Enable internal reference
+        power_down_reg = spi_read(spi, 0x01)
+        power_down_reg &= ~(1 << 0)  # Clear EXTREF bit for internal reference
+        spi_write(spi, 0x01, power_down_reg)
+        logger.info("Internal reference enabled")
+
+        # Set RREF to default 10 kΩ for 1.0V reference
+        spi_write(spi, 0x0D, 0x00)
+        logger.info("RREF set to 10 kΩ for 1.0V reference")
+
+        # Enable on-chip IRSET and QRSET
+        irset_value = 0xA0                  # 10100000
+        spi_write(spi, 0x04, irset_value)   # IRSET
+        spi_write(spi, 0x07, irset_value)   # QRSET
+
+        # Disable internal termination resistors
+        ircml_value = 0x00
+        spi_write(spi, 0x05, ircml_value)  # IRCML
+        spi_write(spi, 0x08, ircml_value)  # QRCML
+
+        spi_write(spi, 0x02, 0xB4)
+
+        # Verify settings
+        irset_read = spi_read(spi, 0x04)
+        qrset_read = spi_read(spi, 0x07)
+        ircml_read = spi_read(spi, 0x05)
+        qrcml_read = spi_read(spi, 0x08)
+        data_control_read = spi_read(spi, 0x02)
+        
+        if (irset_read == irset_value and qrset_read == irset_value and
+            ircml_read == ircml_value and qrcml_read == ircml_value and
+            data_control_read == 0xB4):
+            logger.info("DAC configured for 20mA output with external termination")
+        else:
+            logger.error(f"DAC configuration failed. IRSET: 0x{irset_read:02X}, QRSET: 0x{qrset_read:02X}, "
+                         f"IRCML: 0x{ircml_read:02X}, QRCML: 0x{qrcml_read:02X}, "
+                         f"Data Control: 0x{data_control_read:02X}")
+
+    except Exception as e:
+        logger.error(f"Error configuring DAC: {e}")
+
+def read_from_memory(address, n_bytes):
+    assert n_bytes <= 4
+    addr = address
+
+    try:
+        f = os.open("/dev/mem", os.O_SYNC | os.O_RDWR)
+        with mmap.mmap(
+            f,
+            PAGESIZE,
+            mmap.MAP_SHARED,
+            mmap.PROT_READ | mmap.PROT_WRITE,
+            offset=addr & ~MAP_MASK,
+        ) as mem:
+            start_addr = addr & MAP_MASK
+            stop_addr = start_addr + 4
+            # print(f"addr: 0x{addr:x}\tstart_addr: 0x{start_addr}\tstop_addr: 0x{stop_addr}")
+            contents = mem[start_addr:stop_addr]
+            read_value = list(contents)[:n_bytes]
+    finally:
+        os.close(f)
+
+    return read_value
+
+
+def write_to_memory(address, value):
+    value_bytes = value.to_bytes(4, "little")
+    addr = address
+
+    try:
+        f = os.open("/dev/mem", os.O_SYNC | os.O_RDWR)
+        with mmap.mmap(
+            f,
+            PAGESIZE,
+            mmap.MAP_SHARED,
+            mmap.PROT_READ | mmap.PROT_WRITE,
+            offset=addr & ~MAP_MASK,
+        ) as mem:
+            start_addr = addr & MAP_MASK
+            stop_addr = start_addr + 4
+            mem[start_addr:stop_addr] = value_bytes
+            contents = mem[start_addr:stop_addr]
+    finally:
+        os.close(f)
 
-    spi_write(spi, 0x12, 0x00)      # Clear calibration bits
-    spi_write(spi, 0x0E, 0x30)      # Keep CALSELI and CALSELQ set, clear CALCLK
-    print("DAC self-calibration completed")
 
 def manual_override(enable=True):
     reg_contents = read_from_memory(CTRL_ADDR, 1)[0]
+    print(f"REG contents: 0b{reg_contents:03b}")
     to_write = reg_contents | 0b1 if enable else reg_contents & 0b110
     write_to_memory(CTRL_ADDR, to_write)
-    print(f"Set DAC Output Manual Override: {enable}")
 
-def power_down_afe(channel, power_down=True):
+
+def power_down(channel, power_down=True):
     assert channel in (0, 1)
 
     bitmask = 1 << (channel + 1) & 0b111
@@ -101,65 +235,51 @@ def power_down_afe(channel, power_down=True):
     to_write = reg_contents | value
     write_to_memory(CTRL_ADDR, to_write)
     reg_contents = read_from_memory(CTRL_ADDR, 1)[0]
-    print(f"Power Down DAC AFE Ch{channel}: {power_down}")
+    print(f"REG contents: 0b{reg_contents:03b}")
 
-def set_dac_output(value):
-    value = min(value, 0x3FFF)
-    low_word = value & 0xFF
-    high_word = (value >> 8) & 0x3F
-
-    write_to_memory(CH0_HIGH_WORD_ADDR, high_word)
-    write_to_memory(CH0_LOW_WORD_ADDR, low_word)
-    write_to_memory(CH1_HIGH_WORD_ADDR, high_word)
-    write_to_memory(CH1_LOW_WORD_ADDR, low_word)
-    print(f"DAC output set to: 0x{value:04X}")
-
-def check_clk_relationship(spi):
-    clkmode_reg = spi_read(spi, 0x14)
-    print(f"CLKMODE reg: 0x{clkmode_reg:02X}")
-    if clkmode_reg & 0b00010000:
-        print("Clock relationship is not found")
-        return False
-    else:
-        print("Clock relationship is found")
-        return True
-
-def configure_ad9117():
+def main_dac_init():
     spi = spidev.SpiDev()
-    spi.open(MAIN_DAC_BUS, MAIN_DAC_DEVICE)
-    spi.max_speed_hz = 5000
-    spi.mode = 0b00  # CPOL = 0 CPHA = 0
-    spi.cshigh = False
 
     try:
-        soft_reset(spi)
-        if not check_version(spi):
-            print("Unrecognized DAC version")
-            return False
+        spi.open(MAIN_DAC_BUS, MAIN_DAC_DEVICE)
+        spi.max_speed_hz = 5000
+        spi.mode = 0b00  # CPOL = 0 CPHA = 0
+        spi.cshigh = False
 
-        power_down_afe(0, True)
-        power_down_afe(1, True)
+        hard_reset(spi)
+        check_version(spi)
 
-        configure_dac(spi)
-        check_clk_relationship(spi)
-        dac_self_calibration(spi)
+        configure_dac_for_hardware(spi)
+        set_data_control_and_output_mode(spi, 'differential')
+        wait_for_clock_sync(spi)
+        enable_dac_outputs(spi)
 
-        # Enable DAC outputs
-        spi_write(spi, 0x01, spi_read(spi, 0x01) & ~((1 << 4) | (1 << 3)))
+        power_down(0, False)
+        power_down(1, False)
 
-        power_down_afe(0, False)
-        power_down_afe(1, False)
-        manual_override(False)
+        manual_override(True)
 
-        print("AD9117 configuration completed successfully")
-        return True
+        set_dac_constant_output(0x1FFF)
 
+        # Verify control register
+        reg_contents = read_from_memory(CTRL_ADDR, 1)[0]
+        logger.info(f"Control register contents after setting: 0b{reg_contents:03b}")
+
+        # Verify channel settings
+        ch0_high = read_from_memory(CH0_HIGH_WORD_ADDR, 1)[0]
+        ch0_low = read_from_memory(CH0_LOW_WORD_ADDR, 1)[0]
+        ch1_high = read_from_memory(CH1_HIGH_WORD_ADDR, 1)[0]
+        ch1_low = read_from_memory(CH1_LOW_WORD_ADDR, 1)[0]
+        logger.info(f"Channel 0: 0x{ch0_high:02X}{ch0_low:02X}, Channel 1: 0x{ch1_high:02X}{ch1_low:02X}")
     except Exception as e:
-        print(f"Error configuring AD9117: {e}")
-        return False
+        print(f"Error initializing DAC: {e}")
 
     finally:
         spi.close()
 
+
+def main():
+    main_dac_init()
+    
 if __name__ == "__main__":
-    configure_ad9117()
+    main()

fast-servo/pyfastservo/initialize.py

@@ -21,8 +21,8 @@ from pyfastservo import adc, si5340, dac
 
 def main():
     si5340.configure_si5340()
-    adc.configure_ltc2195()
-    dac.configure_ad9117()
+    adc.main()
+    dac.main()
 
 if __name__ == "__main__":
     main()

fast-servo/pyfastservo/loopback.py

@@ -0,0 +1,48 @@
+# This file is part of Fast Servo Software Package.
+#
+# Copyright (C) 2023 Jakub Matyas
+# Warsaw University of Technology <jakubk.m@gmail.com>
+# SPDX-License-Identifier: GPL-3.0-or-later
+
+from pyfastservo.dac import (
+    CH0_HIGH_WORD_ADDR,
+    CH0_LOW_WORD_ADDR,
+    CH1_HIGH_WORD_ADDR,
+    CH1_LOW_WORD_ADDR,
+    write_sample,
+    manual_override,
+    read_from_memory as dac_read_from_memory
+)
+from pyfastservo.adc import (
+    ADC_CH0_HIGH_ADDR,
+    ADC_CH0_LOW_ADDR,
+    ADC_CH1_HIGH_ADDR,
+    ADC_CH1_LOW_ADDR,
+    read_from_memory as adc_read_from_memory
+)
+
+def main():
+    # Apply manual override for DAC
+    manual_override(True)
+
+    # Write constant value to DAC channels
+    constant_value = 0x1FFF
+    write_sample(0, constant_value)
+    write_sample(1, constant_value)
+
+    # Verify DAC register values
+    dac_ch0 = (dac_read_from_memory(CH0_HIGH_WORD_ADDR, 1)[0] << 8) | dac_read_from_memory(CH0_LOW_WORD_ADDR, 1)[0]
+    dac_ch1 = (dac_read_from_memory(CH1_HIGH_WORD_ADDR, 1)[0] << 8) | dac_read_from_memory(CH1_LOW_WORD_ADDR, 1)[0]
+
+    print(f"DAC CH0: 0x{dac_ch0:04X}")
+    print(f"DAC CH1: 0x{dac_ch1:04X}")
+
+    # Read ADC values
+    adc_ch0 = (adc_read_from_memory(ADC_CH0_HIGH_ADDR, 1)[0] << 8) | adc_read_from_memory(ADC_CH0_LOW_ADDR, 1)[0]
+    adc_ch1 = (adc_read_from_memory(ADC_CH1_HIGH_ADDR, 1)[0] << 8) | adc_read_from_memory(ADC_CH1_LOW_ADDR, 1)[0]
+
+    print(f"ADC CH0: 0x{adc_ch0:04X}")
+    print(f"ADC CH1: 0x{adc_ch1:04X}")
+
+if __name__ == "__main__":
+    main()

flake.nix

@@ -481,7 +481,7 @@
         inherit migen misoc vivado;
       };
       packages.armv7l-linux = {
-        inherit fast-servo-gateware linien-server;
+        inherit fast-servo-gateware linien-server pyfastservo;
       } //
       (board-package-set { board = "zc706"; }) //
       (board-package-set { board = "fast-servo"; });

not-os-patches/network.patch

@@ -1,5 +1,5 @@
 diff --git a/configuration.nix b/configuration.nix
-index 010c487..2d08009 100644
+index 010c487..e1e85ba 100644
 --- a/configuration.nix
 +++ b/configuration.nix
 @@ -1,4 +1,4 @@
@@ -8,7 +8,7 @@ index 010c487..2d08009 100644
  
  {
    imports = [ ./qemu.nix ];
-@@ -7,10 +7,16 @@
+@@ -7,10 +7,15 @@
    environment.etc = {
      "ssh/authorized_keys.d/root" = {
        text = ''
@@ -18,7 +18,6 @@ index 010c487..2d08009 100644
 +        ecdsa-sha2-nistp384 AAAAE2VjZHNhLXNoYTItbmlzdHAzODQAAAAIbmlzdHAzODQAAABhBNdIiLvP2hmDUFyyE0oLOIXrjrMdWWpBV9/gPR5m4AiARx4JkufIDZzmptdYQ5FhJORJ4lluPqp7dAmahoSwg4lv9Di0iNQpHMJvNGZLHYKM1H1FWCCFIEDJ8bD4SVfrDg== root
 +        ecdsa-sha2-nistp384 AAAAE2VjZHNhLXNoYTItbmlzdHAzODQAAAAIbmlzdHAzODQAAABhBF/YybP+fQ0J+bNqM5Vgx5vDmVqVWsgUdF1moUxghv7d73GZAFaM6IFBdrXTAa33AwnWwDPMrTgP1V6SXBkb3ciJo/lD1urJGbydbSI5Ksq9d59wvOeANvyWYrQw6+eqTQ== sb
 +        ecdsa-sha2-nistp384 AAAAE2VjZHNhLXNoYTItbmlzdHAzODQAAAAIbmlzdHAzODQAAABhBFkmOCQ3BQh3qUjLtfdqyeBsx8rkk/QYlzB0TMrnfn6waLN6yKfPC3WVFv4zN5kNKb/OayvqDa+zfkKe85e/oIPQQKflF7GrCHdssz33DCnW90cz532E6iqG1pjeZjID2A== flo
-+        ssh-ed25519 AAAAC3NzaC1lZDI1NTE5AAAAICAranL376soiSJ0kxdYNrwElcaZPW1heLFjs8Y7n0jT linuswck
        '';
        mode = "0444";
      };

not-os-patches/pr-28.patch

@@ -152,7 +152,7 @@ index c61f9d6..fbdf0fd 100644
    };
  }
 diff --git a/zynq_image.nix b/zynq_image.nix
-index 3fa23ab..069fe89 100644
+index 3fa23ab..d5c5eda 100644
 --- a/zynq_image.nix
 +++ b/zynq_image.nix
 @@ -1,66 +1,89 @@
@@ -250,7 +250,7 @@ index 3fa23ab..069fe89 100644
 -  environment.etc."service/getty/run".source = pkgs.writeShellScript "getty" ''
 -    agetty ttyPS0 115200
 +  environment = {
-+    systemPackages = with pkgs; [ inetutils wget gnugrep nano vim ];
++    systemPackages = with pkgs; [ inetutils wget nano ];
 +    etc = {
 +      "service/getty/run".source = pkgs.writeShellScript "getty" ''
 +        hostname ${config.networking.hostName}