pyfastservo: update initialize script

pyfastservo: fix adc init script and cleanup
pyfastservo: fix dac init script and cleanup
2024-07-10 15:45:51 +08:00 · 2024-07-10 15:45:51 +08:00 · 2024-07-10 15:45:45 +08:00 · 2024-07-10 14:23:52 +08:00
45 changed files with 590 additions and 1892 deletions
--- a/README.md
+++ b/README.md
@ -1,60 +0,0 @@
 # Firmware for the Sinara 8462 Fast-Servo
 ## Networking Ports
 | Usage         | Port Number |
 |---------------|-------------|
 | ssh           | 3030        |
 | linien-server | 18862       |
 ## Building
 ### Reproducible build with Nix
 1. Run `nix build .#packages.armv7l-linux.fast-servo-sd-image` to build the sd card image.
 2. Run `nix build .#packages.armv7l-linux.fast-servo-gui` to build the GUI
 3. Run `nix develop` to build a dev shell having access the GUI.
 ### Flashing
 1. Plug in your SD card to your computer and run `lsblk` to locate SD card
 2. If there are any partitions on the SD card, run `umount <mount point>` all the related mount points.
 3. Run `sudo dd if=<path to the SD Card Image> of=/dev/<SD Card Device Name in lsblk> bs=4M status=progress oflag=sync`
 4. Eject the SD Card before removal
 ## Configuration
 You can modify the followings by altering the files directly on the SD card. You can do that by inserting the SD card to a computer in Linux Operating system.
 1. Network Settings
 - File Location: /etc/ip_setup
 - Description: It contains the network setup script that is run once during initialization. You can add any network related to scripts to this file.
 2. SSH Public Key
 - File Location: /etc/ssh/authorized_keys.d/root
 - Description: SSH Public key authentication file.
 You should append the ssh public key of your PC here with hostname removed.
 - Instructions:
    1. Run `ssh-keygen`
    2. Type a filename for key to be saved. Let's say `foo`.
    3. Type `Return(Enter)` twice when it asks for your passphrase. Fast-servo's ssh authentication is passwordless.
    4. Open the generated public key file `foo.pub`.
    5. Append the public key to the file `/etc/ssh/authorized_keys.d/root` with `@hostname` removed. 
        Sample ssh public key: `ssh-ed25519 xxx...xxx username@hostname`
 ## Usage
 1. Make sure the onboard DIP Switch is in the following condition.
    - EN: OFF
    - MODE: ON
 2. Install the SD Card, power up the board via the power jack or PoE and plug in the RJ45 Ethernet cable.
 3. Wait for all the front panel LEDs except the termination status LEDs to turn off. It can take a minutes or two for first boot. If it does not boot up, try to flash the SD Card again.
 4. By default, linien-server starts up automatically. In case linien-server crashes, it will restart itself. Logs are stored in `/root/linien-server-log`. 
 ssh access is not required for linien client if linien-server is started. If not, then linien client will ssh into the fast-servo device to start the linien-server service.
    Here are some commands to interact with the linien-server service once you `ssh <fast servo ip address> -p 3030` into fast-servo. 
 | Description                                          | Command                                 |
 |------------------------------------------------------|-----------------------------------------|
 | Start the linien-server service                      | `linien-server start`                   |
 | Stop the linien-server service                       | `linien-server stop`                    |
 | Check if the linien-server service is running        | `linien-server status`                  |
 | Set the linien-server service to start at bootup     | `linien-server enable`                  |
 | Set the linien-server service not to start at bootup | `linien-server disable`                 |
 4. In the dev shell, run `linien` to launch the GUI. Add new device. Username is `root`.
 5. Select the newly added device and click connect in the GUI to connect and start the GUI.
--- a/fast-servo/fast-servo.dts
+++ b/fast-servo/fast-servo.dts
@ -576,7 +576,7 @@
 / {
 cpus {
  cpu@0 {
-   operating-points = <666667 1000000 333334 1000000>;
+   operating-points = <500000 1000000 250000 1000000>;
  };
 };
 };
--- a/fast-servo/fsbl-support/ps7_init.c
+++ b/fast-servo/fsbl-support/ps7_init.c
@ -25,23 +25,23 @@ unsigned long ps7_pll_init_data_3_0[] = {
    // .. FINISH: SLCR SETTINGS
    // .. START: PLL SLCR REGISTERS
    // .. .. START: ARM PLL INIT
-    // .. .. PLL_RES = 0x2
+    // .. .. PLL_RES = 0xc
-    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. .. ==> 0XF8000110[7:4] = 0x0000000CU
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
    // .. .. PLL_CP = 0x2
    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0xfa
+    // .. .. LOCK_CNT = 0x145
-    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. .. ==> 0XF8000110[21:12] = 0x00000145U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
    // .. .. 
-    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001452C0U),
    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. PLL_FDIV = 0x1e
-    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. .. ==> 0XF8000100[18:12] = 0x0000001EU
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001E000U),
    // .. .. .. FINISH: UPDATE FB_DIV
    // .. .. .. START: BY PASS PLL
    // .. .. .. PLL_BYPASS_FORCE = 1
@ -273,9 +273,9 @@ unsigned long ps7_clock_init_data_3_0[] = {
    // .. CLKACT = 0x1
    // .. ==> 0XF8000140[0:0] = 0x00000001U
    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
+    // .. SRCSEL = 0x2
-    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // .. ==> 0XF8000140[6:4] = 0x00000002U
-    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000020U
    // .. DIVISOR = 0x8
    // .. ==> 0XF8000140[13:8] = 0x00000008U
    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
@ -283,7 +283,7 @@ unsigned long ps7_clock_init_data_3_0[] = {
    // .. ==> 0XF8000140[25:20] = 0x00000001U
    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
    // .. 
-    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100821U),
    // .. CLKACT = 0x1
    // .. ==> 0XF800014C[0:0] = 0x00000001U
    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
@ -4054,23 +4054,23 @@ unsigned long ps7_pll_init_data_2_0[] = {
    // .. FINISH: SLCR SETTINGS
    // .. START: PLL SLCR REGISTERS
    // .. .. START: ARM PLL INIT
-    // .. .. PLL_RES = 0x2
+    // .. .. PLL_RES = 0xc
-    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. .. ==> 0XF8000110[7:4] = 0x0000000CU
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
    // .. .. PLL_CP = 0x2
    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0xfa
+    // .. .. LOCK_CNT = 0x145
-    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. .. ==> 0XF8000110[21:12] = 0x00000145U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
    // .. .. 
-    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001452C0U),
    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. PLL_FDIV = 0x1e
-    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. .. ==> 0XF8000100[18:12] = 0x0000001EU
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001E000U),
    // .. .. .. FINISH: UPDATE FB_DIV
    // .. .. .. START: BY PASS PLL
    // .. .. .. PLL_BYPASS_FORCE = 1
@ -4302,9 +4302,9 @@ unsigned long ps7_clock_init_data_2_0[] = {
    // .. CLKACT = 0x1
    // .. ==> 0XF8000140[0:0] = 0x00000001U
    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
+    // .. SRCSEL = 0x2
-    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // .. ==> 0XF8000140[6:4] = 0x00000002U
-    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000020U
    // .. DIVISOR = 0x8
    // .. ==> 0XF8000140[13:8] = 0x00000008U
    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
@ -4312,7 +4312,7 @@ unsigned long ps7_clock_init_data_2_0[] = {
    // .. ==> 0XF8000140[25:20] = 0x00000001U
    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
    // .. 
-    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100821U),
    // .. CLKACT = 0x1
    // .. ==> 0XF800014C[0:0] = 0x00000001U
    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
@ -8236,23 +8236,23 @@ unsigned long ps7_pll_init_data_1_0[] = {
    // .. FINISH: SLCR SETTINGS
    // .. START: PLL SLCR REGISTERS
    // .. .. START: ARM PLL INIT
-    // .. .. PLL_RES = 0x2
+    // .. .. PLL_RES = 0xc
-    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. .. ==> 0XF8000110[7:4] = 0x0000000CU
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
    // .. .. PLL_CP = 0x2
    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0xfa
+    // .. .. LOCK_CNT = 0x145
-    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. .. ==> 0XF8000110[21:12] = 0x00000145U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
    // .. .. 
-    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001452C0U),
    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. PLL_FDIV = 0x1e
-    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. .. ==> 0XF8000100[18:12] = 0x0000001EU
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001E000U),
    // .. .. .. FINISH: UPDATE FB_DIV
    // .. .. .. START: BY PASS PLL
    // .. .. .. PLL_BYPASS_FORCE = 1
@ -8484,9 +8484,9 @@ unsigned long ps7_clock_init_data_1_0[] = {
    // .. CLKACT = 0x1
    // .. ==> 0XF8000140[0:0] = 0x00000001U
    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
+    // .. SRCSEL = 0x2
-    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // .. ==> 0XF8000140[6:4] = 0x00000002U
-    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000020U
    // .. DIVISOR = 0x8
    // .. ==> 0XF8000140[13:8] = 0x00000008U
    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
@ -8494,7 +8494,7 @@ unsigned long ps7_clock_init_data_1_0[] = {
    // .. ==> 0XF8000140[25:20] = 0x00000001U
    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
    // .. 
-    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100821U),
    // .. CLKACT = 0x1
    // .. ==> 0XF800014C[0:0] = 0x00000001U
    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
--- a/fast-servo/fsbl-support/ps7_init_gpl.c
+++ b/fast-servo/fsbl-support/ps7_init_gpl.c
@ -38,23 +38,23 @@ unsigned long ps7_pll_init_data_3_0[] = {
    // .. FINISH: SLCR SETTINGS
    // .. START: PLL SLCR REGISTERS
    // .. .. START: ARM PLL INIT
-    // .. .. PLL_RES = 0x2
+    // .. .. PLL_RES = 0xc
-    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. .. ==> 0XF8000110[7:4] = 0x0000000CU
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
    // .. .. PLL_CP = 0x2
    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0xfa
+    // .. .. LOCK_CNT = 0x145
-    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. .. ==> 0XF8000110[21:12] = 0x00000145U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
    // .. .. 
-    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001452C0U),
    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. PLL_FDIV = 0x1e
-    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. .. ==> 0XF8000100[18:12] = 0x0000001EU
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001E000U),
    // .. .. .. FINISH: UPDATE FB_DIV
    // .. .. .. START: BY PASS PLL
    // .. .. .. PLL_BYPASS_FORCE = 1
@ -286,9 +286,9 @@ unsigned long ps7_clock_init_data_3_0[] = {
    // .. CLKACT = 0x1
    // .. ==> 0XF8000140[0:0] = 0x00000001U
    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
+    // .. SRCSEL = 0x2
-    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // .. ==> 0XF8000140[6:4] = 0x00000002U
-    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000020U
    // .. DIVISOR = 0x8
    // .. ==> 0XF8000140[13:8] = 0x00000008U
    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
@ -296,7 +296,7 @@ unsigned long ps7_clock_init_data_3_0[] = {
    // .. ==> 0XF8000140[25:20] = 0x00000001U
    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
    // .. 
-    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100821U),
    // .. CLKACT = 0x1
    // .. ==> 0XF800014C[0:0] = 0x00000001U
    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
@ -4067,23 +4067,23 @@ unsigned long ps7_pll_init_data_2_0[] = {
    // .. FINISH: SLCR SETTINGS
    // .. START: PLL SLCR REGISTERS
    // .. .. START: ARM PLL INIT
-    // .. .. PLL_RES = 0x2
+    // .. .. PLL_RES = 0xc
-    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. .. ==> 0XF8000110[7:4] = 0x0000000CU
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
    // .. .. PLL_CP = 0x2
    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0xfa
+    // .. .. LOCK_CNT = 0x145
-    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. .. ==> 0XF8000110[21:12] = 0x00000145U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
    // .. .. 
-    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001452C0U),
    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. PLL_FDIV = 0x1e
-    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. .. ==> 0XF8000100[18:12] = 0x0000001EU
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001E000U),
    // .. .. .. FINISH: UPDATE FB_DIV
    // .. .. .. START: BY PASS PLL
    // .. .. .. PLL_BYPASS_FORCE = 1
@ -4315,9 +4315,9 @@ unsigned long ps7_clock_init_data_2_0[] = {
    // .. CLKACT = 0x1
    // .. ==> 0XF8000140[0:0] = 0x00000001U
    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
+    // .. SRCSEL = 0x2
-    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // .. ==> 0XF8000140[6:4] = 0x00000002U
-    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000020U
    // .. DIVISOR = 0x8
    // .. ==> 0XF8000140[13:8] = 0x00000008U
    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
@ -4325,7 +4325,7 @@ unsigned long ps7_clock_init_data_2_0[] = {
    // .. ==> 0XF8000140[25:20] = 0x00000001U
    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
    // .. 
-    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100821U),
    // .. CLKACT = 0x1
    // .. ==> 0XF800014C[0:0] = 0x00000001U
    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
@ -8249,23 +8249,23 @@ unsigned long ps7_pll_init_data_1_0[] = {
    // .. FINISH: SLCR SETTINGS
    // .. START: PLL SLCR REGISTERS
    // .. .. START: ARM PLL INIT
-    // .. .. PLL_RES = 0x2
+    // .. .. PLL_RES = 0xc
-    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. .. ==> 0XF8000110[7:4] = 0x0000000CU
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
    // .. .. PLL_CP = 0x2
    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0xfa
+    // .. .. LOCK_CNT = 0x145
-    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. .. ==> 0XF8000110[21:12] = 0x00000145U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
    // .. .. 
-    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001452C0U),
    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. PLL_FDIV = 0x1e
-    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. .. ==> 0XF8000100[18:12] = 0x0000001EU
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001E000U),
    // .. .. .. FINISH: UPDATE FB_DIV
    // .. .. .. START: BY PASS PLL
    // .. .. .. PLL_BYPASS_FORCE = 1
@ -8497,9 +8497,9 @@ unsigned long ps7_clock_init_data_1_0[] = {
    // .. CLKACT = 0x1
    // .. ==> 0XF8000140[0:0] = 0x00000001U
    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
+    // .. SRCSEL = 0x2
-    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // .. ==> 0XF8000140[6:4] = 0x00000002U
-    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000020U
    // .. DIVISOR = 0x8
    // .. ==> 0XF8000140[13:8] = 0x00000008U
    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
@ -8507,7 +8507,7 @@ unsigned long ps7_clock_init_data_1_0[] = {
    // .. ==> 0XF8000140[25:20] = 0x00000001U
    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
    // .. 
-    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100821U),
    // .. CLKACT = 0x1
    // .. ==> 0XF800014C[0:0] = 0x00000001U
    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
--- a/fast-servo/fsbl.patch
+++ b/fast-servo/fsbl.patch
@ -1,8 +1,14 @@
-diff --git a/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init.h b/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init.h
+diff --git a/lib/sw_apps/zynq_fsbl/misc/fast-servo/ps7_init.h b/lib/sw_apps/zynq_fsbl/misc/fast-servo/ps7_init.h
-index 9572636..1d79314 100644
+index 9572636306..2f3816271e 100644
--- a/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init.h
+--- a/lib/sw_apps/zynq_fsbl/misc/fast-servo/ps7_init.h
-+++ b/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init.h
+++ b/lib/sw_apps/zynq_fsbl/misc/fast-servo/ps7_init.h
-@@ -72,20 +72,20 @@ extern unsigned long  * ps7_peripherals_init_data;
+@@ -67,20 +67,20 @@ extern unsigned long  * ps7_peripherals_init_data;
 /* Freq of all peripherals */
 -#define APU_FREQ  666666687
 +#define APU_FREQ  500000000
 #define DDR_FREQ  533333374
 #define DCI_FREQ  10158730
 #define QSPI_FREQ  200000000
 #define SMC_FREQ  10000000
@ -14,25 +20,27 @@ index 9572636..1d79314 100644
 -#define SDIO_FREQ  50000000
 -#define UART_FREQ  50000000
 -#define SPI_FREQ  10000000
 -#define I2C_FREQ  111111115
 -#define WDT_FREQ  111111115
 +#define SDIO_FREQ  100000000
 +#define UART_FREQ  100000000
 +#define SPI_FREQ  166666672
- #define I2C_FREQ  111111115
+#define I2C_FREQ  83333336
- #define WDT_FREQ  111111115
+#define WDT_FREQ  83333336
 #define TTC_FREQ  50000000
 #define CAN_FREQ  10000000
 #define PCAP_FREQ  200000000
- #define TPIU_FREQ  200000000
+diff --git a/lib/sw_apps/zynq_fsbl/misc/fast-servo/ps7_init_gpl.h b/lib/sw_apps/zynq_fsbl/misc/fast-servo/ps7_init_gpl.h
-#define FPGA0_FREQ  50000000
+index 8962bed427..df2f16adec 100644
-+#define FPGA0_FREQ  10000000
+--- a/lib/sw_apps/zynq_fsbl/misc/fast-servo/ps7_init_gpl.h
- #define FPGA1_FREQ  10000000
+++ b/lib/sw_apps/zynq_fsbl/misc/fast-servo/ps7_init_gpl.h
- #define FPGA2_FREQ  10000000
+@@ -81,20 +81,20 @@ extern unsigned long  * ps7_peripherals_init_data;
- #define FPGA3_FREQ  10000000
+ 
-diff --git a/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init_gpl.h b/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init_gpl.h
+ /* Freq of all peripherals */
-index 8962bed..562d5b5 100644
+ 
--- a/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init_gpl.h
+-#define APU_FREQ  666666687
-+++ b/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init_gpl.h
+#define APU_FREQ  500000000
-@@ -86,20 +86,20 @@ extern unsigned long  * ps7_peripherals_init_data;
+ #define DDR_FREQ  533333374
 #define DCI_FREQ  10158730
 #define QSPI_FREQ  200000000
 #define SMC_FREQ  10000000
@ -44,37 +52,33 @@ index 8962bed..562d5b5 100644
 -#define SDIO_FREQ  50000000
 -#define UART_FREQ  50000000
 -#define SPI_FREQ  10000000
 -#define I2C_FREQ  111111115
 -#define WDT_FREQ  111111115
 +#define SDIO_FREQ  100000000
 +#define UART_FREQ  100000000
 +#define SPI_FREQ  166666672
- #define I2C_FREQ  111111115
+#define I2C_FREQ  83333336
- #define WDT_FREQ  111111115
+#define WDT_FREQ  83333336
 #define TTC_FREQ  50000000
 #define CAN_FREQ  10000000
 #define PCAP_FREQ  200000000
 #define TPIU_FREQ  200000000
 -#define FPGA0_FREQ  50000000
 +#define FPGA0_FREQ  10000000
 #define FPGA1_FREQ  10000000
 #define FPGA2_FREQ  10000000
 #define FPGA3_FREQ  10000000
 diff --git a/lib/sw_apps/zynq_fsbl/misc/fast-servo/xparameters.h b/lib/sw_apps/zynq_fsbl/misc/fast-servo/xparameters.h
 index 997a982ca1..5461fbb477 100644
--- a/lib/sw_apps/zynq_fsbl/misc/fast-servo/xparameters 
+--- a/lib/sw_apps/zynq_fsbl/misc/fast-servo/xparameters.h
 +++ b/lib/sw_apps/zynq_fsbl/misc/fast-servo/xparameters.h
@@ -9,21 +9,26 @@
 #define XPAR_CPU_ID 0U
 /* Definitions for peripheral PS7_CORTEXA9_0 */
 -#define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
-+#define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
+#define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 500000000
 /******************************************************************/
 /* Canonical definitions for peripheral PS7_CORTEXA9_0 */
 -#define XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
-+#define XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
+#define XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ 500000000
 /******************************************************************/
--- a/fast-servo/linien-client-ssh-port-change.patch
+++ b/fast-servo/linien-client-ssh-port-change.patch
@ -1,31 +0,0 @@
 diff --git a/linien-client/linien_client/deploy.py b/linien-client/linien_client/deploy.py
 index df6683f..7355cc3 100644
 --- a/linien-client/linien_client/deploy.py
 +++ b/linien-client/linien_client/deploy.py
@@ -34,7 +34,7 @@ logger.setLevel(logging.DEBUG)
 def read_remote_version(
 -    device: Device, ssh_port: int = 22, out_stream=sys.stdout
 +    device: Device, ssh_port: int = 3030, out_stream=sys.stdout
 ) -> str:
     """Read the remote version of linien."""
@@ -62,7 +62,7 @@ def read_remote_version(
 def start_remote_server(
 -    device: Device, ssh_port: int = 22, out_stream=sys.stdout
 +    device: Device, ssh_port: int = 3030, out_stream=sys.stdout
 ) -> None:
     """Start the remote linien server."""
@@ -102,7 +102,7 @@ def start_remote_server(
 def install_remote_server(
 -    device: Device, ssh_port: int = 22, out_stream=sys.stdout
 +    device: Device, ssh_port: int = 3030, out_stream=sys.stdout
 ) -> None:
     """Install the remote linien server."""
--- a/fast-servo/linien-common-fast-servo-hardware-specific.patch
+++ b/fast-servo/linien-common-fast-servo-hardware-specific.patch
@ -1,15 +0,0 @@
 diff --git a/linien-common/linien_common/common.py b/linien-common/linien_common/common.py
 index 854d776..a310dbe 100644
 --- a/linien-common/linien_common/common.py
 +++ b/linien-common/linien_common/common.py
@@ -25,8 +25,8 @@ from typing import Dict, Iterable, List, Tuple, Union
 import numpy as np
 from scipy.signal import correlate, resample
 -MHz = 0x10000000 / 8
 -Vpp = ((1 << 14) - 1) / 4
 +MHz = 0x10000000 / 8
 +Vpp = (1 << 14 - 1) / 0.355 * 0.85
 # conversion of bits to V
 ANALOG_OUT_V = 1.8 / ((2**15) - 1)
--- a/fast-servo/linien-demodulate_add_pipeline.patch
+++ b/fast-servo/linien-demodulate_add_pipeline.patch
@ -1,21 +0,0 @@
 diff --git a/gateware/logic/modulate.py b/gateware/logic/modulate.py
 index c750306..ffba1b2 100644
 --- a/gateware/logic/modulate.py
 +++ b/gateware/logic/modulate.py
@@ -45,12 +45,14 @@ class Demodulate(Module, AutoCSR):
             cordic_mode="rotate",
             func_mode="circular",
         )
 -        self.comb += [
 +        self.sync += [
             # cordic input
             self.cordic.xi.eq(self.x),
             self.cordic.zi.eq(
                 ((self.phase * self.multiplier.storage) + self.delay.storage) << 1
 -            ),
 +            )
 +        ]
 +        self.comb += [
             # cordic output
             self.i.eq(self.cordic.xo >> 1),
             self.q.eq(self.cordic.yo >> 1),
--- a/fast-servo/linien-fast-servo-gateware.patch
+++ b/fast-servo/linien-fast-servo-gateware.patch
@ -0,0 +1,38 @@
 # diff from elhep/Fast-Servo-Firmmware commit ID 7fae40c:
 # https://github.com/elhep/Fast-Servo-Firmware/commit/7fae40c0f872a91218be378f8289b98b1e366729
 # Fix for migen add_source deprecation and removed xilinx bootgen command
 # .bin file is being generated by bit2bin.py from Linien repository
 # https://github.com/linien-org/linien/blob/master/gateware/bit2bin.py 
 diff --git a/fast_servo/gateware/fast_servo_platform.py b/fast_servo/gateware/fast_servo_platform.py
 index 13b4aa3..89a8103 100644
 --- a/fast_servo/gateware/fast_servo_platform.py
 +++ b/fast_servo/gateware/fast_servo_platform.py
@@ -324,7 +324,12 @@ class Platform(XilinxPlatform):
         self.ps7_config = ps7_config
         verilog_sources = os.listdir(verilog_dir)
 -        self.add_sources(verilog_dir, *verilog_sources)
 +        self.add_source_dir(verilog_dir)
 +
 +    def build(self, *args, **kwargs):
 +        build_dir = kwargs.get('build_dir', 'build')
 +        self.copy_sources(build_dir)
 +        super().build(*args, **kwargs)
     def do_finalize(self, fragment):
         try:
 diff --git a/fast_servo/gateware/fast_servo_soc.py b/fast_servo/gateware/fast_servo_soc.py
 index 02128f5..abfc583 100644
 --- a/fast_servo/gateware/fast_servo_soc.py
 +++ b/fast_servo/gateware/fast_servo_soc.py
@@ -282,9 +282,3 @@ if __name__ == "__main__":
     os.chdir(os.path.join(root_path, build_dir))
     with open(f"{build_name}.bif", "w") as f:
         f.write(f"all:\n{{\n\t{build_name}.bit\n}}")
 -    
 -    cmd = f"bootgen -image {build_name}.bif -arch zynq -process_bitstream bin -w on".split(" ")
 -    subprocess.run(cmd)
 -
 -    
 -
--- a/fast-servo/linien-gateware-fast-servo.patch
+++ b/fast-servo/linien-gateware-fast-servo.patch
@ -1,42 +1,3 @@
 # diff from elhep/Fast-Servo-Firmmware commit ID 7fae40c:
 # https://github.com/elhep/Fast-Servo-Firmware/commit/7fae40c0f872a91218be378f8289b98b1e366729
 # Fix for migen add_source deprecation and removed xilinx bootgen command
 # .bin file is being generated by bit2bin.py from Linien repository
 # https://github.com/linien-org/linien/blob/master/gateware/bit2bin.py 
 diff --git a/fast_servo/gateware/fast_servo_platform.py b/fast_servo/gateware/fast_servo_platform.py
 index 13b4aa3..89a8103 100644
 --- a/fast_servo/gateware/fast_servo_platform.py
 +++ b/fast_servo/gateware/fast_servo_platform.py
@@ -324,7 +324,12 @@ class Platform(XilinxPlatform):
         self.ps7_config = ps7_config
         verilog_sources = os.listdir(verilog_dir)
 -        self.add_sources(verilog_dir, *verilog_sources)
 +        self.add_source_dir(verilog_dir)
 +
 +    def build(self, *args, **kwargs):
 +        build_dir = kwargs.get('build_dir', 'build')
 +        self.copy_sources(build_dir)
 +        super().build(*args, **kwargs)
     def do_finalize(self, fragment):
         try:
 diff --git a/fast_servo/gateware/fast_servo_soc.py b/fast_servo/gateware/fast_servo_soc.py
 index 02128f5..abfc583 100644
 --- a/fast_servo/gateware/fast_servo_soc.py
 +++ b/fast_servo/gateware/fast_servo_soc.py
@@ -282,9 +282,3 @@ if __name__ == "__main__":
     os.chdir(os.path.join(root_path, build_dir))
     with open(f"{build_name}.bif", "w") as f:
         f.write(f"all:\n{{\n\t{build_name}.bit\n}}")
 -    
 -    cmd = f"bootgen -image {build_name}.bif -arch zynq -process_bitstream bin -w on".split(" ")
 -    subprocess.run(cmd)
 -
 -    
 -
 # diff between linen-org/linien commit ID 93f1f50:
 # https://github.com/linien-org/linien/commit/93f1f50ebd86fe3314cab5a549462d0fcbf6a658
 # and elhep/linien commit ID b73eea0:
@ -55,27 +16,41 @@ index b3f3683..98c6e51 100644
   - repo: https://github.com/pycqa/isort
     rev: 5.12.0
 diff --git a/gateware/build_fpga_image.sh b/gateware/build_fpga_image.sh
 index f822402..be7401c 100644
 --- a/gateware/build_fpga_image.sh
 +++ b/gateware/build_fpga_image.sh
@@ -16,4 +16,9 @@ export PATH=$VIVADOPATH:$PATH
 rm linien-server/linien_server/gateware.bin -f
 # run with -m option to avoid errors related to relative imports without breaking pytest
 -python3 -m gateware.fpga_image_helper
 \ No newline at end of file
 +
 +if [ -z "$1" ]; then
 +    python3 -m gateware.fpga_image_helper
 +else
 +    python3 -m gateware.fpga_image_helper -p $1
 +fi
 \ No newline at end of file
 diff --git a/gateware/fpga_image_helper.py b/gateware/fpga_image_helper.py
-index c3e20e7..ebead1d 100644
+index 6c34429..a0b12d0 100644
 --- a/gateware/fpga_image_helper.py
 +++ b/gateware/fpga_image_helper.py
-@@ -1,6 +1,7 @@
+@@ -1,5 +1,6 @@
- # This file is part of Linien and based on redpid.
+ # Copyright 2014-2015 Robert Jördens <jordens@gmail.com>
- #
+ # Copyright 2018-2022 Benjamin Wiegand <benjamin.wiegand@physik.hu-berlin.de>
 # Copyright (C) 2016-2024 Linien Authors (https://github.com/linien-org/linien#license)
 +# Copyright 2023 Jakub Matyas <jakubk.m@gmail.com>
 #
- # Linien is free software: you can redistribute it and/or modify
+ # This file is part of Linien and based on redpid.
- # it under the terms of the GNU General Public License as published by
+ #
-@@ -20,16 +21,18 @@
+@@ -23,14 +24,16 @@ from pathlib import Path
- from pathlib import Path
+ REPO_ROOT_DIR = Path(__file__).resolve().parents[1]
 from .bit2bin import bit2bin
 -from .hw_platform import Platform
 -from .linien_module import RootModule
 REPO_ROOT_DIR = Path(__file__).resolve().parents[1]
 def py_csrconstants(map, fil):
     fil.write("csr_constants = {\n")
@ -90,7 +65,7 @@ index c3e20e7..ebead1d 100644
     fil.write("}\n\n")
-@@ -51,26 +54,51 @@ def get_csrmap(banks):
+@@ -52,26 +55,49 @@ def get_csrmap(banks):
 def py_csrmap(it, fil):
     fil.write("csr = {\n")
     for reg in it:
@ -109,7 +84,7 @@ index c3e20e7..ebead1d 100644
 -    platform = Platform()
 -    root = RootModule(platform)
 +    import argparse
-+
+ 
 +    parser = argparse.ArgumentParser()
 +    parser.add_argument("-p", "--platform", default=None)
 +    args = parser.parse_args()
@ -128,11 +103,10 @@ index c3e20e7..ebead1d 100644
 +        root = LinienFastServo(platform)
 +    else:
 +        raise ValueError("Unknown platform")
-+    
+
 +    platform.add_source_dir(REPO_ROOT_DIR / "gateware" / "verilog")
 +    build_dir = REPO_ROOT_DIR / "gateware" / "build"
 +    platform.build(root, build_name="top", build_dir=build_dir, run=True)
     with open(
         REPO_ROOT_DIR / "linien-server" / "linien_server" / "csrmap.py", "w"
     ) as fil:
@ -143,7 +117,7 @@ index c3e20e7..ebead1d 100644
         py_csrmap(csr, fil)
         fil.write("states = {}\n".format(repr(root.linien.state_names)))
         fil.write("signals = {}\n".format(repr(root.linien.signal_names)))
- 
+-
 -    platform.add_source_dir(REPO_ROOT_DIR / "gateware" / "verilog")
 -    build_dir = REPO_ROOT_DIR / "gateware" / "build"
 -    platform.build(root, build_name="top", build_dir=build_dir)
@ -154,14 +128,14 @@ diff --git a/gateware/linien_module.py b/gateware/linien_module.py
 index 16ca186..6905ac0 100644
 --- a/gateware/linien_module.py
 +++ b/gateware/linien_module.py
-@@ -1,6 +1,7 @@
+@@ -2,6 +2,7 @@
- # This file is part of Linien and based on redpid.
+ # Copyright 2018-2022 Benjamin Wiegand <benjamin.wiegand@physik.hu-berlin.de>
- #
+ # Copyright 2021-2023 Bastian Leykauf <leykauf@physik.hu-berlin.de>
- # Copyright (C) 2016-2024 Linien Authors (https://github.com/linien-org/linien#license)
+ # Copyright 2022 Christian Freier <christian.freier@nomadatomics.com>
 +# Copyright 2023 Jakub Matyas <jakubk.m@gmail.com>
 #
- # Linien is free software: you can redistribute it and/or modify
+ # This file is part of Linien and based on redpid.
- # it under the terms of the GNU General Public License as published by
+ #
@@ -36,19 +37,13 @@ from misoc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage
 from .logic.autolock import FPGAAutolock
 from .logic.chains import FastChain, SlowChain, cross_connect
--- a/fast-servo/linien-gateware-autolock-pipeline.patch
+++ b/fast-servo/linien-gateware-autolock-pipeline.patch
@ -1,88 +0,0 @@
 diff --git a/gateware/logic/autolock.py b/gateware/logic/autolock.py
 index a6dc764..975b23f 100644
 --- a/gateware/logic/autolock.py
 +++ b/gateware/logic/autolock.py
@@ -148,14 +148,17 @@ class RobustAutolock(Module, AutoCSR):
         final_waited_for = Signal(bits_for(N_points))
         # this is the signal that's used for detecting peaks
 -        sum_diff = Signal((len(self.sum_diff_calculator.output), True))
 -        abs_sum_diff = Signal.like(sum_diff)
 +        self.sum_diff = Signal((len(self.sum_diff_calculator.output), True))
 +        abs_sum_diff = Signal.like(self.sum_diff)
         self.comb += [
             self.sum_diff_calculator.writing_data_now.eq(self.writing_data_now),
             self.sum_diff_calculator.restart.eq(self.at_start),
             self.sum_diff_calculator.input.eq(self.input),
             self.sum_diff_calculator.delay_value.eq(self.time_scale.storage),
 -            sum_diff.eq(self.sum_diff_calculator.output),
 +        ]
 +
 +        self.sync += [
 +            self.sum_diff.eq(self.sum_diff_calculator.output),
         ]
         # has this signal at the moment the same sign as the peak we are looking for?
@@ -167,36 +170,41 @@ class RobustAutolock(Module, AutoCSR):
         # have we detected all peaks (and can turn on the lock)?
         all_instructions_triggered = Signal()
 -        self.comb += [
 -            sign_equal.eq((sum_diff > 0) == (current_peak_height > 0)),
 -            If(sum_diff >= 0, abs_sum_diff.eq(sum_diff)).Else(
 -                abs_sum_diff.eq(-1 * sum_diff)
 -            ),
 -            If(
 -                current_peak_height >= 0,
 +        self.sync += [
 +            If(current_peak_height >= 0, 
                 abs_current_peak_height.eq(current_peak_height),
             ).Else(abs_current_peak_height.eq(-1 * current_peak_height)),
 -            over_threshold.eq(abs_sum_diff >= abs_current_peak_height),
 -            waited_long_enough.eq(waited_for > current_wait_for),
             all_instructions_triggered.eq(
                 self.current_instruction_idx >= self.N_instructions.storage
             ),
 +        ]
 +        self.comb += [
 +            sign_equal.eq((self.sum_diff > 0) == (current_peak_height > 0)),
 +            If(self.sum_diff >= 0, abs_sum_diff.eq(self.sum_diff)).Else(
 +                abs_sum_diff.eq(-1 * self.sum_diff)
 +            ),
 +            over_threshold.eq(abs_sum_diff >= abs_current_peak_height),
 +            waited_long_enough.eq(waited_for > current_wait_for),
             self.turn_on_lock.eq(
                 all_instructions_triggered
                 & (final_waited_for >= self.final_wait_time.storage)
             ),
         ]
 +        watching_reg = Signal()
         self.sync += [
 +            watching.eq(watching_reg),
             If(
                 self.at_start,
 -                waited_for.eq(0),
 +                # Compensate pipeline delay
 +                waited_for.eq(1),
                 # fpga robust autolock algorithm registeres trigger events delayed.
                 # Therefore, we give it a head start for `final_waited_for`
                 final_waited_for.eq(ROBUST_AUTOLOCK_FPGA_DELAY),
                 self.current_instruction_idx.eq(0),
 -                If(self.request_lock, watching.eq(1)).Else(watching.eq(0)),
 +                If(self.request_lock, watching_reg.eq(1)).Else(watching.eq(0), watching_reg.eq(0)),
             ).Else(
 +                # Compensate pipeline delay
                 # not at start
                 If(
                     ~self.request_lock,
@@ -213,7 +221,8 @@ class RobustAutolock(Module, AutoCSR):
                         self.current_instruction_idx.eq(
                             self.current_instruction_idx + 1
                         ),
 -                        waited_for.eq(0),
 +                        # Compensate pipeline delay
 +                        waited_for.eq(1),
                     ).Else(waited_for.eq(waited_for + 1)),
                 ),
                 If(
--- a/fast-servo/linien-gateware-chain-pipeline.patch
+++ b/fast-servo/linien-gateware-chain-pipeline.patch
@ -1,35 +0,0 @@
 diff --git a/gateware/logic/chains.py b/gateware/logic/chains.py
 index a890849..3461a78 100644
 --- a/gateware/logic/chains.py
 +++ b/gateware/logic/chains.py
@@ -93,7 +93,6 @@ class FastChain(Module, AutoCSR):
             self.comb += [
                 x_limit.x.eq(([self.demod.i, self.demod.q][sub_channel_idx] << s) + dx),
 -                iir_c.x.eq(x_limit.y),
                 iir_c.hold.eq(0),
                 iir_c.clear.eq(0),
                 iir_d.x.eq(iir_c.y),
@@ -101,14 +100,20 @@ class FastChain(Module, AutoCSR):
                 iir_d.clear.eq(0),
             ]
 +            self.sync += [
 +                iir_c.x.eq(x_limit.y)
 +            ]
 +
             ys = Array([iir_c.x, iir_c.y, iir_d.y])
             output_signal_this_channel = (self.out_i, self.out_q)[sub_channel_idx]
 -            self.comb += [
 +            self.sync += [
                 y_limit.x.eq(
                     Mux(self.invert.storage, -1, 1)
                     * (ys[self.y_tap.storage] + (ya << s) + (offset_signal << s))
 -                ),
 +                )
 +            ]
 +            self.comb += [
                 output_signal_this_channel.eq(y_limit.y),
             ]
--- a/fast-servo/linien-gateware/cores/adc.py
+++ b/fast-servo/linien-gateware/cores/adc.py
@ -20,21 +20,80 @@
 from migen import *
 from migen.genlib.cdc import MultiReg
 from misoc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage
-from misoc.interconnect.stream import AsyncFIFO
+
 class _CRG(Module):
    def __init__(self, platform, dco_clk, dco_freq=200e6):
        self.clock_domains.cd_dco = ClockDomain()
        self.clock_domains.cd_dco2x = ClockDomain()
        self.clock_domains.cd_dco2d = ClockDomain()
        dco_clk_p, dco_clk_n = dco_clk
        dco_clk_buf = Signal()
        self.specials += Instance(
            "IBUFGDS", i_I=dco_clk_p, i_IB=dco_clk_n, o_O=dco_clk_buf
        )
        # # #
        clk_feedback = Signal()
        clk_feedback_buf = Signal()
        clk_dco = Signal()
        clk_dco2x = Signal()
        clk_dco2d = Signal()
        self.locked = Signal()
        platform.add_period_constraint(dco_clk_p, 1e9 / dco_freq)
        self.specials += [
            Instance(
                "PLLE2_BASE",
                p_BANDWIDTH="OPTIMIZED",
                p_DIVCLK_DIVIDE=1,
                p_CLKFBOUT_PHASE=0.0,
                p_CLKFBOUT_MULT=4,  # VCO @ 800 MHz
                p_CLKIN1_PERIOD=(1e9 / dco_freq),
                p_REF_JITTER1=0.01,
                p_STARTUP_WAIT="FALSE",
                i_CLKIN1=dco_clk_buf,
                i_PWRDWN=0,
                i_RST=ResetSignal("sys"),
                i_CLKFBIN=clk_feedback_buf,
                o_CLKFBOUT=clk_feedback,
                p_CLKOUT0_DIVIDE=4,
                p_CLKOUT0_PHASE=0.0,
                p_CLKOUT0_DUTY_CYCLE=0.5,
                o_CLKOUT0=clk_dco,  # 200 MHz <- dco_clk
                p_CLKOUT1_DIVIDE=2,
                p_CLKOUT1_PHASE=0.0,
                p_CLKOUT1_DUTY_CYCLE=0.5,
                o_CLKOUT1=clk_dco2x,  # 400 MHZ <- 2 * dco_clk = 2*200 MHz
                p_CLKOUT2_DIVIDE=8,
                p_CLKOUT2_PHASE=0.0,
                p_CLKOUT2_DUTY_CYCLE=0.5,
                o_CLKOUT2=clk_dco2d,  # 100 MHz <- dco_clk / 2 = 200 MHz / 2
                o_LOCKED=self.locked,
            )
        ]
        self.specials += Instance("BUFG", i_I=clk_feedback, o_O=clk_feedback_buf)
        self.specials += Instance("BUFG", i_I=clk_dco, o_O=self.cd_dco.clk)
        self.specials += Instance("BUFG", i_I=clk_dco2d, o_O=self.cd_dco2d.clk)
        self.specials += Instance("BUFG", i_I=clk_dco2x, o_O=self.cd_dco2x.clk)
 class ADC(Module, AutoCSR):
-    def __init__(self, platform):
+    def __init__(self, platform, dco_freq=200e6):
        adc_pads = platform.request("adc")
        afe_pads = platform.request("adc_afe")
-        self.frame_csr = CSRStatus(5)
+        self.frame_csr = CSRStatus(4)
        self.data_ch0 = CSRStatus(16)
        self.data_ch1 = CSRStatus(16)
        self.tap_delay = CSRStorage(5)
        self.bitslip_csr = CSRStorage(1)
-        self.afe_ctrl = CSRStorage(7)
+        self.afe_ctrl = CSRStorage(4)
        tap_delay_val = Signal(5)
        bitslip = Signal()
@ -48,25 +107,29 @@ class ADC(Module, AutoCSR):
        self.data_out = [Signal(16, reset_less=True), Signal(16, reset_less=True)]
        self.s_frame = Signal(4)
        ###
        # DCO clock coming from LTC2195
        # dco_clk = Record([("p", 1), ("n", 1)])
        dco_clk =(adc_pads.dco_p, adc_pads.dco_n)
        self.comb += [
            # dco_clk.p.eq(adc_pads.dco_p),
            # dco_clk.n.eq(adc_pads.dco_n),
            tap_delay_val.eq(self.tap_delay.storage),
            Cat(ch1_gain_x10, ch2_gain_x10, ch1_shdn, ch2_shdn).eq(
-                self.afe_ctrl.storage[0:4]
+                self.afe_ctrl.storage
            ),
        ]
-        # self.comb += self.afe_ctrl.storage[4].eq(self.crg.mmcm_rst)
+        self.submodules._crg = _CRG(platform, dco_clk, dco_freq)
        # self.comb += self.afe_ctrl.storage[5].eq(self.crg.ddr_clk_phase_shift_en)
        # self.comb += self.afe_ctrl.storage[6].eq(self.crg.ddr_clk_phase_incdec)
-        self.specials += MultiReg(self.bitslip_csr.re, bitslip_re_dco_2d, "sys")
+        self.specials += MultiReg(self.bitslip_csr.re, bitslip_re_dco_2d, "dco2d")
-        self.sync.sys += [
+        self.sync.dco2d += [
            bitslip.eq(Mux(bitslip_re_dco_2d, self.bitslip_csr.storage, 0))
        ]
        self.comb += [
-            self.frame_csr.status[0:4].eq(self.s_frame[0:4]),
+            self.frame_csr.status.eq(self.s_frame),
            # self.frame_csr.status[4].eq(self.crg.locked),
            self.data_ch0.status.eq(self.data_out[0]),
            self.data_ch1.status.eq(self.data_out[1]),
        ]
@ -85,8 +148,8 @@ class ADC(Module, AutoCSR):
            "LTC2195",
            i_rst_in=ResetSignal("sys"),
            i_clk200=ClockSignal("idelay"),
-            i_DCO=ClockSignal("sys_double"),
+            i_DCO=ClockSignal("dco"),
-            i_DCO_2D=ClockSignal("sys"),
+            i_DCO_2D=ClockSignal("dco2d"),
            i_FR_in_p=adc_pads.frame_p,
            i_FR_in_n=adc_pads.frame_n,
            i_D0_in_p=adc_pads.data0_p,
--- a/fast-servo/linien-gateware/cores/dac.py
+++ b/fast-servo/linien-gateware/cores/dac.py
@ -20,17 +20,13 @@
 from migen import *
 from misoc.interconnect.csr import AutoCSR, CSRStorage
 from migen.genlib.io import DDROutput
 from misoc.interconnect.stream import AsyncFIFO
 class DAC(Module, AutoCSR):
-    def __init__(self, platform, phase_shift_ctrl):
+    def __init__(self, platform):
        dac_pads = platform.request("dac")
        dac_afe_pads = platform.request("dac_afe")
-
+        self.dac_ctrl = CSRStorage(3)
        phase_shift_en, phase_shift_dir = phase_shift_ctrl
        self.dac_ctrl = CSRStorage(5)
        self.output_value_ch0 = CSRStorage(14)
        self.output_value_ch1 = CSRStorage(14)
@ -42,42 +38,37 @@ class DAC(Module, AutoCSR):
        output_data_ch1 = Signal(14)
        self.data_in = [Signal(14, reset_less=True), Signal(14, reset_less=True)]
-        self.data_in_csr = [Signal(14, reset_less=True), Signal(14, reset_less=True)]
+        platform.add_period_constraint(dac_pads.dclkio, 10.0)
        self.comb += [
-            self.data_in_csr[0].eq(self.output_value_ch0.storage), 
+            Cat(manual_override, ch0_pd, ch1_pd).eq(self.dac_ctrl.storage),
            self.data_in_csr[1].eq(self.output_value_ch1.storage),
        ]
        self.comb += [
            Cat(manual_override, ch0_pd, ch1_pd, phase_shift_en, phase_shift_dir).eq(self.dac_ctrl.storage),
            dac_pads.rst.eq(ResetSignal("sys")),
            dac_afe_pads.ch1_pd_n.eq(~ch0_pd),
            dac_afe_pads.ch2_pd_n.eq(~ch1_pd),
            output_data_ch0.eq(
-                Mux(manual_override, self.data_in_csr[0], self.data_in[0])
+                Mux(manual_override, self.output_value_ch0.storage, self.data_in[0])
            ),
            output_data_ch1.eq(
-                Mux(manual_override, self.data_in_csr[1], self.data_in[1])
+                Mux(manual_override, self.output_value_ch1.storage, self.data_in[1])
            ),
        ]
-        self.specials += [
+        # data
-            Instance("ODDR", 
+        for lane in range(14):
-                i_C=ClockSignal("sys"), 
+            self.specials += DDROutput(
-                i_CE=~ResetSignal("sys"), 
+                i1 = output_data_ch0[lane], 
-                i_D1=output_data_ch0[lane], # DDR CLK Rising Edge
+                i2 = output_data_ch1[lane], 
-                i_D2=output_data_ch1[lane], # DDR CLK Falling Edge
+                o = dac_pads.data[lane], 
-                o_Q=dac_pads.data[lane],
+                clk = ClockSignal("dco2d")
-                p_DDR_CLK_EDGE="SAME_EDGE") 
+            )
-            for lane in range(14)]
+        
-        self.specials += Instance("ODDR", 
+        # clock forwarding
-                i_C=ClockSignal("sys_45_degree"), 
+        self.specials += DDROutput(
-                i_CE=~ResetSignal("sys"), 
+            i1 = 0b0,
-                i_D1=0, 
+            i2 = 0b1,
-                i_D2=1, 
+            o = dac_pads.dclkio,
-                o_Q=dac_pads.dclkio,
+            clk = ClockSignal("dco2d"),
-                p_DDR_CLK_EDGE="SAME_EDGE")
+        )
 class AUX_DAC_CTRL(Module, AutoCSR):
--- a/fast-servo/linien-gateware/fast_servo_platform.py
+++ b/fast-servo/linien-gateware/fast_servo_platform.py
@ -80,13 +80,11 @@ _io = [
        Subsignal("data0_n", Pins("E7 B6 E3 C1"), IOStandard("LVDS_25")),
        Subsignal("data1_p", Pins("A2 D5 F2 D7"), IOStandard("LVDS_25")),
        Subsignal("data1_n", Pins("A1 C4 F1 D6"), IOStandard("LVDS_25")),
        Subsignal("dco_p", Pins("B4"), IOStandard("LVDS_25")),
        Subsignal("dco_n", Pins("B3"), IOStandard("LVDS_25")),
        Subsignal("frame_p", Pins("B2"), IOStandard("LVDS_25")),
        Subsignal("frame_n", Pins("B1"), IOStandard("LVDS_25"))
    ),
    ("adc_dco_clk", 0 ,
        Subsignal("p", Pins("B4"), IOStandard("LVDS_25")),
        Subsignal("n", Pins("B3"), IOStandard("LVDS_25")),
    ),
    # ADC AFE
    ("adc_afe", 0,
@ -196,7 +194,7 @@ _io = [
    # Si540 nRST
    ("nrst", 0, Pins("M7"), IOStandard("LVCMOS18")),
-    ("si5340_nlol", 0, Pins("P2"),IOStandard("LVCMOS18")),
+
 ]
@ -273,7 +271,7 @@ ps7_config_board_preset = {
    # ETHERNET
    "PCW_ACT_ENET0_PERIPHERAL_FREQMHZ"  : "125",
-    "PCW_ENET0_PERIPHERAL_CLKSRC"       : "IO PLL",
+    "PCW_ENET0_PERIPHERAL_CLKSRC"       : "ARM PLL",
    "PCW_ENET0_PERIPHERAL_ENABLE"       : "1",
    "PCW_ENET0_ENET0_IO"                : "MIO 16 .. 27",
    "PCW_ENET0_GRP_MDIO_ENABLE"         : "1",
@ -317,23 +315,21 @@ ps7_config_board_preset = {
 }
 class Platform(XilinxPlatform):
-    default_clk_name = "adc_dco_clk_p"
+    default_clk_name = "clk100"
-    default_clk_period = 4.0
+    default_clk_period = 10.0
    def __init__(self):
        XilinxPlatform.__init__(self, "xc7z015-clg485-1", _io, _connector_gpio + _connector_eem, toolchain="vivado")
        ps7_config = ps7_config_board_preset
        self.ps7_config = ps7_config
        self.toolchain.with_phys_opt = True
        verilog_sources = os.listdir(verilog_dir)
        self.add_sources(verilog_dir, *verilog_sources)
    def do_finalize(self, fragment):
        try:
            XilinxPlatform.do_finalize(self, fragment)
-            self.add_period_constraint(self.lookup_request(self.default_clk_name), self.default_clk_period)
+            self.add_period_constraint(self.lookup_request(self.default_clk_name, loose=True), self.default_clk_period)
        except ValueError:
            pass
        except ConstraintError:
--- a/fast-servo/linien-gateware/fast_servo_soc.py
+++ b/fast-servo/linien-gateware/fast_servo_soc.py
@ -31,91 +31,63 @@ from fast_servo.gateware.cores.spi_phy import SpiInterface, SpiPhy
 class CRG(Module):
-    def __init__(self, platform, dco_freq=250e6):
+    def __init__(self, platform):
        self.ps_rst         = Signal()
        self.locked         = Signal()
        dco_clk = platform.request("adc_dco_clk")
        dco_clk_buf = Signal()
        self.specials += Instance(
            "IBUFGDS", i_I=dco_clk.p, i_IB=dco_clk.n, o_O=dco_clk_buf
        )
        self.clock_domains.cd_sys         = ClockDomain()
        self.clock_domains.cd_sys_45_degree = ClockDomain()
        self.clock_domains.cd_sys_double  = ClockDomain()
        self.clock_domains.cd_idelay      = ClockDomain()
        # # #
        # Clk.
        clk100 = platform.request("clk100")
        platform.add_period_constraint(clk100, 10.0)
        self.clkin = clk100
        clk100_buf = Signal()
        self.specials += Instance("IBUFG", i_I=clk100, o_O=clk100_buf)
        clk_feedback = Signal()
        clk_feedback_buf = Signal()
        clk_sys = Signal()
        clk_sys_45_degree = Signal()
        clk_sys_double = Signal()
        clk_idelay = Signal()
        self.ddr_clk_phase_shift_en = Signal()
        self.ddr_clk_phase_incdec = Signal()
        self.mmcm_ps_psdone = Signal()
        si5340_nlol = platform.request("si5340_nlol")
        si5340_nlol_buf = Signal()
        self.specials += Instance("IBUF", i_I=si5340_nlol, o_O=si5340_nlol_buf)
        platform.add_period_constraint(dco_clk.p, 1e9 / dco_freq)
        self.specials += [
            Instance(
-                "MMCME2_ADV",
+                "PLLE2_BASE",
                p_BANDWIDTH="OPTIMIZED",
                p_DIVCLK_DIVIDE=1,
                p_CLKFBOUT_PHASE=0.0,
-                p_CLKFBOUT_MULT_F=4,  # VCO @ 1000 MHz
+                p_CLKFBOUT_MULT=10,
-                p_CLKIN1_PERIOD=(1e9 / dco_freq),
+                p_CLKIN1_PERIOD=10.0,
-                p_REF_JITTER1=0.06, # From LTC2195 Datasheet
+                p_REF_JITTER1=0.01,
                p_STARTUP_WAIT="FALSE",
-                i_CLKIN1=dco_clk_buf,
+                i_CLKIN1=clk100_buf,
                i_PWRDWN=0,
-                i_RST=self.ps_rst | ~si5340_nlol_buf,
+                i_RST=self.ps_rst,
                i_CLKFBIN=clk_feedback_buf,
                o_CLKFBOUT=clk_feedback,
-
+                p_CLKOUT0_DIVIDE=10,
-                p_CLKOUT0_USE_FINE_PS="True",
+                p_CLKOUT0_PHASE=0.0,
                p_CLKOUT0_DIVIDE_F=8,
                p_CLKOUT0_PHASE=45.0,
                p_CLKOUT0_DUTY_CYCLE=0.5,
-                o_CLKOUT0=clk_sys_45_degree,  # 1000MHz / 8 -> 125MHz
+                o_CLKOUT0=clk_sys,           # 100 MHz <- sys_clk
-                o_LOCKED=self.locked,
+                p_CLKOUT1_DIVIDE=5,
                p_CLKOUT1_DIVIDE=8,
                p_CLKOUT1_PHASE=0.0,
                p_CLKOUT1_DUTY_CYCLE=0.5,
-                o_CLKOUT1=clk_sys,  # 1000MHz / 8 -> 120MHz
+                o_CLKOUT1=clk_idelay,       # 200 MHZ <- 2 * sys_clk = 2*100 MHz
-                
+                o_LOCKED=self.locked,
                p_CLKOUT2_DIVIDE=4,
                p_CLKOUT2_PHASE=0.0,
                p_CLKOUT2_DUTY_CYCLE=0.5,
                o_CLKOUT2=clk_sys_double,  # 1000MHz / 4 -> 250MHz
                p_CLKOUT3_DIVIDE=5,
                p_CLKOUT3_PHASE=0.0,
                p_CLKOUT3_DUTY_CYCLE=0.5,
                o_CLKOUT3=clk_idelay,  # 1000MHz / 5 -> 200MHz 
                i_PSCLK=ClockSignal(),
                i_PSEN=self.ddr_clk_phase_shift_en,
                i_PSINCDEC=self.ddr_clk_phase_incdec,
                o_PSDONE=self.mmcm_ps_psdone,
            )
        ]
        self.specials += Instance("BUFG", i_I=clk_feedback, o_O=clk_feedback_buf)
        self.specials += Instance("BUFG", i_I=clk_sys, o_O=self.cd_sys.clk)
        self.specials += Instance("BUFG", i_I=clk_sys_45_degree, o_O=self.cd_sys_45_degree.clk)
        self.specials += Instance("BUFG", i_I=clk_sys_double, o_O=self.cd_sys_double.clk)
        self.specials += Instance("BUFG", i_I=clk_idelay, o_O=self.cd_idelay.clk)
-        
+        self.specials += Instance("BUFG", i_I=clk_idelay, o_O=self.cd_sys_double.clk)
        # Ignore sys_clk to pll clkin path created by SoC's rst.
-        platform.add_false_path_constraints(self.cd_sys.clk, dco_clk)
+        platform.add_false_path_constraints(self.cd_sys.clk, self.clkin)
        self.specials += Instance("FD", p_INIT=1, i_D=~self.locked, i_C=self.cd_sys.clk, o_Q=self.cd_sys.rst)
@ -145,10 +117,6 @@ class BaseSoC(PS7, AutoCSR):
        self.submodules.crg = CRG(platform)
        # self.comb += self.afe_ctrl.storage[4].eq(self.crg.mmcm_rst)
        # self.comb += self.afe_ctrl.storage[5].eq(self.crg.ddr_clk_phase_shift_en)
        # self.comb += self.afe_ctrl.storage[6].eq(self.crg.ddr_clk_phase_incdec)
        # # # AXI to system bus bridge
        self.submodules.axi2sys = Axi2Sys()
        self.submodules.sys2csr = Sys2CSR()
@ -179,10 +147,9 @@ class BaseSoC(PS7, AutoCSR):
        # self.add_main_adc(platform)
        self.submodules.adc = ADC(platform)
        self.csr_devices.append("adc")
        # platform.add_false_path_constraints(self.crg.cd_sys.clk, self.adc.crg.cd_dco2d.clk)
        # self.add_main_dac(platform)
-        self.submodules.dac = DAC(platform, [self.crg.ddr_clk_phase_shift_en, self.crg.ddr_clk_phase_incdec,])
+        self.submodules.dac = DAC(platform)
        self.csr_devices.append("dac")
        # DEBUG
--- a/fast-servo/linien-gui-add-afe_gain-combo-boxes.patch
+++ b/fast-servo/linien-gui-add-afe_gain-combo-boxes.patch
@ -1,132 +0,0 @@
 diff --git a/linien-gui/linien_gui/ui/general_panel.py b/linien-gui/linien_gui/ui/general_panel.py
 index cad2d91..499146d 100644
 --- a/linien-gui/linien_gui/ui/general_panel.py
 +++ b/linien-gui/linien_gui/ui/general_panel.py
@@ -48,6 +48,8 @@ class GeneralPanel(QtWidgets.QWidget):
     polarityContainerFastOut2: QtWidgets.QWidget
     polarityComboBoxFastOut2: QtWidgets.QComboBox
     modulationChannelComboBox: QtWidgets.QComboBox
 +    afeGainComboBoxFastIn1: QtWidgets.QComboBox
 +    afeGainComboBoxFastIn2: QtWidgets.QComboBox
     def __init__(self, *args, **kwargs) -> None:
         super(GeneralPanel, self).__init__(*args, **kwargs)
@@ -80,6 +82,14 @@ class GeneralPanel(QtWidgets.QWidget):
             self.on_polarity_analog_out0_changed
         )
 +        self.afeGainComboBoxFastIn1.currentIndexChanged.connect(
 +            self.on_afe_gain_in1_changed
 +        )
 +
 +        self.afeGainComboBoxFastIn2.currentIndexChanged.connect(
 +            self.on_afe_gain_in2_changed
 +        )
 +
         for idx in range(1, 4):
             element: CustomDoubleSpinBoxNoSign = getattr(
                 self, f"analogOutComboBox{idx}"
@@ -126,6 +136,9 @@ class GeneralPanel(QtWidgets.QWidget):
         param2ui(self.parameters.polarity_fast_out2, self.polarityComboBoxFastOut2)
         param2ui(self.parameters.polarity_analog_out0, self.polarityComboBoxAnalogOut0)
 +        param2ui(self.parameters.adc_afe_10x_gain_1, self.afeGainComboBoxFastIn1)
 +        param2ui(self.parameters.adc_afe_10x_gain_2, self.afeGainComboBoxFastIn2)
 +
         self.parameters.control_channel.add_callback(self.show_polarity_settings)
         self.parameters.sweep_channel.add_callback(self.show_polarity_settings)
         self.parameters.mod_channel.add_callback(self.show_polarity_settings)
@@ -211,6 +224,14 @@ class GeneralPanel(QtWidgets.QWidget):
         self.parameters.polarity_analog_out0.value = bool(polarity)
         self.control.write_registers()
 +    def on_afe_gain_in1_changed(self, polarity):
 +        self.parameters.adc_afe_10x_gain_1.value = bool(polarity)
 +        self.control.write_registers()
 +
 +    def on_afe_gain_in2_changed(self, polarity):
 +        self.parameters.adc_afe_10x_gain_2.value = bool(polarity)
 +        self.control.write_registers()    
 +
     def show_polarity_settings(self, *args):
         used_channels = {
             self.parameters.control_channel.value,
 diff --git a/linien-gui/linien_gui/ui/general_panel.ui b/linien-gui/linien_gui/ui/general_panel.ui
 index 6c2bd45..79f4580 100644
 --- a/linien-gui/linien_gui/ui/general_panel.ui
 +++ b/linien-gui/linien_gui/ui/general_panel.ui
@@ -508,6 +508,74 @@
            </property>
           </widget>
          </item>
 +         <item>
 +          <layout class="QHBoxLayout" name="horizontalLayout_13">
 +           <item>
 +            <widget class="QLabel" name="label_22">
 +             <property name="text">
 +              <string>&lt;html&gt;&lt;head/&gt;&lt;body&gt;&lt;p&gt;&lt;span style=&quot; font-weight:600;&quot;&gt;FAST IN 1 GAIN&lt;/span&gt;&lt;/p&gt;&lt;/body&gt;&lt;/html&gt;</string>
 +             </property>
 +             <property name="textFormat">
 +              <enum>Qt::AutoText</enum>
 +             </property>
 +            </widget>
 +           </item>
 +           <item>
 +            <widget class="QComboBox" name="afeGainComboBoxFastIn1">
 +             <property name="sizePolicy">
 +              <sizepolicy hsizetype="Fixed" vsizetype="Fixed">
 +               <horstretch>0</horstretch>
 +               <verstretch>0</verstretch>
 +              </sizepolicy>
 +             </property>
 +             <item>
 +              <property name="text">
 +               <string>1x</string>
 +              </property>
 +             </item>
 +             <item>
 +              <property name="text">
 +               <string>10x</string>
 +              </property>
 +             </item>
 +            </widget>
 +           </item>
 +          </layout>
 +         </item>
 +         <item>
 +          <layout class="QHBoxLayout" name="horizontalLayout_14">
 +           <item>
 +            <widget class="QLabel" name="label_24">
 +             <property name="text">
 +              <string>&lt;html&gt;&lt;head/&gt;&lt;body&gt;&lt;p&gt;&lt;span style=&quot; font-weight:600;&quot;&gt;FAST IN 2 GAIN&lt;/span&gt;&lt;/p&gt;&lt;/body&gt;&lt;/html&gt;</string>
 +             </property>
 +             <property name="textFormat">
 +              <enum>Qt::AutoText</enum>
 +             </property>
 +            </widget>
 +           </item>
 +           <item>
 +            <widget class="QComboBox" name="afeGainComboBoxFastIn2">
 +             <property name="sizePolicy">
 +              <sizepolicy hsizetype="Fixed" vsizetype="Fixed">
 +               <horstretch>0</horstretch>
 +               <verstretch>0</verstretch>
 +              </sizepolicy>
 +             </property>
 +             <item>
 +              <property name="text">
 +               <string>1x</string>
 +              </property>
 +             </item>
 +             <item>
 +              <property name="text">
 +               <string>10x</string>
 +              </property>
 +             </item>
 +            </widget>
 +           </item>
 +          </layout>
 +         </item>
          <item>
           <widget class="QGroupBox" name="dualChannelMixingGroupBox">
            <property name="title">
--- a/fast-servo/linien-gui-do-not-check-for-update.patch
+++ b/fast-servo/linien-gui-do-not-check-for-update.patch
@ -1,13 +0,0 @@
 diff --git a/linien-gui/linien_gui/app.py b/linien-gui/linien_gui/app.py
 index 3185b45..84ff97e 100644
 --- a/linien-gui/linien_gui/app.py
 +++ b/linien-gui/linien_gui/app.py
@@ -70,7 +70,7 @@ class LinienApp(QtWidgets.QApplication):
         self.periodically_check_for_changed_parameters()
 -        self.check_for_new_version()
 +        # self.check_for_new_version()
     def periodically_check_for_changed_parameters(self):
         if hasattr(self, "client") and self.client and self.client.connected:
--- a/fast-servo/linien-gui-do-not-use-opengl.patch
+++ b/fast-servo/linien-gui-do-not-use-opengl.patch
@ -1,13 +0,0 @@
 diff --git a/linien-gui/linien_gui/ui/plot_widget.py b/linien-gui/linien_gui/ui/plot_widget.py
 index f3b81ce..7d865a3 100644
 --- a/linien-gui/linien_gui/ui/plot_widget.py
 +++ b/linien-gui/linien_gui/ui/plot_widget.py
@@ -40,7 +40,7 @@ from pyqtgraph.Qt import QtCore
 # NOTE: this is required for using a pen_width > 1. There is a bug though that causes
 # the plot to be way too small. Therefore, we call PlotWidget.resize() after a while
 pg.setConfigOptions(
 -    useOpenGL=True,
 +    useOpenGL=False,
     # by default, pyqtgraph tries to clean some things up using atexit. This causes
     # problems with rpyc objects as their connection is already closed. Therefore, we
     # disable this cleanup.
--- a/fast-servo/linien-gui-fast-servo-hardware-specific.patch
+++ b/fast-servo/linien-gui-fast-servo-hardware-specific.patch
@ -1,141 +0,0 @@
 diff --git a/linien-gui/linien_gui/ui/general_panel.ui b/linien_gui/ui/general_panel.ui
 index 7cf74a7..6c2bd45 100644
 --- a/linien-gui/linien_gui/ui/general_panel.ui
 +++ b/linien_gui/ui/general_panel.ui
@@ -128,11 +128,6 @@
             <string>FAST OUT 2</string>
            </property>
           </item>
 -          <item>
 -           <property name="text">
 -            <string>ANALOG OUT 0</string>
 -           </property>
 -          </item>
          </widget>
         </item>
        </layout>
@@ -213,11 +208,6 @@
             <string>FAST OUT 2</string>
            </property>
           </item>
 -          <item>
 -           <property name="text">
 -            <string>ANALOG OUT 0</string>
 -           </property>
 -          </item>
           <item>
            <property name="text">
             <string>disabled</string>
@@ -389,6 +379,9 @@
               <property name="text">
                <string>ANALOG OUT 0</string>
               </property>
 +              <property name="visible">
 +                <bool>false</bool>
 +              </property>
              </widget>
             </item>
             <item>
@@ -399,6 +392,9 @@
                 <verstretch>0</verstretch>
                </sizepolicy>
               </property>
 +              <property name="visible">
 +                <bool>false</bool>
 +              </property>
               <item>
                <property name="text">
                 <string>positive</string>
@@ -619,6 +615,9 @@
      <property name="title">
       <string>Slow Analog Outputs (0-1.8V)</string>
      </property>
 +     <property name="visible">
 +        <bool>false</bool>
 +     </property>
      <layout class="QVBoxLayout" name="verticalLayout_2">
       <item>
        <widget class="QLabel" name="label_20">
 diff --git a/linien-gui/linien_gui/ui/main_window.ui b/linien_gui/ui/main_window.ui
 index 3d8b8bf..72f6159 100644
 --- a/linien-gui/linien_gui/ui/main_window.ui
 +++ b/linien_gui/ui/main_window.ui
@@ -145,10 +145,10 @@ p, li { white-space: pre-wrap; }
                <number>3</number>
               </property>
               <property name="minimum">
 -               <double>-1.000000000000000</double>
 +               <double>-0.250000000000000</double>
               </property>
               <property name="maximum">
 -               <double>1.000000000000000</double>
 +               <double>0.250000000000000</double>
               </property>
               <property name="singleStep">
                <double>0.100000000000000</double>
@@ -199,13 +199,13 @@ p, li { white-space: pre-wrap; }lin
                <double>0.000000000000000</double>
               </property>
               <property name="maximum">
 -               <double>1.000000000000000</double>
 +               <double>0.250000000000000</double>
               </property>
               <property name="singleStep">
                <double>0.100000000000000</double>
               </property>
               <property name="value">
 -               <double>1.000000000000000</double>
 +               <double>0.500000000000000</double>
               </property>
              </widget>
             </item>
@@ -242,7 +242,6 @@ p, li { white-space: pre-wrap; }
              <widget class="QLabel" name="label_4">
               <property name="font">
                <font>
 -                <weight>75</weight>
                 <bold>true</bold>
                </font>
               </property>
@@ -278,7 +277,6 @@ p, li { white-space: pre-wrap; }
              <widget class="QLabel" name="label_5">
               <property name="font">
                <font>
 -                <weight>75</weight>
                 <bold>true</bold>
                </font>
               </property>
@@ -366,7 +364,6 @@ p, li { white-space: pre-wrap; }
                <widget class="QLabel" name="label">
                 <property name="font">
                  <font>
 -                  <weight>75</weight>
                   <bold>true</bold>
                  </font>
                 </property>
 diff --git a/linien-gui/linien_gui/ui/modulation_sweep_panel.ui b/linien_gui/ui/modulation_sweep_panel.ui
 index 6d8af14..29c8a63 100644
 --- a/linien-gui/linien_gui/ui/modulation_sweep_panel.ui
 +++ b/linien_gui/ui/modulation_sweep_panel.ui
@@ -68,7 +68,7 @@
            <number>3</number>
           </property>
           <property name="maximum">
 -           <double>2.000000000000000</double>
 +           <double>0.500000000000000</double>
           </property>
           <property name="singleStep">
            <double>0.100000000000000</double>
 diff --git a/linien-gui/linien_gui/ui/sweep_control.py b/linien-gui/linien_gui/ui/sweep_control.py
 index 7d2bb2d..e98c169 100644
 --- a/linien-gui/linien_gui/ui/sweep_control.py
 +++ b/linien-gui/linien_gui/ui/sweep_control.py
@@ -109,6 +109,6 @@ class SweepSlider(superqt.QDoubleRangeSlider):
     def ready(self):
         # set control boundaries
 -        self.setMinimum(-1.0)
 -        self.setMaximum(1.0)
 +        self.setMinimum(-0.25)
 +        self.setMaximum(0.25)
         self.setSingleStep(0.001)
--- a/fast-servo/linien-gui-fast-servo-rm-ota-update.patch
+++ b/fast-servo/linien-gui-fast-servo-rm-ota-update.patch
@ -1,43 +0,0 @@
 diff --git a/linien_gui/ui/device_manager.py b/linien_gui/ui/device_manager.py
 index e584825..16994ad 100644
 --- a/linien_gui/ui/device_manager.py
 +++ b/linien_gui/ui/device_manager.py
@@ -109,19 +109,13 @@ class DeviceManager(QtWidgets.QMainWindow):
         ) -> None:
             loading_dialog.hide()
             if not aborted:
 -                display_question = (
 +                # Fast Servo does not support OTA Update
 +                display_error = (
                     f"Server version ({remote_version}) does not match the client "
 -                    f"({client_version}) version. Should the corresponding server "
 -                    f"version be installed?"
 +                    f"({client_version}) version."
 +                    f"Please install a matching server and client version"
                 )
 -                if question_dialog(
 -                    self, display_question, "Install corresponding version?"
 -                ):
 -                    show_installation_progress_widget(
 -                        parent=self,
 -                        device=device,
 -                        callback=lambda: self.connect_to_device(device),
 -                    )
 +                error_dialog(self, display_error)
         def handle_authentication_exception():
             loading_dialog.hide()
 diff --git a/linien_gui/ui/main_window.py b/linien_gui/ui/main_window.py
 index dad465e..8d6a0b4 100644
 --- a/linien_gui/ui/main_window.py
 +++ b/linien_gui/ui/main_window.py
@@ -202,7 +202,8 @@ class MainWindow(QtWidgets.QMainWindow):
         super().closeEvent(*args, **kwargs)
     def show_new_version_available(self):
 -        self.newVersionAvailableLabel.show()
 +        # Fast Servo does not support OTA Update
 +        pass
     def handle_key_press(self, key):
         logger.debug(f"key pressed {key}")
--- a/fast-servo/linien-gui-hide-password-box.patch
+++ b/fast-servo/linien-gui-hide-password-box.patch
@ -1,14 +0,0 @@
 diff --git a/linien-gui/linien_gui/ui/new_device_dialog.ui b/linien-gui/linien_gui/ui/new_device_dialog.ui
 index 7d5790c..38c3513 100644
 --- a/linien-gui/linien_gui/ui/new_device_dialog.ui
 +++ b/linien-gui/linien_gui/ui/new_device_dialog.ui
@@ -136,6 +136,9 @@
                 <property name="text">
                  <string>root</string>
                 </property>
 +                <property name="visible">
 +                    <bool>false</bool>
 +                </property>
                </widget>
               </item>
              </layout>
--- a/fast-servo/linien-module-iir-coeff-width-set-to-18bit.patch
+++ b/fast-servo/linien-module-iir-coeff-width-set-to-18bit.patch
@ -1,22 +0,0 @@
 diff --git a/gateware/linien_module.py b/gateware/linien_module.py
 index a64714c..1d905de 100644
 --- a/gateware/linien_module.py
 +++ b/gateware/linien_module.py
@@ -47,7 +47,7 @@ from .lowlevel.scopegen import ScopeGen
 class LinienLogic(Module, AutoCSR):
 -    def __init__(self, width=14, signal_width=25, chain_factor_width=8, coeff_width=25):
 +    def __init__(self, width=14, signal_width=25, chain_factor_width=8, coeff_width=18):
         self.init_csr(width, chain_factor_width)
         self.init_submodules(width, signal_width)
         self.connect_pid()
@@ -154,7 +154,7 @@ class LinienModule(Module, AutoCSR):
     def __init__(self, soc):
         width = 14
         signal_width = 25
 -        coeff_width = 25
 +        coeff_width = 18
         chain_factor_bits = 8
         self.init_submodules(
--- a/fast-servo/linien-pyrp3-monitor.patch
+++ b/fast-servo/linien-pyrp3-monitor.patch
@ -4,14 +4,14 @@
 diff --git a/monitor/Makefile b/monitor/Makefile
 new file mode 100644
-index 0000000..0c9bb53
+index 0000000..044d88e
 --- /dev/null
 +++ b/monitor/Makefile
@@ -0,0 +1,31 @@
 +# Makefile for libmonitor
 +
 +OBJS = monitor.o
-+SRCS = $(subst .o,.c, $(OBJS)))
+SRCS = $(subst .o,.c, $(OBJS))
 +OSOBJS = monitor.os
 +TARGETLIB=libmonitor.so
 +CFLAGS=-g -std=gnu99 -Wall -Werror
@ -59,16 +59,27 @@ index ce1b28e..233b82a 100644
 libmonitor = cdll.LoadLibrary(libmonitor_file)
 libmonitor.read_value.restype = c_uint32
 diff --git a/setup.py b/setup.py
-index 9302177..2258ddc 100644
+index 98bdaee..b0a8af4 100644
 --- a/setup.py
 +++ b/setup.py
-@@ -1,4 +1,28 @@
+@@ -1,5 +1,10 @@
 import re
 -from distutils.core import Extension, setup
 +import os
 +
 +from distutils.core import setup
 +from distutils.command.build import build
 +from distutils.command.install import install
 +
 from pathlib import Path
 # from https://stackoverflow.com/a/7071358/2750945
@@ -11,9 +16,50 @@ if mo:
     verstr = mo.group(1)
 else:
     raise RuntimeError("Unable to find version string in %s." % (VERSIONFILE,))
 +
 +# Patch from https://github.com/linien-org/pyrp3/blob/e6688acf8bd79d2dbe1d192d09c1a1baf1f6c67b/setup.py#L16-L55
 +build_dir = "monitor/"
 +
 +def compile_libmonitor():
@ -80,16 +91,51 @@ index 9302177..2258ddc 100644
 +    finally:
 +        os.chdir(cwd)
 +
 +
 +def install_libmonitor(prefix=""):
 +    cwd = os.getcwd()  # get current directory
 +    try:
 +        os.chdir(build_dir)
 +        os.system("make install INSTALL_DIR={prefix}".format(prefix=prefix))
 +    finally:
 +        os.chdir(cwd)
 +
 +
 +class lib_build(build):
 +    def run(self):
 +        compile_libmonitor()
 +        build.run(self)
 +
-+setup_args = dict(
+
-+    cmdclass={
+class lib_install(install):
-+        "build": lib_build
+    def run(self):
-+    }
+        compile_libmonitor()
-+)
+        install_libmonitor(self.prefix)
 +        # install.run(self)
 +
 +# Will use nix to install libmonitor
 +cmdclass = {
 +    "build": lib_build
 +}
 +
 this_directory = Path(__file__).parent
 long_description = (this_directory / "README.rst").read_text()
-setup_args = dict(ext_modules=[Extension("monitor", ["monitor/monitor.c"])])
+
- setup(**setup_args)
+ setup(
     name="pyrp3",
     version=verstr,
@@ -32,6 +78,7 @@ setup(
         "cached_property>=1.5.2",
         "numpy>=1.11.0",
     ],
 +    cmdclass=cmdclass,
     classifiers=[
         "Intended Audience :: Developers",
         "Intended Audience :: Education",
@@ -45,5 +92,4 @@ setup(
         "Topic :: Software Development :: Libraries :: Python Modules",
     ],
     keywords=["redpitaya", "FPGA", "zynq"],
 -    ext_modules=[Extension("monitor", ["monitor/monitor.c"])],
 )
--- a/fast-servo/linien-server-add-afe_ctrl-regs.patch
+++ b/fast-servo/linien-server-add-afe_ctrl-regs.patch
@ -1,34 +0,0 @@
 diff --git a/linien-server/linien_server/parameters.py b/linien-server/linien_server/parameters.py
 index 287f304..fe482d7 100644
 --- a/linien-server/linien_server/parameters.py
 +++ b/linien-server/linien_server/parameters.py
@@ -154,6 +154,16 @@ class Parameters:
         `error_signal_2_max`.
         """
 +        # ------------------- FAST SERVO PARAMETERS ---------------------------------------
 +        self.adc_afe_10x_gain_1 = Parameter(start=0, min_=0, max_=1, restorable=True)
 +        self.adc_afe_10x_gain_2 = Parameter(start=0, min_=0, max_=1, restorable=True)
 +        """
 +        Configures Fast INs AFE Gain:
 +            0 -->  1x Gain
 +            1 --> 10x Gain
 +        """
 +        
 +
         # ------------------- GENERAL PARAMETERS ---------------------------------------
         self.mod_channel = Parameter(start=0, min_=0, max_=1, restorable=True)
 diff --git a/linien-server/linien_server/registers.py b/linien-server/linien_server/registers.py
 index 365c254..2b8f697 100644
 --- a/linien-server/linien_server/registers.py
 +++ b/linien-server/linien_server/registers.py
@@ -173,6 +173,8 @@ class Registers:
             gpio_n_do0_en=csrmap.signals.index("zero"),
             gpio_n_do1_en=csrmap.signals.index("zero"),
             logic_slow_decimation=16,
 +            # Fast Servo Paramters
 +            adc_afe_ctrl=(self.parameters.adc_afe_10x_gain_2.value << 1 | self.parameters.adc_afe_10x_gain_1.value)
         )
         for instruction_idx, [wait_for, peak_height] in enumerate(
--- a/fast-servo/linien-server-cli.patch
+++ b/fast-servo/linien-server-cli.patch
@ -1,73 +0,0 @@
 diff --git a/linien-client/linien_client/deploy.py b/linien-client/linien_client/deploy.py
 index 7355cc3..876f1ec 100644
 --- a/linien-client/linien_client/deploy.py
 +++ b/linien-client/linien_client/deploy.py
@@ -83,14 +83,14 @@ def start_remote_server(
         if (local_version != remote_version) and not ("dev" in local_version):
             raise InvalidServerVersionException(local_version, remote_version)
 -        logger.debug("Sending credentials")
 -        conn.run(
 -            'python3 -c "from linien_common.communication import write_hash_to_file;'
 -            f"write_hash_to_file('{hash_username_and_password(device.username, device.password)}')\"",  # noqa E501
 -            out_stream=out_stream,
 -            err_stream=out_stream,
 -            warn=True,
 -        )
 +        # logger.debug("Sending credentials")
 +        # conn.run(
 +        #     'python3 -c "from linien_common.communication import write_hash_to_file;'
 +        #     f"write_hash_to_file('{hash_username_and_password(device.username, device.password)}')\"",  # noqa E501
 +        #     out_stream=out_stream,
 +        #     err_stream=out_stream,
 +        #     warn=True,
 +        # )
         logger.debug("Starting server")
         conn.run(
 diff --git a/linien-server/linien_server/cli.py b/linien-server/linien_server/cli.py
 index 7781c74..827d04f 100644
 --- a/linien-server/linien_server/cli.py
 +++ b/linien-server/linien_server/cli.py
@@ -44,20 +44,19 @@ class LinienServerCLI:
     def start(self) -> None:
         """Start the Linien server as a systemd service."""
 -        copy_systemd_service_file()
         logger.info("Starting Linien server")
 -        subprocess.run(["systemctl", "start", "linien-server.service"])
 +        subprocess.run(["sv", "up", "/etc/service/linien-server"])
         logger.info("Started Linien server")
     def stop(self) -> None:
         """Stop the Linien server running as a systemd service."""
         logger.info("Stopping Linien server")
 -        subprocess.run(["systemctl", "stop", "linien-server.service"])
 +        subprocess.run(["sv", "down", "/etc/service/linien-server"])
         logger.info("Stopped Linien server")
     def status(self) -> None:
         """Check the status of the Linien server."""
 -        subprocess.run(["journalctl", "-u", "linien-server.service"])
 +        subprocess.run(["sv", "status", "/etc/service/linien-server"])
     def run(self, fake: bool = False, host: Optional[str] = None) -> None:
         """
@@ -89,15 +88,14 @@ class LinienServerCLI:
     def enable(self) -> None:
         """Enable the Linien server to start on boot."""
 -        copy_systemd_service_file()
         logger.info("Enabling Linien server")
 -        subprocess.run(["systemctl", "enable", "linien-server.service"])
 +        subprocess.run(["rm", "/etc/service/linien-server/down"])
         logger.info("Enabled Linien server")
     def disable(self) -> None:
         """Disable the Linien server from starting on boot."""
         logger.info("Disabling Linien server")
 -        subprocess.run(["systemctl", "disable", "linien-server.service"])
 +        subprocess.run(["touch", "/etc/service/linien-server/down"])
         logger.info("Disabled Linien server")
--- a/fast-servo/linien-server-fast-servo-hardware-specific.patch
+++ b/fast-servo/linien-server-fast-servo-hardware-specific.patch
@ -1,72 +0,0 @@
 diff --git a/linien-server/linien_server/parameters.py b/linien-server/linien_server/parameters.py
 index 12f16ed..287f304 100644
 --- a/linien-server/linien_server/parameters.py
 +++ b/linien-server/linien_server/parameters.py
@@ -311,7 +311,7 @@ class Parameters:
         # ------------------- MODULATION PARAMETERS ------------------------------------
         self.modulation_amplitude = Parameter(
 -            min_=0, max_=(1 << 14) - 1, start=1 * Vpp, restorable=True, loggable=True
 +            min_=0, max_=(1 << 14) - 1, start=0.1 * Vpp, restorable=True, loggable=True
         )
         """
         The amplitude of the modulation in internal units. Use Vpp for conversion to
@@ -320,7 +320,7 @@ class Parameters:
         """
         self.modulation_frequency = Parameter(
 -            min_=0, max_=0xFFFFFFFF, start=15 * MHz, restorable=True, loggable=True
 +            min_=0, max_=0xFFFFFFFF, start=1 * MHz, restorable=True, loggable=True
         )
         """
         Frequency of the modulation in internal units. Use MHz for conversion to
 diff --git a/linien-server/linien_server/parameters.py b/linien-server/linien_server/parameters.py
 index fe482d7..04a3c24 100644
 --- a/linien-server/linien_server/parameters.py
 +++ b/linien-server/linien_server/parameters.py
@@ -292,14 +292,14 @@ class Parameters:
         # ------------------- SWEEP PARAMETERS -----------------------------------------
 -        self.sweep_amplitude = Parameter(min_=0.001, max_=1, start=1, loggable=True)
 +        self.sweep_amplitude = Parameter(min_=0.001, max_=0.25, start=0.25, loggable=True)
         """
         Amplitude of the sweep in units of 0.5 * Vpp of the output (2 V for fast outputs
         (range +/- 1 V) and 0.9 V for slow outputs (range 0 V to 1.8 V)). That means an
         amplitude of 1.0 corresponds to the full sweep range in both cases.
         """
 -        self.sweep_center = Parameter(min_=-1, max_=1, start=0, loggable=True)
 +        self.sweep_center = Parameter(min_=-0.25, max_=0.25, start=0, loggable=True)
         """
         The center position of the sweep. If a fast output is used for the sweep this is
         the sweep center position in volts. If the slow output is used the interval
 diff --git a/linien-server/linien_server/registers.py b/linien-server/linien_server/registers.py
 index 2b8f697..65e9732 100644
 --- a/linien-server/linien_server/registers.py
 +++ b/linien-server/linien_server/registers.py
@@ -94,12 +94,12 @@ class Registers:
             logic_sweep_pause=int(self.parameters.sweep_pause.value),
             logic_sweep_step=int(
                 DEFAULT_SWEEP_SPEED
 -                * self.parameters.sweep_amplitude.value
 +                * self.parameters.sweep_amplitude.value * 4
                 / (2**self.parameters.sweep_speed.value)
             ),
             # NOTE: Sweep center is set by `logic_out_offset`.
 -            logic_sweep_min=-1 * max_(self.parameters.sweep_amplitude.value * 8191),
 -            logic_sweep_max=max_(self.parameters.sweep_amplitude.value * 8191),
 +            logic_sweep_min=-1 * max_(self.parameters.sweep_amplitude.value * 32767),
 +            logic_sweep_max=max_(self.parameters.sweep_amplitude.value * 32767),
             logic_mod_freq=(
                 self.parameters.modulation_frequency.value
                 if not self.parameters.pid_only_mode.value
@@ -121,7 +121,7 @@ class Registers:
             logic_chain_b_offset=twos_complement(
                 int(self.parameters.offset_b.value), 14
             ),
 -            logic_out_offset=int(self.parameters.sweep_center.value * 8191),
 +            logic_out_offset=int(self.parameters.sweep_center.value * 32767),
             logic_combined_offset=twos_complement(
                 self.parameters.combined_offset.value, 14
             ),
--- a/fast-servo/linien-server-fast-servo.patch
+++ b/fast-servo/linien-server-fast-servo.patch
@ -1,26 +0,0 @@
 diff --git a/linien-server/linien_server/cli.py b/linien-server/linien_server/cli.py
 index 98539b2..7781c74 100644
 --- a/linien-server/linien_server/cli.py
 +++ b/linien-server/linien_server/cli.py
@@ -83,18 +83,9 @@ class LinienServerCLI:
         else:
             control = RedPitayaControlService(host=host)
 -        if fake or host:
 -            authenticator = no_authenticator
 -        else:
 -            authenticator = username_and_password_authenticator
 -
 -        try:
 -            if not (fake or host):  # only available on RP
 -                mdio_tool.disable_ethernet_blinking()
 -            run_threaded_server(control, authenticator=authenticator)
 -        finally:
 -            if not (fake or host):  # only available on RP
 -                mdio_tool.enable_ethernet_blinking()
 +        authenticator = no_authenticator
 +
 +        run_threaded_server(control, authenticator=authenticator)
     def enable(self) -> None:
         """Enable the Linien server to start on boot."""
--- a/fast-servo/linien-server-shutdown-control.patch
+++ b/fast-servo/linien-server-shutdown-control.patch
@ -1,22 +0,0 @@
 diff --git a/linien-server/linien_server/server.py b/linien-server/linien_server/server.py
 index 99a2cc3..9cd8ae7 100644
 --- a/linien-server/linien_server/server.py
 +++ b/linien-server/linien_server/server.py
@@ -25,6 +25,7 @@ from socket import socket
 from threading import Event, Thread
 from time import sleep
 from typing import Any, Callable
 +import subprocess
 import numpy as np
 import rpyc
@@ -313,7 +314,8 @@ class RedPitayaControlService(BaseService, LinienControlService):
         self.registers.acquisition.exposed_stop_acquisition()
         # FIXME: hacky way to trigger atexit handlers for saving parameters
         _thread.interrupt_main()
 -        raise SystemExit()
 +        subprocess.Popen (["linien-server", "stop"])
 +        # raise SystemExit()
     def exposed_pause_acquisition(self):
         """
--- a/fast-servo/linien_module_pipeline.patch
+++ b/fast-servo/linien_module_pipeline.patch
@ -1,66 +0,0 @@
 diff --git a/gateware/linien_module.py b/gateware/linien_module.py
 index 54b6285..c3f8d14 100644
 --- a/gateware/linien_module.py
 +++ b/gateware/linien_module.py
@@ -233,30 +233,52 @@ class LinienModule(Module, AutoCSR):
             self.fast_a.adc.eq(soc.analog.adc_a),
             self.fast_b.adc.eq(soc.analog.adc_b),
         ]
 -
         # now, we combine the output of the two paths, with a variable factor each.
         mixed = Signal(
             (2 + ((signal_width + 1) + self.logic.chain_a_factor.size), True)
         )
 +
 +        chain_a_factor_mult_fast_a_out_i = Signal(
 +            (2 + ((signal_width + 1) + self.logic.chain_a_factor.size), True)
 +        )
 +
 +        chain_b_factor_mult_fast_b_out_i = Signal(
 +            (2 + ((signal_width + 1) + self.logic.chain_a_factor.size), True)
 +        )
 +        combined_offset_signed_left_shifted = Signal(
 +            (2 + ((signal_width + 1) + self.logic.chain_a_factor.size), True)
 +        )
 +        fast_a_out_i_left_shifted = Signal(
 +            (2 + ((signal_width + 1) + self.logic.chain_a_factor.size), True)
 +        )
 +
 +        self.sync += [
 +            chain_a_factor_mult_fast_a_out_i.eq(self.logic.chain_a_factor.storage * self.fast_a.out_i),
 +            chain_b_factor_mult_fast_b_out_i.eq(self.logic.chain_b_factor.storage * self.fast_b.out_i),
 +            combined_offset_signed_left_shifted.eq(self.logic.combined_offset_signed << (chain_factor_bits + s)),
 +            fast_a_out_i_left_shifted.eq(self.fast_a.out_i << chain_factor_bits),
 +        ] 
 +
 +
         self.comb += [
             If(
                 self.logic.dual_channel.storage,
                 mixed.eq(
 -                    (self.logic.chain_a_factor.storage * self.fast_a.out_i)
 -                    + (self.logic.chain_b_factor.storage * self.fast_b.out_i)
 -                    + (self.logic.combined_offset_signed << (chain_factor_bits + s))
 +                    (chain_a_factor_mult_fast_a_out_i
 +                    + chain_b_factor_mult_fast_b_out_i
 +                    + combined_offset_signed_left_shifted) >> chain_factor_bits
                 ),
             ).Else(
                 mixed.eq(
 -                    (self.fast_a.out_i << chain_factor_bits)
 -                    + (self.logic.combined_offset_signed << (chain_factor_bits + s))
 -                )
 +                    (fast_a_out_i_left_shifted
 +                    + combined_offset_signed_left_shifted) >> chain_factor_bits
 +                ),
             )
         ]
         mixed_limited = Signal((signal_width, True))
 -        self.comb += [
 -            self.logic.limit_error_signal.x.eq(mixed >> chain_factor_bits),
 +        self.sync += [
 +            self.logic.limit_error_signal.x.eq(mixed),
             mixed_limited.eq(self.logic.limit_error_signal.y),
         ]
--- a/fast-servo/pid_err_sig_pipeline.patch
+++ b/fast-servo/pid_err_sig_pipeline.patch
@ -1,19 +0,0 @@
 diff --git a/gateware/logic/pid.py b/gateware/logic/pid.py
 index e737577..f1a4096 100644
 --- a/gateware/logic/pid.py
 +++ b/gateware/logic/pid.py
@@ -43,10 +43,12 @@ class PID(Module, AutoCSR):
         self.comb += [setpoint_signed.eq(self.setpoint.storage)]
         self.error = Signal((self.width + 1, True))
 +        error_reg = Signal((self.width + 1, True))
 +        self.sync += self.error.eq(error_reg)
         self.comb += [
 -            If(self.running, self.error.eq(self.input - self.setpoint.storage)).Else(
 -                self.error.eq(0)
 +            If(self.running, error_reg.eq(self.input - self.setpoint.storage)).Else(
 +                error_reg.eq(0)
             )
         ]
--- a/fast-servo/pid_pipeline.patch
+++ b/fast-servo/pid_pipeline.patch
@ -1,64 +0,0 @@
 diff --git a/gateware/logic/pid.py b/gateware/logic/pid.py
 index 4320f94..e737577 100644
 --- a/gateware/logic/pid.py
 +++ b/gateware/logic/pid.py
@@ -56,10 +56,13 @@ class PID(Module, AutoCSR):
         self.comb += [kp_signed.eq(self.kp.storage)]
         kp_mult = Signal((self.width + self.coeff_width, True))
 -        self.comb += [kp_mult.eq(self.error * kp_signed)]
 +        kp_mult_reg = Signal((self.width + self.coeff_width, True))
 +        self.sync += kp_mult.eq(kp_mult_reg >> (self.coeff_width - 2))
 +
 +        self.comb += [kp_mult_reg.eq(self.error * kp_signed)]
         self.output_p = Signal((self.width, True))
 -        self.comb += [self.output_p.eq(kp_mult >> (self.coeff_width - 2))]
 +        self.comb += [self.output_p.eq(kp_mult)]
         self.kp_mult = kp_mult
@@ -71,8 +74,10 @@ class PID(Module, AutoCSR):
         self.comb += [ki_signed.eq(self.ki.storage)]
         self.ki_mult = Signal((1 + self.width + self.coeff_width, True))
 +        self.ki_mult_reg = Signal((1 + self.width + self.coeff_width, True))
 +        self.sync += self.ki_mult.eq(self.ki_mult_reg)
 +        self.comb += self.ki_mult_reg.eq((self.error * ki_signed) >> 4)
 -        self.comb += [self.ki_mult.eq((self.error * ki_signed) >> 4)]
         int_reg_width = self.width + self.coeff_width + 4
         extra_width = int_reg_width - self.width
@@ -110,15 +115,17 @@ class PID(Module, AutoCSR):
         self.kd = CSRStorage(self.coeff_width)
         kd_signed = Signal((self.coeff_width, True))
         kd_mult = Signal((mult_width, True))
 +        kd_mult_reg = Signal((mult_width, True))
 +        self.sync += kd_mult.eq(kd_mult_reg)
 -        self.comb += [kd_signed.eq(self.kd.storage), kd_mult.eq(self.error * kd_signed)]
 +        self.comb += [kd_signed.eq(self.kd.storage), kd_mult_reg.eq(self.error * kd_signed >> (self.coeff_width - self.d_shift))]
         kd_reg = Signal((out_width, True))
         kd_reg_r = Signal((out_width, True))
         self.output_d = Signal((out_width, True))
         self.sync += [
 -            kd_reg.eq(kd_mult >> (self.coeff_width - self.d_shift)),
 +            kd_reg.eq(kd_mult),
             kd_reg_r.eq(kd_reg),
             self.output_d.eq(kd_reg - kd_reg_r),
         ]
@@ -143,4 +150,10 @@ class PID(Module, AutoCSR):
         # sync is required here, otherwise we get artifacts when one of the
         # signals changes sign
 -        self.sync += [self.pid_sum.eq(self.output_p + self.int_out + self.output_d)]
 +        self.sync += [
 +            If(
 +                self.running,
 +                self.pid_sum.eq(self.output_p + self.int_out + self.output_d),
 +            )
 +            .Else(self.pid_sum.eq(0))
 +        ]
--- a/fast-servo/pyfastservo/adc.py
+++ b/fast-servo/pyfastservo/adc.py
@ -17,7 +17,7 @@
 # You should have received a copy of the GNU General Public License
 # along with this program. If not, see <https://www.gnu.org/licenses/>.
-import time
+
 import spidev
 from pyfastservo.common import (
    ADC_AFE_CTRL_ADDR,
@ -54,128 +54,108 @@ def spi_read(spi, address):
 def main_adc_config(spi, test_pattern):
    high_word = (test_pattern & 0xFF00) >> 8
    low_word = test_pattern & 0xFF
    register_settings = {
        0x01: 0x20,                         # REGISTER A1: set to Two's complement Data Format
        0x02: 0x11,                         # REGISTER A2: set to LVDS output, set 4 data lanes
        0x03: high_word,                    # REGISTER A3: test pattern high word
        0x04: low_word,                     # REGISTER A4: test pattern low word
    }
-    spi_write(spi, 0x00, 0x80)              # Soft Reset
+    spi_write(spi, 0x00, 0x80)              # reset
-    for addr, val in register_settings.items():
+    spi_write(spi, 0x01, 0x20)              # REGISTER A1: set to Two's complement Data Format
-        spi_write(spi, addr, val)
+    spi_write(spi, 0x02, 0x15)              # REGISTER A2: set to LVDS output, set 4 data lanes and turn on test mode
-    return verify_registers_vals(spi, register_settings)
+    spi_write(spi, 0x03, high_word)         # REGISTER A3: test pattern high word
-    
+    spi_write(spi, 0x04, low_word)          # REGISTER A4: test pattern low word
 def main_adc_test_mode(spi, enable):
-    value = spi_read(spi, 0x02)
+    reg_contents = 0x15 if enable else 0x11 # set to LVDS output, set 4 data lanes and turn on or off test mode
-    # set to LVDS output, set 4 data lanes and turn on or off test mode
+    spi_write(spi, 0x02, reg_contents)
    if enable:
        value |= 1 << 2
    else:
        value &= 0xfb
-    spi_write(spi, 0x02, value)
+def verify_adc_registers(spi, reg_to_check):
    return verify_registers_vals(spi, {0x02: value})
 def verify_registers_vals(spi, reg_to_check):
    for register, expected_value in reg_to_check.items():
        value = spi_read(spi, register)
        print(f"Spi readback register 0x{register:02x}: 0x{value:02x}")
        if value != expected_value:
-            print(f"Different value read than sent in reg 0x{register:02x}. Expected: 0x{expected_value:02x} Got: 0x{value:02x}")
+            print(f"Different value read than sent in reg 0x{register:02x}")
            return False
    return True
 def read_frame():
    return read_from_memory(ADC_FRAME_ADDR, 1)[0]
-def perform_word_alignment():
+def perform_bitslip():
    for i in range(4):
        current_frame = read_frame()
-        if current_frame & 0x0F != 0x0C:
+        if current_frame != 0x0C:
            print(f"Performing bitslip (iteration: {i}). Current frame: 0x{current_frame:02x}")
            write_to_memory(ADC_BITSLIP_ADDR, 1)
        else:
            print(f"No bitslip required; Current frame: 0x{current_frame:02x}")
-            break
+            return
 def find_edge():
    prev_frame = read_frame()
    transition = False
    for tap_delay in range(32):
        write_to_memory(ADC_DELAY_ADDR, tap_delay)
        current_frame = read_frame()
        print(f"Tap delay: {tap_delay}, Current frame: 0x{current_frame:02x}")
        print(f"prev_frame: 0x{prev_frame:02x}")
        if current_frame != prev_frame:
-            final_delay = ((tap_delay+1) // 2) + 2
+            if not transition:
-            print(f"Edge detected; setting iDelay to: {final_delay}")
+                transition = True
-            write_to_memory(ADC_DELAY_ADDR, final_delay)
+            else:
-            return True
+                final_delay = (tap_delay // 2) + 2
                print(f"Edge detected; setting iDelay to: {final_delay}")
                write_to_memory(ADC_DELAY_ADDR, final_delay)
                return
        prev_frame = current_frame
-    return False
+
    # If no edge detected
    final_delay = 11
    print(f"No edge detected; setting iDelay to: {final_delay}")
    write_to_memory(ADC_DELAY_ADDR, final_delay)
 def read_adc_channel(high_addr, low_addr):
    return (read_from_memory(high_addr, 1)[0] << 8) | read_from_memory(low_addr, 1)[0]
-def is_clk_aligned(spi, test_pattern):
+def print_adc_channels():
-    aligned = True
+    adc_ch0 = read_adc_channel(ADC_CH0_HIGH_ADDR, ADC_CH0_LOW_ADDR)
-    main_adc_test_mode(spi, True)
+    adc_ch1 = read_adc_channel(ADC_CH1_HIGH_ADDR, ADC_CH1_LOW_ADDR)
-    for i in range(100):
+    print(f"Final ADC_CH0: 0x{adc_ch0:04x}")
-        adc_ch0 = read_adc_channel(ADC_CH0_HIGH_ADDR, ADC_CH0_LOW_ADDR)
+    print(f"Final ADC_CH1: 0x{adc_ch1:04x}")
        adc_ch1 = read_adc_channel(ADC_CH1_HIGH_ADDR, ADC_CH1_LOW_ADDR)
        if adc_ch0 != test_pattern or adc_ch1 != test_pattern:
            aligned = False
            break
    main_adc_test_mode(spi, False)
    return aligned
 def enable_adc_afe(ch1_x10=False, ch2_x10=False):
    ctrl_value = (ch2_x10 << 1) | ch1_x10
    write_to_memory(ADC_AFE_CTRL_ADDR, ctrl_value)
    afe_ctrl = read_from_memory(ADC_AFE_CTRL_ADDR, 1)[0]
-    print(f"Configure ADC AFE Gain: ch1_10x: {"10x" if ch1_x10 else "1x"} | ch2_x10: {"10x" if ch2_x10 else "1x"}")
+    print(f"ADC_AFE_CTRL: 0x{afe_ctrl:02X}")
    return afe_ctrl
 def print_adc_channel(ch):
    if ch == 0:
        adc_ch0 = read_adc_channel(ADC_CH0_HIGH_ADDR, ADC_CH0_LOW_ADDR)
        print(f"Final ADC_CH0: 0x{adc_ch0:04x}")
    if ch == 1:
        adc_ch1 = read_adc_channel(ADC_CH1_HIGH_ADDR, ADC_CH1_LOW_ADDR)
        print(f"Final ADC_CH1: 0x{adc_ch1:04x}")
 def configure_ltc2195():
    print()
    print("### Initializing LTC2195 Adc")
    spi = spidev.SpiDev()
    spi.open(MAIN_ADC_BUS, MAIN_ADC_DEVICE)
    spi.max_speed_hz = 50000
    spi.mode = 0b00  # CPOL = 0 CPHA = 0
    spi.cshigh = False
    success = True
    try:
        spi.open(MAIN_ADC_BUS, MAIN_ADC_DEVICE)
        spi.max_speed_hz = 50000
        spi.mode = 0b00  # CPOL = 0 CPHA = 0
        spi.cshigh = False
        test_pattern = 0x811F
-        success &= main_adc_config(spi, test_pattern)
+        main_adc_config(spi, test_pattern)
-        
+
-        success &= perform_word_alignment()
+        verify_adc_registers(spi, {
-        if is_clk_aligned(spi, test_pattern):
+            0x01: 0x20,
-            print("PL Data and Clock Alignment is verified")
+            0x02: 0x15,
-        else:
+            0x03: (test_pattern & 0xFF00) >> 8,
-            success &= False
+            0x04: test_pattern & 0xFF
-            print("Error: Clocks are not aligned")
+        })
-        enable_adc_afe(ch1_x10=0, ch2_x10=0)
+
-    except Exception as e:
+        # Performing Word Align
-        print(f"Error configuring LTC2195: {e}")
+        perform_bitslip()
-        success = False
+        find_edge()
        print_adc_channels()
        main_adc_test_mode(spi, False)
        verify_adc_registers(spi, {0x02: 0x11})  # Verify test mode is off
        enable_adc_afe()
    finally:
        spi.close()
        if success:
            print("LTC2195 Adc init completed")
        else:
            print("LTC2195 Adc init failed")
        return success
 if __name__ == "__main__":
    configure_ltc2195()
--- a/fast-servo/pyfastservo/dac.py
+++ b/fast-servo/pyfastservo/dac.py
@ -37,17 +37,6 @@ MAIN_DAC_BUS = 2
 MAIN_DAC_DEVICE = 0
 DAC_VERSION = 0x0A
 def inc_ddr_clk_phase():
    curr_cfg = read_from_memory(CTRL_ADDR, 1)[0] & 0x07
    write_to_memory(CTRL_ADDR, 0x10 | curr_cfg) # Set MMCM Phase Shift to be INC
    write_to_memory(CTRL_ADDR, 0x18 | curr_cfg) # Assert MMCM Phase Shift EN High
    write_to_memory(CTRL_ADDR, curr_cfg)        # Deassert MMCM Phase Shift EN High
 def dec_ddr_clk_phase():
    curr_cfg = read_from_memory(CTRL_ADDR, 1)[0] & 0x07
    write_to_memory(CTRL_ADDR, 0x00 | curr_cfg) # Set MMCM Phase Shift to be DEC
    write_to_memory(CTRL_ADDR, 0x08 | curr_cfg) # Assert MMCM Phase Shift EN High
    write_to_memory(CTRL_ADDR, curr_cfg)        # Deassert MMCM Phase Shift EN High
 def spi_write(spi, address, value):
    spi.xfer2([address, value])
@ -56,15 +45,7 @@ def spi_read(spi, address):
    rx_buffer = spi.xfer2([0x80 | address, 0x00])
    return rx_buffer[1]
-def verify_registers_vals(spi, reg_to_check):
+def hard_reset(spi):
    for register, expected_value in reg_to_check.items():
        value = spi_read(spi, register)
        if value != expected_value:
            print(f"Different value read than sent in reg 0x{register:02x}. Expected: 0x{expected_value:02x} Got: 0x{value:02x}")
            return False
    return True
 def soft_reset(spi):
    spi_write(spi, 0x00, 0x10)  # Software reset
    spi_write(spi, 0x00, 0x00)  # Release software reset
    spi_read(spi, 0x00)         # Read reset address (necessary for reset to take effect)
@ -75,22 +56,14 @@ def check_version(spi):
    return version == DAC_VERSION
 def configure_dac(spi):
-    register_settings = {
+    power_down_reg = spi_read(spi, 0x01)
-        0x01: 0x40,      # Clear EXTREF bit for internal reference, 
+    spi_write(spi, 0x01, power_down_reg & ~(1 << 0))  # Clear EXTREF bit for internal reference
-        0x02: 0xB4,      # Enable 2's complement, IFirst: True, IRising: True, DCI_EN: Enabled
+    spi_write(spi, 0x0D, 0x00)      # Set RREF to 10 kΩ for 1.0V reference
-        0x0D: 0x00,      # Set RREF to 10 kΩ for 1.0V reference
+    spi_write(spi, 0x04, 0xA0)      # Enable on-chip IRSET (1.6 kΩ for 20mA output)
-        0x04: 0xA0,      # Enable on-chip IRSET (1.6 kΩ for 20mA output)
+    spi_write(spi, 0x07, 0xA0)      # Enable on-chip QRSET (1.6 kΩ for 20mA output)
-        0x07: 0xA0,      # Enable on-chip QRSET (1.6 kΩ for 20mA output)
+    spi_write(spi, 0x05, 0x00)      # Disable internal IRCML
-        0x05: 0x00,      # Disable internal IRCML
+    spi_write(spi, 0x08, 0x00)      # Disable internal QRCML
-        0x08: 0x00,      # Disable internal QRCML
+    spi_write(spi, 0x02, 0xB4)      # Enable 2's complement, LVDS interface, 4 LVDS lanes
    }
    for addr, val in register_settings.items():
        spi_write(spi, addr, val)
    success = verify_registers_vals(spi, register_settings)
    if success:
        # Set manual override output default back to 0V in 2's complement
        set_dac_input_override_value(0x0000)
    return success
 def dac_self_calibration(spi):
    spi_write(spi, 0x12, 0x00)      # Reset calibration status
@ -106,16 +79,15 @@ def dac_self_calibration(spi):
    spi_write(spi, 0x12, 0x00)      # Clear calibration bits
    spi_write(spi, 0x0E, 0x30)      # Keep CALSELI and CALSELQ set, clear CALCLK
-    print("DAC self-calibration completes")
+    print("DAC self-calibration completed")
    return True
-def set_dac_input_override(enable=True):
+def manual_override(enable=True):
    reg_contents = read_from_memory(CTRL_ADDR, 1)[0]
    print(f"REG contents: 0b{reg_contents:03b}")
    to_write = reg_contents | 0b1 if enable else reg_contents & 0b110
    write_to_memory(CTRL_ADDR, to_write)
    print(f"Enable DAC Input Override: {enable}")
-def power_down_afe(channel, power_down=True):
+def power_down(channel, power_down=True):
    assert channel in (0, 1)
    bitmask = 1 << (channel + 1) & 0b111
@ -126,42 +98,20 @@ def power_down_afe(channel, power_down=True):
    to_write = reg_contents | value
    write_to_memory(CTRL_ADDR, to_write)
    reg_contents = read_from_memory(CTRL_ADDR, 1)[0]
-    print(f"Power Down DAC AFE Ch{channel}: {power_down}")
+    print(f"REG contents: 0b{reg_contents:03b}")
-def set_dac_input_override_value(value):
+def set_dac_output(value):
    value = min(value, 0x3FFF)
    low_word = value & 0xFF
    high_word = (value >> 8) & 0x3F
    # Note: DAC HIGH word and LOW word output are not updated 
    #   at the same time. On scope, you will see more than one step
    #   of value changed.
    write_to_memory(CH0_HIGH_WORD_ADDR, high_word)
    write_to_memory(CH0_LOW_WORD_ADDR, low_word)
    write_to_memory(CH1_HIGH_WORD_ADDR, high_word)
    write_to_memory(CH1_LOW_WORD_ADDR, low_word)
-    print(f"Set DAC Input Override Value to: 0x{value:04X}")
+    print(f"DAC output set to: 0x{value:04X}")
 def check_clk_relationship(spi):
    # Trigger the retimer to reacquire the clock relationship
    spi_write(spi, 0x14, 0x00)
    spi_write(spi, 0x14, 0x08)
    spi_write(spi, 0x14, 0x00)
    clkmode_reg = spi_read(spi, 0x14)
    print(f"AD9117 CLKMODE reg: 0x{clkmode_reg:02X}")
    if clkmode_reg & 0b00010000:
        print("Ad9117 Clock relationship is established")
        return False
    else:
        print("Ad9117 Clock relationship is found")
        return True
 def configure_ad9117():
    print()
    print("### Initializing AD9117 Dac")
    success = True
    spi = spidev.SpiDev()
    spi.open(MAIN_DAC_BUS, MAIN_DAC_DEVICE)
    spi.max_speed_hz = 5000
@ -169,35 +119,28 @@ def configure_ad9117():
    spi.cshigh = False
    try:
-        soft_reset(spi)
+        hard_reset(spi)
        if not check_version(spi):
            print("Unrecognized DAC version")
            return False
-        # Disable DAC Output during Initialization
+        configure_dac(spi)
-        spi_write(spi, 0x01, 0x46)
+        dac_self_calibration(spi)
        success &= verify_registers_vals(spi, {0x01: 0x46})
-        success &= configure_dac(spi)
+        power_down(0, False)
-        success &= check_clk_relationship(spi)
+        power_down(1, False)
-        success &= dac_self_calibration(spi)
+        manual_override(True)
-        power_down_afe(0, False)
+        # Enable DAC outputs
-        power_down_afe(1, False)
+        spi_write(spi, 0x01, spi_read(spi, 0x01) & ~((1 << 4) | (1 << 3)))
-        if success:
+        print("AD9117 configuration completed successfully")
-            set_dac_input_override(False)
+        return True
            # Re-Enable DAC Output
            spi_write(spi, 0x01, 0x40)
            verify_registers_vals(spi, {0x01: 0x40})
            print("AD9117 Dac init completed")
        else:
            print("AD9117 Dac init fails")
        return success
    except Exception as e:
-        print(f"Error configuring AD9117 Dac: {e}")
+        print(f"Error configuring AD9117: {e}")
        return False
    finally:
        spi.close()
--- a/fast-servo/pyfastservo/initialize.py
+++ b/fast-servo/pyfastservo/initialize.py
@ -20,30 +20,9 @@
 from pyfastservo import adc, si5340, dac
 def main():
-    print()
+    si5340.configure_si5340()
-    print("### PL Initialization")
+    adc.configure_ltc2195()
-    print()
+    dac.configure_ad9117()
    # Set output voltage to be 0V after AD9117-2 soft reset
    # DAC starts up in unsigned Data Format. Set DAC to output 0V before Clock is provided to it
    dac.set_dac_input_override_value(0x1FFF)
    dac.set_dac_input_override(True)
    si5340_ok = si5340.configure_si5340()
    adc_ok = adc.configure_ltc2195()
    dac_ok = dac.configure_ad9117()
    if si5340_ok and adc_ok and dac_ok:
        print()
        print("### PL init success")
        print()
    else:
        print()
        print("### Something is wrong with PL init")
        print(f"Si5340 Clock Generator Init Status: {"Success" if si5340_ok else "Failed"}")
        print(f"LTC2195 Adc Init Status: {"Success" if adc_ok else "Failed"}")
        print(f"Ad9117 Dac Init Status: {"Success" if dac_ok else "Failed"}")
        print()
 if __name__ == "__main__":
    main()
--- a/fast-servo/pyfastservo/si5340.py
+++ b/fast-servo/pyfastservo/si5340.py
@ -35,15 +35,6 @@ STATUS_LOSREF = 0x04
 STATUS_LOL = 0x08
 def write_register(bus, address, value):
    page = address >> 8
    register = address & 0xFF
    bus.write_byte_data(IC_ADDR, 0x01, page)
    try:
        bus.write_byte_data(IC_ADDR, register, value)
    except Exception as e:
        raise Exception(f"Write failed 0x{value:02X} at 0x{address:04X}: {e}")
 def write_preamble(bus):
    preamble = [
        (0x0B24, 0xC0),
@ -54,7 +45,7 @@ def write_preamble(bus):
        (0x0B4E, 0x1A),
    ]
    for address, value in preamble:
-        write_register(bus, address, value)
+        bus.write_byte_data(IC_ADDR, address, value)
 def write_postamble(bus):
    postamble = [
@ -63,7 +54,7 @@ def write_postamble(bus):
        (0x0B25, 0x02),
    ]
    for address, value in postamble:
-        write_register(bus, address, value)
+        bus.write_byte_data(IC_ADDR, address, value)
 def wait_device_ready(bus):
    for _ in range(15):
@ -93,8 +84,6 @@ def check_los_status(bus):
    return not xaxb_los
 def configure_si5340():
    print()
    print("### Initializing Si5340 Clock Generator")
    with SMBus(BUS_NO) as bus:
        if not wait_device_ready(bus):
            print("Device not ready. Aborting.")
@ -145,8 +134,8 @@ def configure_si5340():
            (0x0235, 0x00),  # M_NUM
            (0x0236, 0x00),
            (0x0237, 0x00),
-            (0x0238, 0xA0),
+            (0x0238, 0x80),
-            (0x0239, 0x8C),
+            (0x0239, 0x89),
            (0x023A, 0x00),
            (0x023B, 0x00),  # M_DEN
            (0x023C, 0x00),
@ -158,13 +147,13 @@ def configure_si5340():
            (0x0303, 0x00),
            (0x0304, 0x00),
            (0x0305, 0x00),
-            (0x0306, 0x1B),
+            (0x0306, 0x21),
            (0x0307, 0x00),
            (0x0308, 0x00),  # N0_DEN
            (0x0309, 0x00),
            (0x030A, 0x00),
            (0x030B, 0x80),
-            (0x030C, 0x01),  # N0_UPDATE
+            (0x030C, 0x01), # N0_UPDATE
            # N1 Configuration (1:1 ratio)
            (0x030D, 0x00),  # N1_NUM
@ -172,11 +161,11 @@ def configure_si5340():
            (0x030F, 0x00),
            (0x0310, 0x00),
            (0x0311, 0x00),
-            (0x0312, 0x00),
+            (0x0312, 0x01),
            (0x0313, 0x00),  # N1_DEN
            (0x0314, 0x00),
            (0x0315, 0x00),
-            (0x0316, 0x00),
+            (0x0316, 0x01),
            (0x0317, 0x01),  # N1_UPDATE
            # N2 Configuration (1:1 ratio)
@ -185,11 +174,11 @@ def configure_si5340():
            (0x031A, 0x00),
            (0x031B, 0x00),
            (0x031C, 0x00),
-            (0x031D, 0x00),
+            (0x031D, 0x01),
            (0x031E, 0x00),  # N2_DEN
            (0x031F, 0x00),
            (0x0320, 0x00),
-            (0x0321, 0x00),
+            (0x0321, 0x01),
            (0x0322, 0x01),  # N2_UPDATE
            # N3 Configuration (1:1 ratio)
@ -198,11 +187,11 @@ def configure_si5340():
            (0x0325, 0x00),
            (0x0326, 0x00),
            (0x0327, 0x00),
-            (0x0328, 0x00),
+            (0x0328, 0x01),
            (0x0329, 0x00),  # N3_DEN
            (0x032A, 0x00),
            (0x032B, 0x00),
-            (0x032C, 0x00),
+            (0x032C, 0x01),
            (0x032D, 0x01),  # N3_UPDATE
            # Output configuration
@ -255,7 +244,7 @@ def configure_si5340():
        print("Writing main configuration...")
        for address, value in main_config:
-            write_register(bus, address, value)
+            bus.write_byte_data(IC_ADDR, address, value)
        print("Main configuration written")
        write_postamble(bus)
@ -273,13 +262,10 @@ def configure_si5340():
        if not pll_locked:
            print("Error: PLL is not locked")
            return False
        elif not xaxb_signal_present:
            print("Error: XA/XB signal is lost")
            return False
        else:
-            print("Si5340 init completed")
+            print("Si5340 configuration completed successfully")
            return True
 if __name__ == "__main__":
    configure_si5340()
--- a/flake.lock
+++ b/flake.lock
@ -18,16 +18,16 @@
    },
    "nixpkgs": {
      "locked": {
-        "lastModified": 1736867362,
+        "lastModified": 1709237383,
-        "narHash": "sha256-i/UJ5I7HoqmFMwZEH6vAvBxOrjjOJNU739lnZnhUln8=",
+        "narHash": "sha256-cy6ArO4k5qTx+l5o+0mL9f5fa86tYUX3ozE1S+Txlds=",
        "owner": "NixOS",
        "repo": "nixpkgs",
-        "rev": "9c6b49aeac36e2ed73a8c472f1546f6d9cf1addc",
+        "rev": "1536926ef5621b09bba54035ae2bb6d806d72ac8",
        "type": "github"
      },
      "original": {
        "owner": "NixOS",
-        "ref": "nixos-24.11",
+        "ref": "nixos-unstable",
        "repo": "nixpkgs",
        "type": "github"
      }
@ -40,11 +40,11 @@
        ]
      },
      "locked": {
-        "lastModified": 1736697818,
+        "lastModified": 1699416673,
-        "narHash": "sha256-JqqQO9W2s64vt6q2XrAY1ml0l7ff+7HbY5xCUhJJFmM=",
+        "narHash": "sha256-uJ6QnU7hFUYZsz6J/HIBEpLW0bS7GLQOo6ccKtoZ68k=",
        "owner": "cleverca22",
        "repo": "not-os",
-        "rev": "c556294ad82fb256082ca0a787cc5da7cb4e91e3",
+        "rev": "79ff6e6fe0b64bf8b8d38363b2bb0dea0cd5a686",
        "type": "github"
      },
      "original": {
@ -64,11 +64,11 @@
    "src-migen": {
      "flake": false,
      "locked": {
-        "lastModified": 1735131698,
+        "lastModified": 1702942348,
-        "narHash": "sha256-P4vaF+9iVekRAC2/mc9G7IwI6baBpPAxiDQ8uye4sAs=",
+        "narHash": "sha256-gKIfHZxsv+jcgDFRW9mPqmwqbZXuRvXefkZcSFjOGHw=",
        "owner": "m-labs",
        "repo": "migen",
-        "rev": "4c2ae8dfeea37f235b52acb8166f12acaaae4f7c",
+        "rev": "50934ad10a87ade47219b796535978b9bdf24023",
        "type": "github"
      },
      "original": {
@ -80,11 +80,11 @@
    "src-misoc": {
      "flake": false,
      "locked": {
-        "lastModified": 1736416570,
+        "lastModified": 1699352904,
-        "narHash": "sha256-tbcN/fzejZIaYbTbwk8Ir1glYevESqMinMeDB3z8oxg=",
+        "narHash": "sha256-SglyTmXOPv8jJOjwAjJrj/WhAkItQfUbvKfUqrynwRg=",
        "ref": "refs/heads/master",
-        "rev": "1f5318e9edc1085ac77e9b85b8f5e03371dba54c",
+        "rev": "a53859f2167c31ab5225b6c09f30cf05527b94f4",
-        "revCount": 2464,
+        "revCount": 2452,
        "submodules": true,
        "type": "git",
        "url": "https://github.com/m-labs/misoc.git"
--- a/flake.nix
+++ b/flake.nix
@ -1,7 +1,7 @@
 {
  description = "Firmware for Sinara Fast-Servo based on Not-OS and Linien";
-  inputs.nixpkgs.url = github:NixOS/nixpkgs/nixos-24.11;
+  inputs.nixpkgs.url = github:NixOS/nixpkgs/nixos-unstable;
  inputs.not-os.url = github:cleverca22/not-os;
  inputs.not-os.inputs.nixpkgs.follows = "nixpkgs";
@ -14,43 +14,6 @@
      pkgs-armv7l = pkgs.pkgsCross.zynq-armv7l-linux;
      fsbl-support = ./fast-servo/fsbl-support;
      version = "2.1.0";
      linien-src = pkgs.applyPatches {
          name = "linien-src";
          src = pkgs.fetchFromGitHub {
            owner = "linien-org";
            repo = "linien";
            rev = "v" + version;
            sha256 = "sha256-j6oiP/usLfV5HZtKLcXQ5pHhhxRG05kP2FMwingiWm0=";
          };
          prePatch = ''
            mkdir -p fast_servo/gateware
            cp -r ${./fast-servo/linien-gateware}/. fast_servo/gateware
          '';
          patches = [
            ./fast-servo/linien-common-fast-servo-hardware-specific.patch
            ./fast-servo/linien-server-fast-servo-hardware-specific.patch
            ./fast-servo/linien-gui-fast-servo-hardware-specific.patch
            ./fast-servo/linien-gui-add-afe_gain-combo-boxes.patch
            ./fast-servo/linien-gui-do-not-use-opengl.patch
            ./fast-servo/linien-gui-hide-password-box.patch
            ./fast-servo/linien-gui-do-not-check-for-update.patch
            ./fast-servo/linien-client-ssh-port-change.patch
            ./fast-servo/linien-server-fast-servo.patch
            ./fast-servo/linien-server-cli.patch
            ./fast-servo/linien-server-add-afe_ctrl-regs.patch
            ./fast-servo/linien-server-shutdown-control.patch
            ./fast-servo/linien-gateware-fast-servo.patch 
            ./fast-servo/linien-gateware-autolock-pipeline.patch
            ./fast-servo/linien-module-iir-coeff-width-set-to-18bit.patch
            ./fast-servo/linien_module_pipeline.patch
            ./fast-servo/pid_pipeline.patch
            ./fast-servo/pid_err_sig_pipeline.patch
            ./fast-servo/linien-gateware-chain-pipeline.patch
            ./fast-servo/linien-demodulate_add_pipeline.patch
          ];
      };
      patched-not-os = pkgs.applyPatches {
        name = "not-os-patched";
        src = not-os;
@ -61,9 +24,6 @@
          ./not-os-patches/pr-30.patch
          ./not-os-patches/pr-31.patch
          ./not-os-patches/pr-33.patch
          ./not-os-patches/pr-34.patch
          ./not-os-patches/iproute2.patch
          ./not-os-patches/user_defined_ip_settings.patch
        ];
      };
@ -136,44 +96,29 @@
          freetype
          fontconfig
        ];
-        profile = "set -e; source /opt/Xilinx/Vivado/2024.2/settings64.sh";
+        profile = "set -e; source /opt/Xilinx/Vivado/2022.2/settings64.sh";
        runScript = "vivado";
      };
      cma = pkgs-armv7l.python3Packages.buildPythonPackage rec {
        pname = "cma";
        version = "3.3.0";
        src = pkgs.fetchFromGitHub {
          owner = "CMA-ES";
          repo = "pycma";
          rev = "refs/tags/r${version}";
          hash = "sha256-+UJI3hDVbDMfRF4bkwHED3eJCHzxS2hO4YPUzJqcoQI=";
        };
        propagatedBuildInputs = [ pkgs-armv7l.python3Packages.numpy ];
        pythonImportsCheck = [ "cma" ];
        checkPhase = ''
          # At least one doctest fails, thus only limited amount of files is tested
          python -m cma.test interfaces.py purecma.py logger.py optimization_tools.py transformations.py
        '';
      };
      pyrp3 = pkgs-armv7l.python3Packages.buildPythonPackage rec {
        pname = "pyrp3";
-        version = "2.1.0";
+        version = "1.2.0";
-        format = "pyproject";
+        pyproject = true;
        src = pkgs.fetchFromGitHub {
          owner = "linien-org";
          repo = "pyrp3";
          rev = "v${version}";
-          hash = "sha256-ol1QGXyCOei94iIPIocuTRHBxa5jKSH5RzjzROfZaBI=";
+          hash = "sha256-43TTlpJ5SMAjQM71bNVvrWQyciRXM3zpuA/Dw41AEgU=";
        };
        patches = ./fast-servo/linien-pyrp3-monitor.patch;
-        nativeBuildInputs = [
+        nativeBuildInputs = with pkgs-armv7l.python3Packages; [
-          pkgs-armv7l.python3Packages.setuptools
+          setuptools wheel setuptools-scm
-          pkgs-armv7l.gcc
+        ] ++ (with pkgs-armv7l; [ gcc gnumake ]);
        propagatedBuildInputs = with pkgs-armv7l.python3Packages; [
          myhdl
          rpyc4
          cached-property
          numpy
        ];
        postInstall = ''
          cp monitor/libmonitor.so $out/lib
@ -182,141 +127,13 @@
          substituteInPlace $out/${pkgs.python3.sitePackages}/pyrp3/raw_memory.py \
            --replace "libmonitor.so" "$out/lib/libmonitor.so"
        '';
        propagatedBuildInputs = with pkgs-armv7l.python3Packages; [
          cached-property
          numpy
          rpyc
        ];
      };
      linien-common = pkgs.python3Packages.buildPythonPackage rec {
        pname = "linien-common";
        inherit version;
        pyproject = true;
        src = linien-src;
        sourceRoot = "${src.name}/linien-common";
        preBuild = ''
          export HOME=$(mktemp -d)
        '';
        nativeBuildInputs = [ pkgs.python3Packages.setuptools ];
        pythonRelaxDeps = [ "importlib-metadata" ];
        propagatedBuildInputs = with pkgs.python3Packages; [
          importlib-metadata
          numpy
          rpyc
          scipy
          appdirs
        ];
        pythonImportsCheck = [ "linien_common" ];
      };
      linien-common-armv7l = pkgs-armv7l.python3Packages.buildPythonPackage rec {
        pname = "linien-common-armv7l";
        inherit version;
        pyproject = true;
        src = linien-src;
        sourceRoot = "${src.name}/linien-common";
        preBuild = ''
          export HOME=$(mktemp -d)
        '';
        nativeBuildInputs = [ pkgs-armv7l.python3Packages.setuptools ];
        pythonRelaxDeps = [ "importlib-metadata" ];
        propagatedBuildInputs = with pkgs-armv7l.python3Packages; [
          importlib-metadata
          numpy
          rpyc
          scipy
          appdirs
        ];
        pythonImportsCheck = [ "linien_common" ];
      };
      linien-client = pkgs.python3Packages.buildPythonPackage rec {
        pname = "linien-client";
        inherit version;
        src = linien-src;
        pyproject = true;
        sourceRoot = "${src.name}/linien-client";
        preBuild = ''
          export HOME=$(mktemp -d)
        '';
        nativeBuildInputs = [ pkgs.python3Packages.setuptools ];
        doInstallCheck = false;
        doCheck = false;
        propagatedBuildInputs = with pkgs.python3Packages; [
          fabric
          typing-extensions
        ] ++ [ linien-common ];
        pythonImportsCheck = [ "linien_client" ];
        };
      linien-gui = pkgs.python3Packages.buildPythonApplication rec {
        pname = "linien-gui";
        inherit version;
        src = linien-src;
        pyproject = true;
        sourceRoot = "${src.name}/linien-gui";
        nativeBuildInputs = with pkgs.python3Packages; [
          setuptools
        ] ++ [
          pkgs.qt5.wrapQtAppsHook
        ];
        patches = [
          ./fast-servo/linien-gui-fast-servo-rm-ota-update.patch
        ];
        # Makes qt-wayland appear in the qt paths injected by the wrapper - helps users
        # with `QT_QPA_PLATFORM=wayland` in their environment.
        buildInputs = [
          pkgs.qt5.qtwayland
        ];
        propagatedBuildInputs = with pkgs.python3Packages; [
          click
          pyqtgraph
          pyqt5
          requests
          superqt
        ] ++ [ linien-client ];
        dontWrapQtApps = true;
        preFixup = ''
          makeWrapperArgs+=("''${qtWrapperArgs[@]}")
        '';
      };
      linien-server = pkgs-armv7l.python3Packages.buildPythonPackage rec {
        pname = "linien-server";
        inherit version;
        src = linien-src;
        pyproject = true;
-
+        inherit (pkgs.python3Packages.linien-common) src version;
-        sourceRoot = "${src.name}/linien-server";
+        sourceRoot = "source/linien-server";
        postPatch = ''
          cp ${fast-servo-gateware}/csrmap.py linien_server/csrmap.py
          substituteInPlace linien_server/acquisition.py \
@ -326,19 +143,28 @@
        '';
        nativeBuildInputs = [ pkgs-armv7l.python3Packages.setuptools ];
        propagatedBuildInputs = with pkgs-armv7l.python3Packages; [
-          fire
+          appdirs
-          influxdb-client
+          certifi
-          pylpsd
+          click
        ] ++ [ 
          linien-common-armv7l
          cma
          pylpsd
          pyrp3
          requests
          linien-common
        ];
      };
      fast-servo-gateware = pkgs.stdenv.mkDerivation rec {
        name = "fast-servo-gateware";
-        src = linien-src;
+        inherit (pkgs.python3Packages.linien-common) src;
        prePatch = ''
          mkdir -p fast_servo/gateware
          cp -r ${./fast-servo/linien-gateware}/. fast_servo/gateware
        '';
        patches = [
          fast-servo/linien-fast-servo-gateware.patch
          fast-servo/linien-fast-servo-server.patch
        ];
        nativeBuildInputs = [
          (pkgs.python3.withPackages(ps: [
            migen misoc
@ -359,7 +185,6 @@
        installPhase = ''
          mkdir -p $out $out/nix-support
          cp gateware/build/top.bit $out
          cp gateware/build $out -r
          cp linien-server/linien_server/gateware.bin $out
          cp linien-server/linien_server/csrmap.py $out
          echo file binary-dist $out/top.bit >> $out/nix-support/hydra-build-products
@ -419,7 +244,8 @@
          ] ++ pkgs.lib.optionals (board == "fast-servo") [
            ({ config, pkgs, lib, ... }: {
              environment.systemPackages = [
-                (pkgs.python3.withPackages(ps: with ps; [ pyfastservo linien-server]))
+                linien-server
                (pkgs.python3.withPackages(ps: [ pyfastservo ]))
              ];
              boot.postBootCommands = lib.mkAfter ''
@ -431,7 +257,8 @@
                cp ${fast-servo-gateware}/gateware.bin /lib/firmware/
                echo gateware.bin > /sys/class/fpga_manager/fpga0/firmware
-                # Initialize All PL Peripherals
+                # Run device init scripts
                echo "Initializing clock generator, ADC, and DAC..."
                python3 -m pyfastservo.initialize
              '';
            })];
@ -647,19 +474,8 @@
        "${board}-dtb" = dtb;
        "${board}-sd-image" = sd-image;
        "${board}-qemu" = not-os-qemu;
        "${board}-gui" = linien-gui;
      };
    in rec {
      devShell.x86_64-linux = pkgs.mkShell {
        name = "nix-servo-dev_shell";
        packages = [
          vivado
        ];
        buildInputs = with pkgs.python3Packages; [ 
          matplotlib
        ] ++ [ linien-common linien-client linien-gui ];
      };
      packages.x86_64-linux = {
        inherit mkbootimage;
        inherit migen misoc vivado;
--- a/not-os-patches/iproute2.patch
+++ b/not-os-patches/iproute2.patch
@ -1,13 +0,0 @@
 diff --git a/system-path.nix b/system-path.nix
 index 490197d..93e940a 100644
 --- a/system-path.nix
 +++ b/system-path.nix
@@ -6,7 +6,7 @@
 with lib;
 let
 -  requiredPackages = with pkgs; [ utillinux coreutils iproute iputils procps bashInteractive runit ];
 +  requiredPackages = with pkgs; [ utillinux coreutils iproute2 iputils procps bashInteractive runit ];
 in
 {
   options = {
--- a/not-os-patches/network.patch
+++ b/not-os-patches/network.patch
@ -1,5 +1,5 @@
 diff --git a/configuration.nix b/configuration.nix
-index 010c487..2d08009 100644
+index 010c487..e1e85ba 100644
 --- a/configuration.nix
 +++ b/configuration.nix
@@ -1,4 +1,4 @@
@ -8,7 +8,7 @@ index 010c487..2d08009 100644
 {
   imports = [ ./qemu.nix ];
-@@ -7,10 +7,16 @@
+@@ -7,10 +7,15 @@
   environment.etc = {
     "ssh/authorized_keys.d/root" = {
       text = ''
@ -18,7 +18,6 @@ index 010c487..2d08009 100644
 +        ecdsa-sha2-nistp384 AAAAE2VjZHNhLXNoYTItbmlzdHAzODQAAAAIbmlzdHAzODQAAABhBNdIiLvP2hmDUFyyE0oLOIXrjrMdWWpBV9/gPR5m4AiARx4JkufIDZzmptdYQ5FhJORJ4lluPqp7dAmahoSwg4lv9Di0iNQpHMJvNGZLHYKM1H1FWCCFIEDJ8bD4SVfrDg== root
 +        ecdsa-sha2-nistp384 AAAAE2VjZHNhLXNoYTItbmlzdHAzODQAAAAIbmlzdHAzODQAAABhBF/YybP+fQ0J+bNqM5Vgx5vDmVqVWsgUdF1moUxghv7d73GZAFaM6IFBdrXTAa33AwnWwDPMrTgP1V6SXBkb3ciJo/lD1urJGbydbSI5Ksq9d59wvOeANvyWYrQw6+eqTQ== sb
 +        ecdsa-sha2-nistp384 AAAAE2VjZHNhLXNoYTItbmlzdHAzODQAAAAIbmlzdHAzODQAAABhBFkmOCQ3BQh3qUjLtfdqyeBsx8rkk/QYlzB0TMrnfn6waLN6yKfPC3WVFv4zN5kNKb/OayvqDa+zfkKe85e/oIPQQKflF7GrCHdssz33DCnW90cz532E6iqG1pjeZjID2A== flo
 +        ssh-ed25519 AAAAC3NzaC1lZDI1NTE5AAAAICAranL376soiSJ0kxdYNrwElcaZPW1heLFjs8Y7n0jT linuswck
       '';
       mode = "0444";
     };
@ -28,15 +27,11 @@ index 010c487..2d08009 100644
   };
 }
 diff --git a/runit.nix b/runit.nix
-index d7b0bf3..14dd437 100644
+index d7b0bf3..67cff43 100644
 --- a/runit.nix
 +++ b/runit.nix
-@@ -4,11 +4,11 @@ let
+@@ -7,8 +7,8 @@ let
-   sshd_config = pkgs.writeText "sshd_config" ''
+     Port 22
     HostKey /etc/ssh/ssh_host_rsa_key
     HostKey /etc/ssh/ssh_host_ed25519_key
 -    Port 22
 +    Port 3030
     PidFile /run/sshd.pid
     Protocol 2
 -    PermitRootLogin yes
--- a/not-os-patches/pr-28.patch
+++ b/not-os-patches/pr-28.patch
@ -1,5 +1,5 @@
 diff --git a/base.nix b/base.nix
-index 7eaee32..9aa338e 100644
+index 7eaee32..3a2a0a9 100644
 --- a/base.nix
 +++ b/base.nix
@@ -27,6 +27,11 @@ with lib;
@ -14,12 +14,9 @@ index 7eaee32..9aa338e 100644
     not-os.simpleStaticIp = mkOption {
       type = types.bool;
       default = false;
-@@ -84,17 +89,25 @@ with lib;
+@@ -86,15 +91,25 @@ with lib;
     };
     environment.etc = {
       "nix/nix.conf".source = pkgs.runCommand "nix.conf" {} ''
-        extraPaths=$(for i in $(cat ${pkgs.writeReferencesToFile pkgs.runtimeShell}); do if test -d $i; then echo $i; fi; done)
+         extraPaths=$(for i in $(cat ${pkgs.writeReferencesToFile pkgs.runtimeShell}); do if test -d $i; then echo $i; fi; done)
 +        extraPaths=$(for i in $(cat ${pkgs.writeClosure [ pkgs.bash ]}); do if test -d $i; then echo $i; fi; done)
         cat > $out << EOF
 -        build-use-sandbox = true
 +        auto-optimise-store = true
@ -31,6 +28,8 @@ index 7eaee32..9aa338e 100644
 +        extra-sandbox-paths = /bin/sh=${pkgs.runtimeShell} $(echo $extraPaths)
 +        max-jobs = auto
 +        sandbox = true
 +        substituters = https://cache.armv7l.xyz
 +        trusted-public-keys = cache.armv7l.xyz-1:kBY/eGnBAYiqYfg0fy0inWhshUo+pGFM3Pj7kIkmlBk=
 +        trusted-users = root
         EOF
       '';
@ -152,7 +151,7 @@ index c61f9d6..fbdf0fd 100644
   };
 }
 diff --git a/zynq_image.nix b/zynq_image.nix
-index 3fa23ab..069fe89 100644
+index 3fa23ab..9d1621e 100644
 --- a/zynq_image.nix
 +++ b/zynq_image.nix
@@ -1,66 +1,89 @@
@ -164,7 +163,7 @@ index 3fa23ab..069fe89 100644
 -  # dont use overlays for the qemu, it causes a lot of wasted time on recompiles
 -  x86pkgs = import pkgs.path { system = "x86_64-linux"; };
 -  customKernel = pkgs.linux.override {
-+  customKernel = (pkgs.linux_6_6.override {
+  customKernel = (pkgs.linux.override {
     extraConfig = ''
       OVERLAY_FS y
 +      MEDIA_SUPPORT n
@ -250,7 +249,7 @@ index 3fa23ab..069fe89 100644
 -  environment.etc."service/getty/run".source = pkgs.writeShellScript "getty" ''
 -    agetty ttyPS0 115200
 +  environment = {
-+    systemPackages = with pkgs; [ inetutils wget gnugrep nano vim ];
+    systemPackages = with pkgs; [ inetutils wget nano ];
 +    etc = {
 +      "service/getty/run".source = pkgs.writeShellScript "getty" ''
 +        hostname ${config.networking.hostName}
--- a/not-os-patches/pr-29.patch
+++ b/not-os-patches/pr-29.patch
@ -26,3 +26,16 @@ index 7eaee32..c1881cb 100644
     # nix-build -A system.build.toplevel && du -h $(nix-store -qR result) --max=0 -BM|sort -n
     system.build.toplevel = pkgs.runCommand "not-os" {
 diff --git a/systemd-compat.nix b/systemd-compat.nix
 index 11464c6..cb223b8 100644
 --- a/systemd-compat.nix
 +++ b/systemd-compat.nix
@@ -9,6 +9,8 @@ with lib;
     };
     systemd.user = mkOption {
     };
 +    systemd.tmpfiles = mkOption {
 +    };
   };
   config = {
   };
--- a/not-os-patches/pr-33.patch
+++ b/not-os-patches/pr-33.patch
@ -394,10 +394,10 @@ index 0000000..53c5349
 \ No newline at end of file
 diff --git a/xilinx-fpga-manager.patch b/xilinx-fpga-manager.patch
 new file mode 100644
-index 0000000..33daffe
+index 0000000..59aa585
 --- /dev/null
 +++ b/xilinx-fpga-manager.patch
-@@ -0,0 +1,676 @@
+@@ -0,0 +1,663 @@
 +# Enable user-space interface for PL programming via Linux FPGA manager
 +# diff cherry-picked from Xilinx/linux-xilinx/tree/xlnx_rebase_v6.6_LTS
 +# commit IDs: e61c0a9, 0a38712, dc67651, 89a24e3, 8d224b1, 2a9c05f, 4e94580
@ -425,7 +425,7 @@ index 0000000..33daffe
 + 	tristate "Altera SOCFPGA FPGA Manager"
 + 	depends on ARCH_INTEL_SOCFPGA || COMPILE_TEST
 +diff --git a/drivers/fpga/fpga-mgr.c b/drivers/fpga/fpga-mgr.c
-+index 0f4035b089a2..3aa9f5f041f6 100644
+index 06651389c592..6e8c45974f28 100644
 +--- a/drivers/fpga/fpga-mgr.c
 ++++ b/drivers/fpga/fpga-mgr.c
 +@@ -8,6 +8,9 @@
@ -673,7 +673,7 @@ index 0000000..33daffe
 + 	NULL,
 + };
 + ATTRIBUTE_GROUPS(fpga_mgr);
-+@@ -739,6 +871,106 @@ void fpga_mgr_put(struct fpga_manager *mgr)
+@@ -732,6 +864,106 @@ void fpga_mgr_put(struct fpga_manager *mgr)
 + }
 + EXPORT_SYMBOL_GPL(fpga_mgr_put);
 + 
@ -780,8 +780,8 @@ index 0000000..33daffe
 + /**
 +  * fpga_mgr_lock - Lock FPGA manager for exclusive use
 +  * @mgr:	fpga manager
-+@@ -788,6 +1020,9 @@ __fpga_mgr_register_full(struct device *parent, const struct fpga_manager_info *
+@@ -779,6 +1011,9 @@ struct fpga_manager *
-+ 			 struct module *owner)
+ fpga_mgr_register_full(struct device *parent, const struct fpga_manager_info *info)
 + {
 + 	const struct fpga_manager_ops *mops = info->mops;
 ++#ifdef CONFIG_FPGA_MGR_DEBUG_FS
@ -790,7 +790,7 @@ index 0000000..33daffe
 + 	struct fpga_manager *mgr;
 + 	int id, ret;
 + 
-+@@ -826,10 +1061,28 @@ __fpga_mgr_register_full(struct device *parent, const struct fpga_manager_info *
+@@ -815,10 +1050,28 @@ fpga_mgr_register_full(struct device *parent, const struct fpga_manager_info *in
 + 	mgr->dev.of_node = parent->of_node;
 + 	mgr->dev.id = id;
 + 
@ -819,7 +819,7 @@ index 0000000..33daffe
 + 	/*
 + 	 * Initialize framework state by requesting low level driver read state
 + 	 * from device.  FPGA may be in reset mode or may have been programmed
-+@@ -843,6 +1096,28 @@ __fpga_mgr_register_full(struct device *parent, const struct fpga_manager_info *
+@@ -832,6 +1085,28 @@ fpga_mgr_register_full(struct device *parent, const struct fpga_manager_info *in
 + 		return ERR_PTR(ret);
 + 	}
 + 
@ -848,7 +848,7 @@ index 0000000..33daffe
 + 	return mgr;
 + 
 + error_device:
-+@@ -894,6 +1169,10 @@ void fpga_mgr_unregister(struct fpga_manager *mgr)
+@@ -882,6 +1157,10 @@ void fpga_mgr_unregister(struct fpga_manager *mgr)
 + {
 + 	dev_info(&mgr->dev, "%s %s\n", __func__, mgr->name);
 + 
@ -881,10 +881,10 @@ index 0000000..33daffe
 + 				     &firmware_name)) {
 + 		info->firmware_name = devm_kstrdup(dev, firmware_name,
 +diff --git a/drivers/fpga/zynqmp-fpga.c b/drivers/fpga/zynqmp-fpga.c
-+index f3434e2c487b..d2434ed85eff 100644
+index f3434e2c487b..db923746cac5 100644
 +--- a/drivers/fpga/zynqmp-fpga.c
 ++++ b/drivers/fpga/zynqmp-fpga.c
-+@@ -43,25 +43,47 @@ static int zynqmp_fpga_ops_write(struct fpga_manager *mgr,
+@@ -43,25 +43,42 @@ static int zynqmp_fpga_ops_write(struct fpga_manager *mgr,
 + 	struct zynqmp_fpga_priv *priv;
 + 	dma_addr_t dma_addr;
 + 	u32 eemi_flags = 0;
@ -915,11 +915,6 @@ index 0000000..33daffe
 ++
 + 	wmb(); /* ensure all writes are done before initiate FW call */
 + 
 ++	if (priv->flags & FPGA_MGR_DDR_MEM_AUTH_BITSTREAM)
 ++		eemi_flags |= XILINX_ZYNQMP_PM_FPGA_AUTHENTICATION_DDR;
 ++	else if (priv->flags & FPGA_MGR_SECURE_MEM_AUTH_BITSTREAM)
 ++		eemi_flags |= XILINX_ZYNQMP_PM_FPGA_AUTHENTICATION_OCM;
 ++
 + 	if (priv->flags & FPGA_MGR_PARTIAL_RECONFIG)
 + 		eemi_flags |= XILINX_ZYNQMP_PM_FPGA_PARTIAL;
 + 
@ -936,22 +931,20 @@ index 0000000..33daffe
 + 	return ret;
 + }
 +diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
-+index e8b12ec8b060..ffd2dfdb6abd 100644
+index 9dda7d9898ff..edaf77160746 100644
 +--- a/include/linux/firmware/xlnx-zynqmp.h
 ++++ b/include/linux/firmware/xlnx-zynqmp.h
-+@@ -83,6 +83,10 @@
+@@ -70,6 +70,8 @@
 +  */
 + #define XILINX_ZYNQMP_PM_FPGA_FULL	0x0U
 + #define XILINX_ZYNQMP_PM_FPGA_PARTIAL	BIT(0)
 ++#define XILINX_ZYNQMP_PM_FPGA_AUTHENTICATION_DDR	BIT(1)
 ++#define XILINX_ZYNQMP_PM_FPGA_AUTHENTICATION_OCM	BIT(2)
 ++#define XILINX_ZYNQMP_PM_FPGA_ENCRYPTION_USERKEY	BIT(3)
 ++#define XILINX_ZYNQMP_PM_FPGA_ENCRYPTION_DEVKEY		BIT(4)
 + 
 + /* FPGA Status Reg */
 + #define XILINX_ZYNQMP_PM_FPGA_CONFIG_STAT_OFFSET	7U
 +diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h
-+index 0d4fe068f3d8..f884d268c974 100644
+index 54f63459efd6..c96a4405f909 100644
 +--- a/include/linux/fpga/fpga-mgr.h
 ++++ b/include/linux/fpga/fpga-mgr.h
 +@@ -9,8 +9,11 @@
@ -966,7 +959,7 @@ index 0000000..33daffe
 + struct fpga_manager;
 + struct sg_table;
 + 
-+@@ -66,17 +69,29 @@ enum fpga_mgr_states {
+@@ -66,17 +69,25 @@ enum fpga_mgr_states {
 +  *
 +  * %FPGA_MGR_EXTERNAL_CONFIG: FPGA has been configured prior to Linux booting
 +  *
@ -980,10 +973,6 @@ index 0000000..33daffe
 ++ *
 ++ * %FPGA_MGR_USERKEY_ENCRYPTED_BITSTREAM: indicates bitstream is encrypted with
 ++ *					  user key
 ++ * %FPGA_MGR_DDR_MEM_AUTH_BITSTREAM: do bitstream authentication using DDR
 ++ *				     memory if supported
 ++ * %FPGA_MGR_SECURE_MEM_AUTH_BITSTREAM: do bitstream authentication using secure
 ++ *					memory if supported
 +  */
 + #define FPGA_MGR_PARTIAL_RECONFIG	BIT(0)
 + #define FPGA_MGR_EXTERNAL_CONFIG	BIT(1)
@ -997,7 +986,7 @@ index 0000000..33daffe
 + 
 + /**
 +  * struct fpga_image_info - information specific to an FPGA image
-+@@ -86,6 +101,7 @@ enum fpga_mgr_states {
+@@ -86,6 +97,7 @@ enum fpga_mgr_states {
 +  * @config_complete_timeout_us: maximum time for FPGA to switch to operating
 +  *	   status in the write_complete op.
 +  * @firmware_name: name of FPGA image firmware file
@ -1005,7 +994,7 @@ index 0000000..33daffe
 +  * @sgt: scatter/gather table containing FPGA image
 +  * @buf: contiguous buffer containing FPGA image
 +  * @count: size of buf
-+@@ -102,6 +118,7 @@ struct fpga_image_info {
+@@ -102,6 +114,7 @@ struct fpga_image_info {
 + 	u32 disable_timeout_us;
 + 	u32 config_complete_timeout_us;
 + 	char *firmware_name;
@ -1013,7 +1002,7 @@ index 0000000..33daffe
 + 	struct sg_table *sgt;
 + 	const char *buf;
 + 	size_t count;
-+@@ -160,6 +177,7 @@ struct fpga_manager_info {
+@@ -160,6 +173,7 @@ struct fpga_manager_info {
 +  * @write: write count bytes of configuration data to the FPGA
 +  * @write_sg: write the scatter list of configuration data to the FPGA
 +  * @write_complete: set FPGA to operating state after writing is done
@ -1021,7 +1010,7 @@ index 0000000..33daffe
 +  * @fpga_remove: optional: Set FPGA into a specific state during driver remove
 +  * @groups: optional attribute groups.
 +  *
-+@@ -182,6 +200,7 @@ struct fpga_manager_ops {
+@@ -182,6 +196,7 @@ struct fpga_manager_ops {
 + 	int (*write_sg)(struct fpga_manager *mgr, struct sg_table *sgt);
 + 	int (*write_complete)(struct fpga_manager *mgr,
 + 			      struct fpga_image_info *info);
@ -1029,7 +1018,7 @@ index 0000000..33daffe
 + 	void (*fpga_remove)(struct fpga_manager *mgr);
 + 	const struct attribute_group **groups;
 + };
-+@@ -196,23 +215,37 @@ struct fpga_manager_ops {
+@@ -196,21 +211,35 @@ struct fpga_manager_ops {
 + /**
 +  * struct fpga_manager - fpga manager structure
 +  * @name: name of low level fpga manager
@ -1042,7 +1031,6 @@ index 0000000..33daffe
 +  * @state: state of fpga manager
 +  * @compat_id: FPGA manager id for compatibility check.
 +  * @mops: pointer to struct of fpga manager ops
 +  * @mops_owner: module containing the mops
 +  * @priv: low level driver private date
 ++ * @err: low level driver error code
 ++ * @dir: debugfs image directory
@ -1058,7 +1046,6 @@ index 0000000..33daffe
 + 	enum fpga_mgr_states state;
 + 	struct fpga_compat_id *compat_id;
 + 	const struct fpga_manager_ops *mops;
 + 	struct module *mops_owner;
 + 	void *priv;
 ++	int err;
 ++#ifdef CONFIG_FPGA_MGR_DEBUG_FS
@ -1067,21 +1054,21 @@ index 0000000..33daffe
 + };
 + 
 + #define to_fpga_manager(d) container_of(d, struct fpga_manager, dev)
-+@@ -258,4 +291,6 @@ __devm_fpga_mgr_register(struct device *parent, const char *name,
+@@ -244,4 +273,6 @@ struct fpga_manager *
-+ 			 const struct fpga_manager_ops *mops, void *priv,
+ devm_fpga_mgr_register(struct device *parent, const char *name,
-+ 			 struct module *owner);
+ 		       const struct fpga_manager_ops *mops, void *priv);
 + 
 ++#define FPGA_IOCTL_LOAD_DMA_BUFF	_IOWR('R', 1, __u32)
 ++
 + #endif /*_LINUX_FPGA_MGR_H */
 diff --git a/zynq_image.nix b/zynq_image.nix
-index d5c5eda..7ede584 100644
+index 9d1621e..012e50c 100644
 --- a/zynq_image.nix
 +++ b/zynq_image.nix
@@ -3,6 +3,16 @@
 with lib;
 let
-   customKernel = (pkgs.linux_6_6.override {
+   customKernel = (pkgs.linux.override {
 +    kernelPatches = [
 +      ({
 +        name = "xilinx-configfs-overlays";
--- a/not-os-patches/pr-34.patch
+++ b/not-os-patches/pr-34.patch
@ -1,20 +0,0 @@
 diff --git a/zynq_image.nix b/zynq_image.nix
 index 069fe89..979b760 100644
 --- a/zynq_image.nix
 +++ b/zynq_image.nix
@@ -51,6 +51,15 @@ in {
         hostname ${config.networking.hostName}
         exec setsid agetty ttyPS0 115200
       '';
 +      "service/linien-server/run".source = pkgs.writeShellScript "linien-server" ''
 +        exec 2>&1
 +        exec setsid linien-server run
 +      '';
 +      "service/linien-server/log/run".source = pkgs.writeShellScript "linien-server-logger" ''
 +        exec 2>&1
 +        mkdir -p /root/linien-server-log
 +        exec svlogd -tt /root/linien-server-log
 +      '';
       "pam.d/other".text = ''
         auth     sufficient pam_permit.so
         account  required pam_permit.so
--- a/not-os-patches/user_defined_ip_settings.patch
+++ b/not-os-patches/user_defined_ip_settings.patch
@ -1,42 +0,0 @@
 diff --git a/runit.nix b/runit.nix
 index 14dd437..982823d 100644
 --- a/runit.nix
 +++ b/runit.nix
@@ -36,6 +36,10 @@ in
         ip route add 103.206.98.200/29 dev eth0
         ip route add default via 103.206.98.200 dev eth0
         ''}
 +
 +        # Setup IP Address
 +        /etc/ip_setup
 +
         mkdir /bin/
         ln -s ${pkgs.runtimeShell} /bin/sh
 diff --git a/zynq_image.nix b/zynq_image.nix
 index 979b760..0be26b2 100644
 --- a/zynq_image.nix
 +++ b/zynq_image.nix
@@ -33,7 +33,7 @@ in {
   nixpkgs.system = "armv7l-linux";
   networking.hostName = "zynq";
   not-os.sd = true;
 -  not-os.simpleStaticIp = true;
 +  not-os.simpleStaticIp = false;
   system.build.zynq_image = pkgs.runCommand "zynq_image" {
     preferLocalBuild = true;
   } ''
@@ -60,6 +60,13 @@ in {
         mkdir -p /root/linien-server-log
         exec svlogd -tt /root/linien-server-log
       '';
 +      "ip_setup" = {
 +        text = ''
 +          ifconfig eth0 192.168.1.129 netmask 255.255.255.0
 +          ip link set eth0 up
 +        '';
 +        mode = "0762";
 +      };
       "pam.d/other".text = ''
         auth     sufficient pam_permit.so
         account  required pam_permit.so
Author	SHA1	Message	Date
Florian Agbuya	43aada8ec3	pyfastservo: update initialize script	2024-07-10 15:45:51 +08:00
Florian Agbuya	acf58c9224	pyfastservo: fix adc init script and cleanup	2024-07-10 15:45:51 +08:00
Florian Agbuya	8506da0128	pyfastservo: fix dac init script and cleanup	2024-07-10 15:45:45 +08:00
Florian Agbuya	61fa18fb18	pyfastservo: transfer common functions to common	2024-07-10 14:23:52 +08:00