pyfastservo adc: Add helper fn for phase shifting the dac ddr clock

- Fix: if frame changed at 31 tap delay, edge would not get detected

fast-servo/linien-gateware/cores/adc.py

@@ -22,11 +22,12 @@ from migen.genlib.cdc import MultiReg
 from misoc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage
 
 
-class _CRG(Module):
+class CRG(Module):
     def __init__(self, platform, dco_clk, dco_freq=200e6):
         self.clock_domains.cd_dco = ClockDomain()
         self.clock_domains.cd_dco2x = ClockDomain()
         self.clock_domains.cd_dco2d = ClockDomain()
+        self.clock_domains.cd_dco2d_45_degree = ClockDomain()
         dco_clk_p, dco_clk_n = dco_clk
 
         dco_clk_buf = Signal()
@@ -41,59 +42,83 @@ class _CRG(Module):
         clk_dco = Signal()
         clk_dco2x = Signal()
         clk_dco2d = Signal()
+        clk_dco2d_45_degree = Signal()
+        mmcm_ps_psdone = Signal()
+
         self.locked = Signal()
+        self.mmcm_rst = Signal()
+        self.ddr_clk_phase_shift_en = Signal()
+        self.ddr_clk_phase_incdec = Signal()
 
         platform.add_period_constraint(dco_clk_p, 1e9 / dco_freq)
         self.specials += [
             Instance(
-                "PLLE2_BASE",
+                "MMCME2_ADV",
                 p_BANDWIDTH="OPTIMIZED",
                 p_DIVCLK_DIVIDE=1,
                 p_CLKFBOUT_PHASE=0.0,
-                p_CLKFBOUT_MULT=4,  # VCO @ 800 MHz
+                p_CLKFBOUT_MULT_F=4,  # VCO @ 800 MHz
                 p_CLKIN1_PERIOD=(1e9 / dco_freq),
                 p_REF_JITTER1=0.01,
                 p_STARTUP_WAIT="FALSE",
                 i_CLKIN1=dco_clk_buf,
                 i_PWRDWN=0,
-                i_RST=ResetSignal("sys"),
+                i_RST=ResetSignal("sys") | self.mmcm_rst,
                 i_CLKFBIN=clk_feedback_buf,
                 o_CLKFBOUT=clk_feedback,
-                p_CLKOUT0_DIVIDE=4,
-                p_CLKOUT0_PHASE=0.0,
+
+                p_CLKOUT0_USE_FINE_PS="TRUE",
+                p_CLKOUT0_DIVIDE_F=8,
+                p_CLKOUT0_PHASE=45.0,
                 p_CLKOUT0_DUTY_CYCLE=0.5,
-                o_CLKOUT0=clk_dco,  # 200 MHz <- dco_clk
+                o_CLKOUT0=clk_dco2d_45_degree,  # 100 MHz <- dco_clk / 2 = 200 MHz / 2
+                o_LOCKED=self.locked,
+
                 p_CLKOUT1_DIVIDE=2,
                 p_CLKOUT1_PHASE=0.0,
                 p_CLKOUT1_DUTY_CYCLE=0.5,
                 o_CLKOUT1=clk_dco2x,  # 400 MHZ <- 2 * dco_clk = 2*200 MHz
+                
                 p_CLKOUT2_DIVIDE=8,
                 p_CLKOUT2_PHASE=0.0,
                 p_CLKOUT2_DUTY_CYCLE=0.5,
                 o_CLKOUT2=clk_dco2d,  # 100 MHz <- dco_clk / 2 = 200 MHz / 2
-                o_LOCKED=self.locked,
+                
+                p_CLKOUT3_DIVIDE=4,
+                p_CLKOUT3_PHASE=0.0,
+                p_CLKOUT3_DUTY_CYCLE=0.5,
+                o_CLKOUT3=clk_dco,  # 200 MHz <- dco_clk
+
+                i_PSCLK=ClockSignal(),
+                i_PSEN=self.ddr_clk_phase_shift_en,
+                i_PSINCDEC=self.ddr_clk_phase_incdec,
+                o_PSDONE=mmcm_ps_psdone,
             )
         ]
 
         self.specials += Instance("BUFG", i_I=clk_feedback, o_O=clk_feedback_buf)
         self.specials += Instance("BUFG", i_I=clk_dco, o_O=self.cd_dco.clk)
         self.specials += Instance("BUFG", i_I=clk_dco2d, o_O=self.cd_dco2d.clk)
+        self.specials += Instance("BUFG", i_I=clk_dco2d_45_degree, o_O=self.cd_dco2d_45_degree.clk)
         self.specials += Instance("BUFG", i_I=clk_dco2x, o_O=self.cd_dco2x.clk)
 
+        # Ignore dco2d to mmcm dco_clk path created by SoC's rst.
+        platform.add_false_path_constraints(self.cd_dco2d.clk, dco_clk_buf)
+        self.specials += Instance("FD", p_INIT=1, i_D=~self.locked, i_C=self.cd_dco2d.clk, o_Q=self.cd_dco2d.rst)
 
 class ADC(Module, AutoCSR):
     def __init__(self, platform, dco_freq=200e6):
         adc_pads = platform.request("adc")
         afe_pads = platform.request("adc_afe")
 
-        self.frame_csr = CSRStatus(4)
+        self.frame_csr = CSRStatus(5)
         self.data_ch0 = CSRStatus(16)
         self.data_ch1 = CSRStatus(16)
 
         self.tap_delay = CSRStorage(5)
         self.bitslip_csr = CSRStorage(1)
 
-        self.afe_ctrl = CSRStorage(4)
+        self.afe_ctrl = CSRStorage(7)
 
         tap_delay_val = Signal(5)
         bitslip = Signal()
@@ -117,11 +142,14 @@ class ADC(Module, AutoCSR):
             # dco_clk.n.eq(adc_pads.dco_n),
             tap_delay_val.eq(self.tap_delay.storage),
             Cat(ch1_gain_x10, ch2_gain_x10, ch1_shdn, ch2_shdn).eq(
-                self.afe_ctrl.storage
+                self.afe_ctrl.storage[0:4]
             ),
         ]
 
-        self.submodules._crg = _CRG(platform, dco_clk, dco_freq)
+        self.submodules.crg = CRG(platform, dco_clk, dco_freq)
+        self.comb += self.afe_ctrl.storage[4].eq(self.crg.mmcm_rst)
+        self.comb += self.afe_ctrl.storage[5].eq(self.crg.ddr_clk_phase_shift_en)
+        self.comb += self.afe_ctrl.storage[6].eq(self.crg.ddr_clk_phase_incdec)
 
         self.specials += MultiReg(self.bitslip_csr.re, bitslip_re_dco_2d, "dco2d")
         self.sync.dco2d += [
@@ -129,7 +157,8 @@ class ADC(Module, AutoCSR):
         ]
 
         self.comb += [
-            self.frame_csr.status.eq(self.s_frame),
+            self.frame_csr.status[0:4].eq(self.s_frame[0:4]),
+            self.frame_csr.status[4].eq(self.crg.locked),
             self.data_ch0.status.eq(self.data_out[0]),
             self.data_ch1.status.eq(self.data_out[1]),
         ]
@@ -146,7 +175,7 @@ class ADC(Module, AutoCSR):
 
         self.specials += Instance(
             "LTC2195",
-            i_rst_in=ResetSignal("sys"),
+            i_rst_in=ResetSignal("dco2d"),
             i_clk200=ClockSignal("idelay"),
             i_DCO=ClockSignal("dco"),
             i_DCO_2D=ClockSignal("dco2d"),

fast-servo/linien-gateware/cores/dac.py

@@ -42,7 +42,7 @@ class DAC(Module, AutoCSR):
 
         self.comb += [
             Cat(manual_override, ch0_pd, ch1_pd).eq(self.dac_ctrl.storage),
-            dac_pads.rst.eq(ResetSignal("sys")),
+            dac_pads.rst.eq(ResetSignal("dco2d")),
             dac_afe_pads.ch1_pd_n.eq(~ch0_pd),
             dac_afe_pads.ch2_pd_n.eq(~ch1_pd),
             output_data_ch0.eq(
@@ -53,22 +53,22 @@ class DAC(Module, AutoCSR):
             ),
         ]
 
-        # data
-        for lane in range(14):
-            self.specials += DDROutput(
-                i1 = output_data_ch0[lane], 
-                i2 = output_data_ch1[lane], 
-                o = dac_pads.data[lane], 
-                clk = ClockSignal("dco2d")
-            )
-        
-        # clock forwarding
-        self.specials += DDROutput(
-            i1 = 0b0,
-            i2 = 0b1,
-            o = dac_pads.dclkio,
-            clk = ClockSignal("dco2d"),
-        )
+        self.specials += [
+            Instance("ODDR", 
+                i_C=ClockSignal("dco2d"), 
+                i_CE=~ResetSignal("dco2d"), 
+                i_D1=output_data_ch0[lane], # DDR CLK Rising Edge
+                i_D2=output_data_ch1[lane], # DDR CLK Falling Edge
+                o_Q=dac_pads.data[lane],
+                p_DDR_CLK_EDGE="SAME_EDGE") 
+            for lane in range(14)]
+        self.specials += Instance("ODDR", 
+                i_C=ClockSignal("dco2d_45_degree"), 
+                i_CE=~ResetSignal("dco2d"), 
+                i_D1=0, 
+                i_D2=1, 
+                o_Q=dac_pads.dclkio,
+                p_DDR_CLK_EDGE="SAME_EDGE")
 
 
 class AUX_DAC_CTRL(Module, AutoCSR):

fast-servo/pyfastservo/adc.py

@@ -17,7 +17,7 @@
 # You should have received a copy of the GNU General Public License
 # along with this program. If not, see <https://www.gnu.org/licenses/>.
 
-
+import time
 import spidev
 from pyfastservo.common import (
     ADC_AFE_CTRL_ADDR,
@@ -78,30 +78,47 @@ def read_frame():
 def perform_bitslip():
     for i in range(4):
         current_frame = read_frame()
-        if current_frame != 0x0C:
+        if current_frame & 0x0F != 0x0C:
             print(f"Performing bitslip (iteration: {i}). Current frame: 0x{current_frame:02x}")
             write_to_memory(ADC_BITSLIP_ADDR, 1)
         else:
             print(f"No bitslip required; Current frame: 0x{current_frame:02x}")
             return
 
+def mmcm_rst():
+    curr_cfg = read_from_memory(ADC_AFE_CTRL_ADDR, 1)[0] & 0x0F
+    write_to_memory(ADC_AFE_CTRL_ADDR, 0x10 | curr_cfg) # Reset MMCM
+    write_to_memory(ADC_AFE_CTRL_ADDR, 0x00 | curr_cfg) # Release MMCM Reset
+    while not(read_frame() & 0x10):
+        print(f"Waiting for MMCM to lock")
+        time.sleep(0.001)
+
+def inc_ddr_clk_phase():
+    curr_cfg = read_from_memory(ADC_AFE_CTRL_ADDR, 1)[0] & 0x1F
+    write_to_memory(ADC_AFE_CTRL_ADDR, 0x40 | curr_cfg) # Set MMCM Phase Shift to be INC
+    write_to_memory(ADC_AFE_CTRL_ADDR, 0x60 | curr_cfg) # Assert MMCM Phase Shift EN High
+    write_to_memory(ADC_AFE_CTRL_ADDR, curr_cfg)        # Deassert MMCM Phase Shift EN High
+
+def dec_ddr_clk_phase():
+    curr_cfg = read_from_memory(ADC_AFE_CTRL_ADDR, 1)[0] & 0x1F
+    write_to_memory(ADC_AFE_CTRL_ADDR, 0x00 | curr_cfg) # Set MMCM Phase Shift to be DEC
+    write_to_memory(ADC_AFE_CTRL_ADDR, 0x20 | curr_cfg) # Assert MMCM Phase Shift EN High
+    write_to_memory(ADC_AFE_CTRL_ADDR, curr_cfg)        # Deassert MMCM Phase Shift EN High
+
 def find_edge():
     prev_frame = read_frame()
-    transition = False
     for tap_delay in range(32):
         write_to_memory(ADC_DELAY_ADDR, tap_delay)
         current_frame = read_frame()
 
         print(f"Tap delay: {tap_delay}, Current frame: 0x{current_frame:02x}")
+        print(f"prev_frame: 0x{prev_frame:02x}")
 
         if current_frame != prev_frame:
-            if not transition:
-                transition = True
-            else:
-                final_delay = (tap_delay // 2) + 2
-                print(f"Edge detected; setting iDelay to: {final_delay}")
-                write_to_memory(ADC_DELAY_ADDR, final_delay)
-                return
+            final_delay = ((tap_delay+1) // 2) + 2
+            print(f"Edge detected; setting iDelay to: {final_delay}")
+            write_to_memory(ADC_DELAY_ADDR, final_delay)
+            return
 
         prev_frame = current_frame
 
@@ -126,6 +143,36 @@ def enable_adc_afe(ch1_x10=False, ch2_x10=False):
     print(f"ADC_AFE_CTRL: 0x{afe_ctrl:02X}")
     return afe_ctrl
 
+def search_edge():
+    for tap_delay in range(32):
+        print(f"iDelay to: {tap_delay}")
+        write_to_memory(ADC_DELAY_ADDR, tap_delay)
+        time.sleep(1)
+        current_frame = read_frame()
+        print(f"Tap delay: {tap_delay}, Current frame: 0x{current_frame:02x}")
+        print_adc_channels()
+
+def print_adc_channel(ch):
+    if ch == 0:
+        adc_ch0 = read_adc_channel(ADC_CH0_HIGH_ADDR, ADC_CH0_LOW_ADDR)
+        print(f"Final ADC_CH0: 0x{adc_ch0:04x}")
+    if ch == 1:
+        adc_ch1 = read_adc_channel(ADC_CH1_HIGH_ADDR, ADC_CH1_LOW_ADDR)
+        print(f"Final ADC_CH1: 0x{adc_ch1:04x}")
+
+def find_min_max_ch(ch):
+    test = []
+    for i in range(100):
+        if ch == 0:
+            test.append(read_adc_channel(ADC_CH0_HIGH_ADDR, ADC_CH0_LOW_ADDR))
+        else:
+            test.append(read_adc_channel(ADC_CH1_HIGH_ADDR, ADC_CH1_LOW_ADDR)) 
+        print("ch", ch, hex(test[-1]))
+    print("Min:", hex(min(test)))
+    print("Max:", hex(max(test)))
+    print("Diff:", hex(max(test)-min(test)))
+
+
 def configure_ltc2195():
     spi = spidev.SpiDev()
     try:
@@ -144,15 +191,31 @@ def configure_ltc2195():
             0x04: test_pattern & 0xFF
         })
 
+        # ADC software reset put its PLL to sleep momentarily. Thus, MMCM needs to be reset as well.
+        mmcm_rst()
+        
         # Performing Word Align
         perform_bitslip()
         find_edge()
-        print_adc_channels()
+        
+        # Printing it once is not enough to check whether the alignment is correct.
+        for i in range(100):
+            print_adc_channels()
 
         main_adc_test_mode(spi, False)
         verify_adc_registers(spi, {0x02: 0x11})  # Verify test mode is off
       
-        enable_adc_afe()
+        # FIXME: AFE Gain 1x is not functional on that batch of fast servo under development
+        enable_adc_afe(ch1_x10=1, ch2_x10=1)
+
+        #find_min_max_ch(0)
+        #find_min_max_ch(1)
+
+        #for i in range(10):
+        #    print_adc_channel(0)
+
+        #for i in range(10):
+        #    print_adc_channel(1)
 
     finally:
         spi.close()

fast-servo/pyfastservo/dac.py

@@ -45,7 +45,7 @@ def spi_read(spi, address):
     rx_buffer = spi.xfer2([0x80 | address, 0x00])
     return rx_buffer[1]
 
-def hard_reset(spi):
+def soft_reset(spi):
     spi_write(spi, 0x00, 0x10)  # Software reset
     spi_write(spi, 0x00, 0x00)  # Release software reset
     spi_read(spi, 0x00)         # Read reset address (necessary for reset to take effect)
@@ -63,7 +63,10 @@ def configure_dac(spi):
     spi_write(spi, 0x07, 0xA0)      # Enable on-chip QRSET (1.6 kΩ for 20mA output)
     spi_write(spi, 0x05, 0x00)      # Disable internal IRCML
     spi_write(spi, 0x08, 0x00)      # Disable internal QRCML
-    spi_write(spi, 0x02, 0xB4)      # Enable 2's complement, LVDS interface, 4 LVDS lanes
+    spi_write(spi, 0x02, 0xB4)      # Enable 2's complement, IFirst: True, IRising: True, DCI_EN: Enabled
+    spi_write(spi, 0x14, 0x00)      
+    spi_write(spi, 0x14, 0x08)      # Trigger the retimer to reacquire the clock relationship
+    spi_write(spi, 0x14, 0x00)
 
 def dac_self_calibration(spi):
     spi_write(spi, 0x12, 0x00)      # Reset calibration status
@@ -83,11 +86,11 @@ def dac_self_calibration(spi):
 
 def manual_override(enable=True):
     reg_contents = read_from_memory(CTRL_ADDR, 1)[0]
-    print(f"REG contents: 0b{reg_contents:03b}")
     to_write = reg_contents | 0b1 if enable else reg_contents & 0b110
     write_to_memory(CTRL_ADDR, to_write)
+    print(f"Set DAC Output Manual Override: {enable}")
 
-def power_down(channel, power_down=True):
+def power_down_afe(channel, power_down=True):
     assert channel in (0, 1)
 
     bitmask = 1 << (channel + 1) & 0b111
@@ -98,7 +101,7 @@ def power_down(channel, power_down=True):
     to_write = reg_contents | value
     write_to_memory(CTRL_ADDR, to_write)
     reg_contents = read_from_memory(CTRL_ADDR, 1)[0]
-    print(f"REG contents: 0b{reg_contents:03b}")
+    print(f"Power Down DAC AFE Ch{channel}: {power_down}")
 
 def set_dac_output(value):
     value = min(value, 0x3FFF)
@@ -111,6 +114,16 @@ def set_dac_output(value):
     write_to_memory(CH1_LOW_WORD_ADDR, low_word)
     print(f"DAC output set to: 0x{value:04X}")
 
+def check_clk_relationship(spi):
+    clkmode_reg = spi_read(spi, 0x14)
+    print(f"CLKMODE reg: 0x{clkmode_reg:02X}")
+    if clkmode_reg & 0b00010000:
+        print("Clock relationship is not found")
+        return False
+    else:
+        print("Clock relationship is found")
+        return True
+
 def configure_ad9117():
     spi = spidev.SpiDev()
     spi.open(MAIN_DAC_BUS, MAIN_DAC_DEVICE)
@@ -119,20 +132,24 @@ def configure_ad9117():
     spi.cshigh = False
 
     try:
-        hard_reset(spi)
+        soft_reset(spi)
         if not check_version(spi):
             print("Unrecognized DAC version")
             return False
 
+        power_down_afe(0, True)
+        power_down_afe(1, True)
+
         configure_dac(spi)
+        check_clk_relationship(spi)
         dac_self_calibration(spi)
 
         # Enable DAC outputs
         spi_write(spi, 0x01, spi_read(spi, 0x01) & ~((1 << 4) | (1 << 3)))
 
-        power_down(0, False)
-        power_down(1, False)
-        manual_override(True)
+        power_down_afe(0, False)
+        power_down_afe(1, False)
+        manual_override(False)
 
         print("AD9117 configuration completed successfully")
         return True