6 Commits

Author	SHA1	Message	Date
linuswck	a5dc232be4	gateware: add cdc fifo for dac output value override csr	2024-11-15 15:42:25 +08:00
linuswck	87059eef2b	gateware: async fifo with depth of 2 is broken ... - Changing depth to 4 has resolved cdc issue	2024-11-15 15:42:25 +08:00
linuswck	8a40bb4f21	gateware: Add cdc fifo for adc and dac ... - dco2d and sys clk use two different clock sources	2024-11-13 15:43:35 +08:00
linuswck	6cef418756	gateware: Add CSR Ctrl to PL's MMCM ... - Generate 45 Degree Phase Shifted DDR Clock - PLLE2_Base -> MMCM_ADV for ddr clock dynamic phase shift - Add mmcm_rst, ddr_clk_ps, mmcm_locked status to CSR - Generate dco2d rst signal from mmcm and connect to the related logic	2024-11-08 16:33:17 +08:00
Florian Agbuya	1244c84f67	fix typo	2024-03-06 17:53:13 +08:00
Florian Agbuya	cd9590503c	add fast-servo gateware support files	2024-03-01 16:39:56 +08:00