M-Labs/nix-servo
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gateware: sys freq 100MHz -> 125MHz

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This commit is contained in:
linuswck 2025-01-10 12:40:05 +08:00
parent 0ca6ac1354
commit fd125a506f
3 changed files with 18 additions and 18 deletions
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2
fast-servo/linien-gateware/fast_servo_platform.py
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@ -318,7 +318,7 @@ ps7_config_board_preset = {
class Platform(XilinxPlatform): class Platform(XilinxPlatform):
default_clk_name = "adc_dco_clk_p" default_clk_name = "adc_dco_clk_p"
default_clk_period = 5.0 default_clk_period = 4.0
def __init__(self): def __init__(self):
XilinxPlatform.__init__(self, "xc7z015-clg485-1", _io, _connector_gpio + _connector_eem, toolchain="vivado") XilinxPlatform.__init__(self, "xc7z015-clg485-1", _io, _connector_gpio + _connector_eem, toolchain="vivado")

14
fast-servo/linien-gateware/fast_servo_soc.py
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@ -31,7 +31,7 @@ from fast_servo.gateware.cores.spi_phy import SpiInterface, SpiPhy
class CRG(Module): class CRG(Module):
def __init__(self, platform, dco_freq=200e6): def __init__(self, platform, dco_freq=250e6):
self.ps_rst = Signal() self.ps_rst = Signal()
self.locked = Signal() self.locked = Signal()
@ -69,7 +69,7 @@ class CRG(Module):
p_BANDWIDTH="OPTIMIZED", p_BANDWIDTH="OPTIMIZED",
p_DIVCLK_DIVIDE=1, p_DIVCLK_DIVIDE=1,
p_CLKFBOUT_PHASE=0.0, p_CLKFBOUT_PHASE=0.0,
p_CLKFBOUT_MULT_F=4, # VCO @ 800 MHz p_CLKFBOUT_MULT_F=4, # VCO @ 1000 MHz
p_CLKIN1_PERIOD=(1e9 / dco_freq), p_CLKIN1_PERIOD=(1e9 / dco_freq),
p_REF_JITTER1=0.06, # From LTC2195 Datasheet p_REF_JITTER1=0.06, # From LTC2195 Datasheet
p_STARTUP_WAIT="FALSE", p_STARTUP_WAIT="FALSE",
@ -83,23 +83,23 @@ class CRG(Module):
p_CLKOUT0_DIVIDE_F=8, p_CLKOUT0_DIVIDE_F=8,
p_CLKOUT0_PHASE=45.0, p_CLKOUT0_PHASE=45.0,
p_CLKOUT0_DUTY_CYCLE=0.5, p_CLKOUT0_DUTY_CYCLE=0.5,
o_CLKOUT0=clk_sys_45_degree, # 800MHz / 8 -> 100MHz o_CLKOUT0=clk_sys_45_degree, # 1000MHz / 8 -> 125MHz
o_LOCKED=self.locked, o_LOCKED=self.locked,
p_CLKOUT1_DIVIDE=8, p_CLKOUT1_DIVIDE=8,
p_CLKOUT1_PHASE=0.0, p_CLKOUT1_PHASE=0.0,
p_CLKOUT1_DUTY_CYCLE=0.5, p_CLKOUT1_DUTY_CYCLE=0.5,
o_CLKOUT1=clk_sys, # 800MHz / 8 -> 100MHz o_CLKOUT1=clk_sys, # 1000MHz / 8 -> 120MHz
p_CLKOUT2_DIVIDE=4, p_CLKOUT2_DIVIDE=4,
p_CLKOUT2_PHASE=0.0, p_CLKOUT2_PHASE=0.0,
p_CLKOUT2_DUTY_CYCLE=0.5, p_CLKOUT2_DUTY_CYCLE=0.5,
o_CLKOUT2=clk_sys_double, # 800MHz / 4 -> 200MHz o_CLKOUT2=clk_sys_double, # 1000MHz / 4 -> 250MHz
p_CLKOUT3_DIVIDE=4, p_CLKOUT3_DIVIDE=5,
p_CLKOUT3_PHASE=0.0, p_CLKOUT3_PHASE=0.0,
p_CLKOUT3_DUTY_CYCLE=0.5, p_CLKOUT3_DUTY_CYCLE=0.5,
o_CLKOUT3=clk_idelay, # 800MHz / 4 -> 200MHz o_CLKOUT3=clk_idelay, # 1000MHz / 5 -> 200MHz
i_PSCLK=ClockSignal(), i_PSCLK=ClockSignal(),
i_PSEN=self.ddr_clk_phase_shift_en, i_PSEN=self.ddr_clk_phase_shift_en,

20
fast-servo/pyfastservo/si5340.py
View File

@ -143,8 +143,8 @@ def configure_si5340():
(0x0235, 0x00), # M_NUM (0x0235, 0x00), # M_NUM
(0x0236, 0x00), (0x0236, 0x00),
(0x0237, 0x00), (0x0237, 0x00),
(0x0238, 0x80), (0x0238, 0xA0),
(0x0239, 0x89), (0x0239, 0x8C),
(0x023A, 0x00), (0x023A, 0x00),
(0x023B, 0x00), # M_DEN (0x023B, 0x00), # M_DEN
(0x023C, 0x00), (0x023C, 0x00),
@ -156,13 +156,13 @@ def configure_si5340():
(0x0303, 0x00), (0x0303, 0x00),
(0x0304, 0x00), (0x0304, 0x00),
(0x0305, 0x00), (0x0305, 0x00),
(0x0306, 0x21), (0x0306, 0x1B),
(0x0307, 0x00), (0x0307, 0x00),
(0x0308, 0x00), # N0_DEN (0x0308, 0x00), # N0_DEN
(0x0309, 0x00), (0x0309, 0x00),
(0x030A, 0x00), (0x030A, 0x00),
(0x030B, 0x80), (0x030B, 0x80),
(0x030C, 0x01), # N0_UPDATE (0x030C, 0x01), # N0_UPDATE
# N1 Configuration (1:1 ratio) # N1 Configuration (1:1 ratio)
(0x030D, 0x00), # N1_NUM (0x030D, 0x00), # N1_NUM
@ -170,11 +170,11 @@ def configure_si5340():
(0x030F, 0x00), (0x030F, 0x00),
(0x0310, 0x00), (0x0310, 0x00),
(0x0311, 0x00), (0x0311, 0x00),
(0x0312, 0x01), (0x0312, 0x00),
(0x0313, 0x00), # N1_DEN (0x0313, 0x00), # N1_DEN
(0x0314, 0x00), (0x0314, 0x00),
(0x0315, 0x00), (0x0315, 0x00),
(0x0316, 0x01), (0x0316, 0x00),
(0x0317, 0x01), # N1_UPDATE (0x0317, 0x01), # N1_UPDATE
# N2 Configuration (1:1 ratio) # N2 Configuration (1:1 ratio)
@ -183,11 +183,11 @@ def configure_si5340():
(0x031A, 0x00), (0x031A, 0x00),
(0x031B, 0x00), (0x031B, 0x00),
(0x031C, 0x00), (0x031C, 0x00),
(0x031D, 0x01), (0x031D, 0x00),
(0x031E, 0x00), # N2_DEN (0x031E, 0x00), # N2_DEN
(0x031F, 0x00), (0x031F, 0x00),
(0x0320, 0x00), (0x0320, 0x00),
(0x0321, 0x01), (0x0321, 0x00),
(0x0322, 0x01), # N2_UPDATE (0x0322, 0x01), # N2_UPDATE
# N3 Configuration (1:1 ratio) # N3 Configuration (1:1 ratio)
@ -196,11 +196,11 @@ def configure_si5340():
(0x0325, 0x00), (0x0325, 0x00),
(0x0326, 0x00), (0x0326, 0x00),
(0x0327, 0x00), (0x0327, 0x00),
(0x0328, 0x01), (0x0328, 0x00),
(0x0329, 0x00), # N3_DEN (0x0329, 0x00), # N3_DEN
(0x032A, 0x00), (0x032A, 0x00),
(0x032B, 0x00), (0x032B, 0x00),
(0x032C, 0x01), (0x032C, 0x00),
(0x032D, 0x01), # N3_UPDATE (0x032D, 0x01), # N3_UPDATE
# Output configuration # Output configuration