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pyfastservo: fix adc init script and cleanup

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Florian Agbuya 2024-07-10 14:22:18 +08:00 committed by sb10q
parent b92d401f2b
commit e3b1525125
1 changed files with 84 additions and 242 deletions
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326
fast-servo/pyfastservo/adc.py
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@ -17,8 +17,6 @@
# You should have received a copy of the GNU General Public License # You should have received a copy of the GNU General Public License
# along with this program. If not, see <https://www.gnu.org/licenses/>. # along with this program. If not, see <https://www.gnu.org/licenses/>.
import mmap
import os
import spidev import spidev
from pyfastservo.common import ( from pyfastservo.common import (
@ -33,6 +31,8 @@ from pyfastservo.common import (
AUX_ADC_ADDR, AUX_ADC_ADDR,
MAP_MASK, MAP_MASK,
PAGESIZE, PAGESIZE,
write_to_memory,
read_from_memory
) )
# /dev/spidev1.0 <=> spidev<BUS>.<DEVICE> # /dev/spidev1.0 <=> spidev<BUS>.<DEVICE>
@ -44,276 +44,118 @@ AUX_ADC_PORT_A = 2
AUX_ADC_PORT_B = 3 AUX_ADC_PORT_B = 3
def main_adc_config(test_pattern): def spi_write(spi, address, value):
spi.xfer2([address, value])
def spi_read(spi, address):
rx_buffer = spi.xfer2([0x80 | address, 0x00])
return rx_buffer[1]
def main_adc_config(spi, test_pattern):
high_word = (test_pattern & 0xFF00) >> 8 high_word = (test_pattern & 0xFF00) >> 8
low_word = test_pattern & 0xFF low_word = test_pattern & 0xFF
spi = spidev.SpiDev() spi_write(spi, 0x00, 0x80) # reset
spi_write(spi, 0x01, 0x20) # REGISTER A1: set to Two's complement Data Format
spi_write(spi, 0x02, 0x15) # REGISTER A2: set to LVDS output, set 4 data lanes and turn on test mode
spi_write(spi, 0x03, high_word) # REGISTER A3: test pattern high word
spi_write(spi, 0x04, low_word) # REGISTER A4: test pattern low word
try: def main_adc_test_mode(spi, enable):
spi.open(MAIN_ADC_BUS, MAIN_ADC_DEVICE) reg_contents = 0x15 if enable else 0x11 # set to LVDS output, set 4 data lanes and turn on or off test mode
spi.max_speed_hz = 50000 spi_write(spi, 0x02, reg_contents)
spi.mode = 0b00 # CPOL = 0 CPHA = 0
spi.cshigh = False
# spi.read0 = False
spi_buffer = [0x00, 0x80] # reset def verify_adc_registers(spi, reg_to_check):
rx_buffer = [0x00, 0x00] for register, expected_value in reg_to_check.items():
value = spi_read(spi, register)
print(f"Spi readback register 0x{register:02x}: 0x{value:02x}")
if value != expected_value:
print(f"Different value read than sent in reg 0x{register:02x}")
spi.xfer2(spi_buffer) def read_frame():
return read_from_memory(ADC_FRAME_ADDR, 1)[0]
# REGISTER A1
spi_buffer = [0x01, 0x20] # set to Two's complement Data Format
spi.xfer2(spi_buffer)
# read values back
spi_buffer = [0x81, 0x00]
rx_buffer = spi.xfer2(spi_buffer)
print(f"Spi readback register 0x01: 0x{rx_buffer[1]:02x}")
if rx_buffer[1] != 0x20:
print("Different value read than sent in reg 0x02")
# REGISTER A2
spi_buffer = [
0x02,
0x15,
] # set to LVDS output, set 4 data lanes and turn on test mode
spi.xfer2(spi_buffer)
# read values back
spi_buffer = [0x82, 0x00]
rx_buffer = spi.xfer2(spi_buffer)
print(f"Spi readback register 0x02: 0x{rx_buffer[1]:02x}")
if rx_buffer[1] != 0x15:
print("Different value read than sent in reg 0x02")
# REGISTER A3
# test pattern high word
spi_buffer = [0x03, high_word]
spi.xfer2(spi_buffer)
# read balues back
spi_buffer = [0x83, 0x00]
rx_buffer = spi.xfer2(spi_buffer)
print(f"Spi readback register 0x03: 0x{rx_buffer[1]:02x}")
if rx_buffer[1] != high_word:
print("Different value read than sent in reg 0x03")
# REGISTER A4
# test pattern low word
spi_buffer = [0x04, low_word]
spi.xfer2(spi_buffer)
# read balues back
spi_buffer = [0x84, 0x00]
rx_buffer = spi.xfer2(spi_buffer)
print(f"Spi readback register 0x04: 0x{rx_buffer[1]:02x}")
if rx_buffer[1] != low_word:
print("Different value read than sent in reg 0x04")
finally:
spi.close()
def main_adc_test_mode(enable):
spi = spidev.SpiDev()
try:
spi.open(MAIN_ADC_BUS, MAIN_ADC_DEVICE)
spi.max_speed_hz = 50000
spi.mode = 0b00 # CPOL = 0 CPHA = 0
spi.cshigh = False
# spi.read0 = True
reg_contents = (
0x15 if enable else 0x11
) # set to LVDS output, set 4 data lanes and turn on or off test mode
spi_buffer = [0x02, reg_contents]
spi.xfer2(spi_buffer)
# read values back
spi_buffer = [0x82, 0x00]
rx_buffer = spi.xfer2(spi_buffer)
print(f"Spi readback register 0x02: 0x{rx_buffer[1]:02x}")
if rx_buffer[1] != reg_contents:
print("Different value read than sent in reg 0x02")
finally:
spi.close()
def read_from_memory(address, n_bytes):
assert n_bytes <= 4
addr = address
try:
f = os.open("/dev/mem", os.O_SYNC | os.O_RDWR)
with mmap.mmap(
f,
PAGESIZE,
mmap.MAP_SHARED,
mmap.PROT_READ | mmap.PROT_WRITE,
offset=addr & ~MAP_MASK,
) as mem:
start_addr = addr & MAP_MASK
stop_addr = start_addr + 4
# print(f"addr: 0x{addr:x}\tstart_addr: 0x{start_addr}\tstop_addr: 0x{stop_addr}")
contents = mem[start_addr:stop_addr]
read_value = list(contents)[:n_bytes]
# print("Read value: ", read_value)
finally:
os.close(f)
return read_value
def write_to_memory(address, value):
value_bytes = value.to_bytes(4, "little")
addr = address
try:
f = os.open("/dev/mem", os.O_SYNC | os.O_RDWR)
with mmap.mmap(
f,
PAGESIZE,
mmap.MAP_SHARED,
mmap.PROT_READ | mmap.PROT_WRITE,
offset=addr & ~MAP_MASK,
) as mem:
start_addr = addr & MAP_MASK
stop_addr = start_addr + 4
# print(f"addr: 0x{addr:x}\tstart_addr: 0x{start_addr}\tstop_addr: 0x{stop_addr}")
mem[start_addr:stop_addr] = value_bytes
contents = mem[start_addr:stop_addr]
# print("Read value: ", list(contents), " written value: ", list(value_bytes))
finally:
os.close(f)
def word_align():
value = 0
edge_detected = False
transition = False
tap_delay = 0
def perform_bitslip():
for i in range(4): for i in range(4):
current_frame = read_from_memory(ADC_FRAME_ADDR, 1)[0] current_frame = read_frame()
if current_frame != 0x0C: if current_frame != 0x0C:
print( print(f"Performing bitslip (iteration: {i}). Current frame: 0x{current_frame:02x}")
f"Performing bitslip (bitslip iteration: {i}). Reason: current_frame is 0x{current_frame:02x} instead of 0x0C"
)
write_to_memory(ADC_BITSLIP_ADDR, 1) write_to_memory(ADC_BITSLIP_ADDR, 1)
else: else:
print(f"No bitslip required; Currernt frame = 0x{current_frame:02x}") print(f"No bitslip required; Current frame: 0x{current_frame:02x}")
break return
current_frame = read_from_memory(ADC_FRAME_ADDR, 1)[0] def find_edge():
prev_frame = current_frame prev_frame = read_frame()
transition = False
for i in range(32): for tap_delay in range(32):
write_to_memory(ADC_DELAY_ADDR, tap_delay) write_to_memory(ADC_DELAY_ADDR, tap_delay)
if edge_detected == 1: current_frame = read_frame()
break
current_frame = read_from_memory(ADC_FRAME_ADDR, 1)[0]
print(f"Tap delay: {tap_delay}") print(f"Tap delay: {tap_delay}, Current frame: 0x{current_frame:02x}")
print(f"Current frame: 0x{current_frame:02x}")
if current_frame == prev_frame: if current_frame != prev_frame:
tap_delay += 1 if not transition:
elif not transition: transition = True
tap_delay += 1 else:
transition = True final_delay = (tap_delay // 2) + 2
elif transition: print(f"Edge detected; setting iDelay to: {final_delay}")
tap_delay = i // 2 write_to_memory(ADC_DELAY_ADDR, final_delay)
edge_detected = True return
prev_frame = current_frame prev_frame = current_frame
if not edge_detected: # If no edge detected
tap_delay = 11 # empirically tested to work best final_delay = 11
write_to_memory(ADC_DELAY_ADDR, tap_delay) print(f"No edge detected; setting iDelay to: {final_delay}")
print(f"No edge detected; setting iDelay to: {tap_delay}") write_to_memory(ADC_DELAY_ADDR, final_delay)
if edge_detected:
write_to_memory(ADC_DELAY_ADDR, tap_delay + 2)
print(f"Edge detected; setting iDelay to (tap_delay + 2): {tap_delay} + 2")
adc_ch0 = read_from_memory(ADC_CH0_HIGH_ADDR, 4) def read_adc_channel(high_addr, low_addr):
print(f"ADC_CH0: 0x{adc_ch0}") return (read_from_memory(high_addr, 1)[0] << 8) | read_from_memory(low_addr, 1)[0]
adc_ch0 = (read_from_memory(ADC_CH0_HIGH_ADDR, 1)[0] << 8) | read_from_memory( def print_adc_channels():
ADC_CH0_LOW_ADDR, 1 adc_ch0 = read_adc_channel(ADC_CH0_HIGH_ADDR, ADC_CH0_LOW_ADDR)
)[0] adc_ch1 = read_adc_channel(ADC_CH1_HIGH_ADDR, ADC_CH1_LOW_ADDR)
adc_ch1 = (read_from_memory(ADC_CH1_HIGH_ADDR, 1)[0] << 8) | read_from_memory(
ADC_CH1_LOW_ADDR, 1
)[0]
print(f"Final ADC_CH0: 0x{adc_ch0:04x}") print(f"Final ADC_CH0: 0x{adc_ch0:04x}")
print(f"Final ADC_CH1: 0x{adc_ch1:04x}") print(f"Final ADC_CH1: 0x{adc_ch1:04x}")
def enable_adc_afe(ch1_x10=False, ch2_x10=False):
ctrl_value = (ch2_x10 << 1) | ch1_x10
write_to_memory(ADC_AFE_CTRL_ADDR, ctrl_value)
afe_ctrl = read_from_memory(ADC_AFE_CTRL_ADDR, 1)[0]
print(f"ADC_AFE_CTRL: 0x{afe_ctrl:02X}")
return afe_ctrl
def modify_bit(original_value, position, bit_value): def configure_ltc2195():
mask = 1 << position
return (original_value & ~mask) | (bit_value << position)
def adc_aux_config():
# MSB to LSB
# | RANGE | ADDR [2:0] | DIFF |
# DIFF = 0 => configure as single ended (it is negated in gateware)
# RANGE = 0 => configure as 0-2.5 Vref
to_write = 0b00000
write_to_memory(AUX_ADC_ADDR, to_write)
def adc_aux_read(port, type, pin):
# port:
# 1 - port A
# 2 - port B
# type:
# 0 - single-ended
# 1 - differential
# pin:
# 0b000 - VA1/VB1
# 0b001 - VA2/VB2
# 0b010 - VA3/VB3
# 0b011 - VA4/VB4
assert type in (0, 1)
assert port in (1, 2)
write_buffer = [0, 0]
read_buffer = [0, 0]
aux_config_reg = read_from_memory(AUX_ADC_ADDR, 1)[0]
aux_config = (aux_config_reg & 0b10001) | pin << 1
write_to_memory(AUX_ADC_ADDR, aux_config)
spi = spidev.SpiDev() spi = spidev.SpiDev()
try: try:
spi.open(1, 3) # AUX ADC 1? spi.open(MAIN_ADC_BUS, MAIN_ADC_DEVICE)
spi.max_speed_hz = 5000 spi.max_speed_hz = 50000
spi.mode = 0b00 spi.mode = 0b00 # CPOL = 0 CPHA = 0
spi.cshigh = False spi.cshigh = False
read_buffer = spi.xfer2(write_buffer) test_pattern = 0x811F
mu_voltage = read_buffer[0] << 8 | read_buffer[1] >> 2 main_adc_config(spi, test_pattern)
print(f"MU_voltage: 0x{mu_voltage:04X}")
print(f"Read_buffer[0]: 0x{read_buffer[0]:02X}") verify_adc_registers(spi, {
print(f"Read_buffer[1]: 0x{read_buffer[1]:02X}") 0x01: 0x20,
return mu_voltage * 2.5 / 4096 0x02: 0x15,
0x03: (test_pattern & 0xFF00) >> 8,
0x04: test_pattern & 0xFF
})
# Performing Word Align
perform_bitslip()
find_edge()
print_adc_channels()
main_adc_test_mode(spi, False)
verify_adc_registers(spi, {0x02: 0x11}) # Verify test mode is off
enable_adc_afe()
finally: finally:
spi.close() spi.close()
def main():
main_adc_config(0x811F)
word_align()
main_adc_test_mode(False)
write_to_memory(ADC_AFE_CTRL_ADDR, 0b1100) # {-, -, ch2_X10, ch1_X10}
print(read_from_memory(ADC_AFE_CTRL_ADDR, 1)[0])
if __name__ == "__main__": if __name__ == "__main__":
main() configure_ltc2195()