gateware: use si5340 to generate PL's rst

fast-servo/linien-gateware/fast_servo_platform.py

@@ -194,7 +194,7 @@ _io = [
 
     # Si540 nRST
     ("nrst", 0, Pins("M7"), IOStandard("LVCMOS18")),
-
+    ("si5340_nlol", 0, Pins("P2"),IOStandard("LVCMOS18")),
 ]
 
 

fast-servo/linien-gateware/fast_servo_soc.py

@@ -54,6 +54,10 @@ class CRG(Module):
         clk_sys_double = Signal()
         clk_idelay = Signal()
 
+        si5340_nlol = platform.request("si5340_nlol")
+        si5340_nlol_buf = Signal()
+        self.specials += Instance("IBUF", i_I=si5340_nlol, o_O=si5340_nlol_buf)
+
         self.specials += [
             Instance(
                 "PLLE2_BASE",
@@ -66,7 +70,7 @@ class CRG(Module):
                 p_STARTUP_WAIT="FALSE",
                 i_CLKIN1=clk100_buf,
                 i_PWRDWN=0,
-                i_RST=self.ps_rst,
+                i_RST=self.ps_rst | ~si5340_nlol_buf,
                 i_CLKFBIN=clk_feedback_buf,
                 o_CLKFBOUT=clk_feedback,
                 p_CLKOUT0_DIVIDE=10,