From d9d44fa9e81c98929d6096a85ce2ef631e87e3e2 Mon Sep 17 00:00:00 2001 From: linuswck Date: Thu, 9 Jan 2025 16:56:56 +0800 Subject: [PATCH] gateware: use si5340 to generate PL's rst --- fast-servo/linien-gateware/fast_servo_platform.py | 2 +- fast-servo/linien-gateware/fast_servo_soc.py | 6 +++++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/fast-servo/linien-gateware/fast_servo_platform.py b/fast-servo/linien-gateware/fast_servo_platform.py index 13b4aa3..b490040 100644 --- a/fast-servo/linien-gateware/fast_servo_platform.py +++ b/fast-servo/linien-gateware/fast_servo_platform.py @@ -194,7 +194,7 @@ _io = [ # Si540 nRST ("nrst", 0, Pins("M7"), IOStandard("LVCMOS18")), - + ("si5340_nlol", 0, Pins("P2"),IOStandard("LVCMOS18")), ] diff --git a/fast-servo/linien-gateware/fast_servo_soc.py b/fast-servo/linien-gateware/fast_servo_soc.py index 93b2e2d..257fc8b 100644 --- a/fast-servo/linien-gateware/fast_servo_soc.py +++ b/fast-servo/linien-gateware/fast_servo_soc.py @@ -54,6 +54,10 @@ class CRG(Module): clk_sys_double = Signal() clk_idelay = Signal() + si5340_nlol = platform.request("si5340_nlol") + si5340_nlol_buf = Signal() + self.specials += Instance("IBUF", i_I=si5340_nlol, o_O=si5340_nlol_buf) + self.specials += [ Instance( "PLLE2_BASE", @@ -66,7 +70,7 @@ class CRG(Module): p_STARTUP_WAIT="FALSE", i_CLKIN1=clk100_buf, i_PWRDWN=0, - i_RST=self.ps_rst, + i_RST=self.ps_rst | ~si5340_nlol_buf, i_CLKFBIN=clk_feedback_buf, o_CLKFBOUT=clk_feedback, p_CLKOUT0_DIVIDE=10,