gateware: Revert IIR Coeff Width to 18bit

- Revert commit 25dd0db. Related Issue: #40.
- Fail to meet timing for IIR Filter's Multiply and Add operation as
    multiplication operation cannot be fitted inside a single DSP
    Slice (25b x 18b). Thus, multiple DSPs are needed for multiplication.
    This causes timing violation at 100MHz and 125MHz sys frequency.

fast-servo/iir_pipeline.patch

@@ -1,13 +0,0 @@
-diff --git a/gateware/logic/iir.py b/gateware/logic/iir.py
-index 2380dd7..60bfeb7 100644
---- a/gateware/logic/iir.py
-+++ b/gateware/logic/iir.py
-@@ -89,7 +89,7 @@ class Iir(Filter):
-                 zr = Signal.like(z)
-                 self.sync += zr.eq(z)
-                 z = Signal.like(zr)
--                self.comb += z.eq(zr + signal * c[coeff])
-+                self.sync += z.eq(zr + signal * c[coeff])
-             self.comb += y_next.eq(z)
-             self.latency.value = Constant(order + 1)
-             self.interval.value = Constant(1)

fast-servo/linien-module-iir-coeff-width-set-to-18bit.patch

@@ -0,0 +1,22 @@
+diff --git a/gateware/linien_module.py b/gateware/linien_module.py
+index a64714c..1d905de 100644
+--- a/gateware/linien_module.py
++++ b/gateware/linien_module.py
+@@ -47,7 +47,7 @@ from .lowlevel.scopegen import ScopeGen
+ 
+ 
+ class LinienLogic(Module, AutoCSR):
+-    def __init__(self, width=14, signal_width=25, chain_factor_width=8, coeff_width=25):
++    def __init__(self, width=14, signal_width=25, chain_factor_width=8, coeff_width=18):
+         self.init_csr(width, chain_factor_width)
+         self.init_submodules(width, signal_width)
+         self.connect_pid()
+@@ -154,7 +154,7 @@ class LinienModule(Module, AutoCSR):
+     def __init__(self, soc):
+         width = 14
+         signal_width = 25
+-        coeff_width = 25
++        coeff_width = 18
+         chain_factor_bits = 8
+ 
+         self.init_submodules(

flake.nix

@@ -35,7 +35,7 @@
             ./fast-servo/linien-server-fast-servo.patch
             ./fast-servo/linien-gateware-fast-servo.patch 
             ./fast-servo/autolock_pipeline.patch
-            ./fast-servo/iir_pipeline.patch
+            ./fast-servo/linien-module-iir-coeff-width-set-to-18bit.patch
             ./fast-servo/linien_module_pipeline.patch
             ./fast-servo/pid_pipeline.patch
             ./fast-servo/pid_err_sig_pipeline.patch