Fix malformed pid_pipeline patch

fast-servo/pid_pipeline.patch

@@ -1,5 +1,5 @@
 diff --git a/gateware/logic/pid.py b/gateware/logic/pid.py
-index 4320f94..64e1a74 100644
+index 4320f94..e737577 100644
 --- a/gateware/logic/pid.py
 +++ b/gateware/logic/pid.py
 @@ -56,10 +56,13 @@ class PID(Module, AutoCSR):
@@ -50,7 +50,7 @@ index 4320f94..64e1a74 100644
              kd_reg_r.eq(kd_reg),
              self.output_d.eq(kd_reg - kd_reg_r),
          ]
-@@ -143,4 +150,12 @@ class PID(Module, AutoCSR):
+@@ -143,4 +150,10 @@ class PID(Module, AutoCSR):
  
          # sync is required here, otherwise we get artifacts when one of the
          # signals changes sign