Fix malformed pid_pipeline patch
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@ -1,5 +1,5 @@
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diff --git a/gateware/logic/pid.py b/gateware/logic/pid.py
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diff --git a/gateware/logic/pid.py b/gateware/logic/pid.py
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index 4320f94..64e1a74 100644
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index 4320f94..e737577 100644
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--- a/gateware/logic/pid.py
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--- a/gateware/logic/pid.py
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+++ b/gateware/logic/pid.py
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+++ b/gateware/logic/pid.py
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@@ -56,10 +56,13 @@ class PID(Module, AutoCSR):
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@@ -56,10 +56,13 @@ class PID(Module, AutoCSR):
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@ -50,7 +50,7 @@ index 4320f94..64e1a74 100644
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kd_reg_r.eq(kd_reg),
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kd_reg_r.eq(kd_reg),
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self.output_d.eq(kd_reg - kd_reg_r),
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self.output_d.eq(kd_reg - kd_reg_r),
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]
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]
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@@ -143,4 +150,12 @@ class PID(Module, AutoCSR):
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@@ -143,4 +150,10 @@ class PID(Module, AutoCSR):
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# sync is required here, otherwise we get artifacts when one of the
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# sync is required here, otherwise we get artifacts when one of the
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# signals changes sign
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# signals changes sign
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