pyfastservo: fix adc init script and cleanup
This commit is contained in:
parent
8506da0128
commit
acf58c9224
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@ -17,8 +17,6 @@
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# You should have received a copy of the GNU General Public License
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# along with this program. If not, see <https://www.gnu.org/licenses/>.
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import mmap
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import os
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import spidev
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from pyfastservo.common import (
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@ -33,6 +31,8 @@ from pyfastservo.common import (
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AUX_ADC_ADDR,
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MAP_MASK,
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PAGESIZE,
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write_to_memory,
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read_from_memory
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)
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# /dev/spidev1.0 <=> spidev<BUS>.<DEVICE>
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@ -44,276 +44,118 @@ AUX_ADC_PORT_A = 2
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AUX_ADC_PORT_B = 3
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def main_adc_config(test_pattern):
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def spi_write(spi, address, value):
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spi.xfer2([address, value])
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def spi_read(spi, address):
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rx_buffer = spi.xfer2([0x80 | address, 0x00])
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return rx_buffer[1]
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def main_adc_config(spi, test_pattern):
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high_word = (test_pattern & 0xFF00) >> 8
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low_word = test_pattern & 0xFF
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spi = spidev.SpiDev()
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spi_write(spi, 0x00, 0x80) # reset
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spi_write(spi, 0x01, 0x20) # REGISTER A1: set to Two's complement Data Format
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spi_write(spi, 0x02, 0x15) # REGISTER A2: set to LVDS output, set 4 data lanes and turn on test mode
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spi_write(spi, 0x03, high_word) # REGISTER A3: test pattern high word
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spi_write(spi, 0x04, low_word) # REGISTER A4: test pattern low word
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try:
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spi.open(MAIN_ADC_BUS, MAIN_ADC_DEVICE)
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spi.max_speed_hz = 50000
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spi.mode = 0b00 # CPOL = 0 CPHA = 0
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spi.cshigh = False
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# spi.read0 = False
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def main_adc_test_mode(spi, enable):
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reg_contents = 0x15 if enable else 0x11 # set to LVDS output, set 4 data lanes and turn on or off test mode
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spi_write(spi, 0x02, reg_contents)
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spi_buffer = [0x00, 0x80] # reset
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rx_buffer = [0x00, 0x00]
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def verify_adc_registers(spi, reg_to_check):
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for register, expected_value in reg_to_check.items():
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value = spi_read(spi, register)
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print(f"Spi readback register 0x{register:02x}: 0x{value:02x}")
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if value != expected_value:
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print(f"Different value read than sent in reg 0x{register:02x}")
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spi.xfer2(spi_buffer)
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# REGISTER A1
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spi_buffer = [0x01, 0x20] # set to Two's complement Data Format
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spi.xfer2(spi_buffer)
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# read values back
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spi_buffer = [0x81, 0x00]
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rx_buffer = spi.xfer2(spi_buffer)
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print(f"Spi readback register 0x01: 0x{rx_buffer[1]:02x}")
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if rx_buffer[1] != 0x20:
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print("Different value read than sent in reg 0x02")
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# REGISTER A2
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spi_buffer = [
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0x02,
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0x15,
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] # set to LVDS output, set 4 data lanes and turn on test mode
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spi.xfer2(spi_buffer)
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# read values back
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spi_buffer = [0x82, 0x00]
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rx_buffer = spi.xfer2(spi_buffer)
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print(f"Spi readback register 0x02: 0x{rx_buffer[1]:02x}")
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if rx_buffer[1] != 0x15:
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print("Different value read than sent in reg 0x02")
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# REGISTER A3
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# test pattern high word
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spi_buffer = [0x03, high_word]
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spi.xfer2(spi_buffer)
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# read balues back
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spi_buffer = [0x83, 0x00]
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rx_buffer = spi.xfer2(spi_buffer)
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print(f"Spi readback register 0x03: 0x{rx_buffer[1]:02x}")
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if rx_buffer[1] != high_word:
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print("Different value read than sent in reg 0x03")
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# REGISTER A4
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# test pattern low word
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spi_buffer = [0x04, low_word]
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spi.xfer2(spi_buffer)
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# read balues back
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spi_buffer = [0x84, 0x00]
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rx_buffer = spi.xfer2(spi_buffer)
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print(f"Spi readback register 0x04: 0x{rx_buffer[1]:02x}")
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if rx_buffer[1] != low_word:
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print("Different value read than sent in reg 0x04")
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finally:
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spi.close()
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def main_adc_test_mode(enable):
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spi = spidev.SpiDev()
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try:
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spi.open(MAIN_ADC_BUS, MAIN_ADC_DEVICE)
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spi.max_speed_hz = 50000
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spi.mode = 0b00 # CPOL = 0 CPHA = 0
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spi.cshigh = False
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# spi.read0 = True
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reg_contents = (
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0x15 if enable else 0x11
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) # set to LVDS output, set 4 data lanes and turn on or off test mode
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spi_buffer = [0x02, reg_contents]
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spi.xfer2(spi_buffer)
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# read values back
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spi_buffer = [0x82, 0x00]
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rx_buffer = spi.xfer2(spi_buffer)
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print(f"Spi readback register 0x02: 0x{rx_buffer[1]:02x}")
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if rx_buffer[1] != reg_contents:
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print("Different value read than sent in reg 0x02")
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finally:
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spi.close()
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def read_from_memory(address, n_bytes):
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assert n_bytes <= 4
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addr = address
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try:
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f = os.open("/dev/mem", os.O_SYNC | os.O_RDWR)
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with mmap.mmap(
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f,
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PAGESIZE,
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mmap.MAP_SHARED,
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mmap.PROT_READ | mmap.PROT_WRITE,
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offset=addr & ~MAP_MASK,
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) as mem:
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start_addr = addr & MAP_MASK
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stop_addr = start_addr + 4
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# print(f"addr: 0x{addr:x}\tstart_addr: 0x{start_addr}\tstop_addr: 0x{stop_addr}")
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contents = mem[start_addr:stop_addr]
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read_value = list(contents)[:n_bytes]
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# print("Read value: ", read_value)
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finally:
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os.close(f)
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return read_value
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def write_to_memory(address, value):
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value_bytes = value.to_bytes(4, "little")
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addr = address
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try:
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f = os.open("/dev/mem", os.O_SYNC | os.O_RDWR)
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with mmap.mmap(
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f,
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PAGESIZE,
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mmap.MAP_SHARED,
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mmap.PROT_READ | mmap.PROT_WRITE,
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offset=addr & ~MAP_MASK,
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) as mem:
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start_addr = addr & MAP_MASK
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stop_addr = start_addr + 4
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# print(f"addr: 0x{addr:x}\tstart_addr: 0x{start_addr}\tstop_addr: 0x{stop_addr}")
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mem[start_addr:stop_addr] = value_bytes
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contents = mem[start_addr:stop_addr]
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# print("Read value: ", list(contents), " written value: ", list(value_bytes))
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finally:
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os.close(f)
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def word_align():
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value = 0
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edge_detected = False
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transition = False
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tap_delay = 0
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def read_frame():
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return read_from_memory(ADC_FRAME_ADDR, 1)[0]
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def perform_bitslip():
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for i in range(4):
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current_frame = read_from_memory(ADC_FRAME_ADDR, 1)[0]
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current_frame = read_frame()
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if current_frame != 0x0C:
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print(
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f"Performing bitslip (bitslip iteration: {i}). Reason: current_frame is 0x{current_frame:02x} instead of 0x0C"
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)
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print(f"Performing bitslip (iteration: {i}). Current frame: 0x{current_frame:02x}")
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write_to_memory(ADC_BITSLIP_ADDR, 1)
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else:
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print(f"No bitslip required; Currernt frame = 0x{current_frame:02x}")
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break
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print(f"No bitslip required; Current frame: 0x{current_frame:02x}")
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return
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current_frame = read_from_memory(ADC_FRAME_ADDR, 1)[0]
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prev_frame = current_frame
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for i in range(32):
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def find_edge():
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prev_frame = read_frame()
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transition = False
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for tap_delay in range(32):
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write_to_memory(ADC_DELAY_ADDR, tap_delay)
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if edge_detected == 1:
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break
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current_frame = read_from_memory(ADC_FRAME_ADDR, 1)[0]
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current_frame = read_frame()
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print(f"Tap delay: {tap_delay}")
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print(f"Current frame: 0x{current_frame:02x}")
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print(f"Tap delay: {tap_delay}, Current frame: 0x{current_frame:02x}")
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if current_frame == prev_frame:
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tap_delay += 1
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elif not transition:
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tap_delay += 1
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if current_frame != prev_frame:
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if not transition:
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transition = True
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elif transition:
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tap_delay = i // 2
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edge_detected = True
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else:
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final_delay = (tap_delay // 2) + 2
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print(f"Edge detected; setting iDelay to: {final_delay}")
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write_to_memory(ADC_DELAY_ADDR, final_delay)
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return
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prev_frame = current_frame
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if not edge_detected:
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tap_delay = 11 # empirically tested to work best
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write_to_memory(ADC_DELAY_ADDR, tap_delay)
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print(f"No edge detected; setting iDelay to: {tap_delay}")
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if edge_detected:
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write_to_memory(ADC_DELAY_ADDR, tap_delay + 2)
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print(f"Edge detected; setting iDelay to (tap_delay + 2): {tap_delay} + 2")
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# If no edge detected
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final_delay = 11
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print(f"No edge detected; setting iDelay to: {final_delay}")
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write_to_memory(ADC_DELAY_ADDR, final_delay)
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adc_ch0 = read_from_memory(ADC_CH0_HIGH_ADDR, 4)
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print(f"ADC_CH0: 0x{adc_ch0}")
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def read_adc_channel(high_addr, low_addr):
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return (read_from_memory(high_addr, 1)[0] << 8) | read_from_memory(low_addr, 1)[0]
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adc_ch0 = (read_from_memory(ADC_CH0_HIGH_ADDR, 1)[0] << 8) | read_from_memory(
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ADC_CH0_LOW_ADDR, 1
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)[0]
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adc_ch1 = (read_from_memory(ADC_CH1_HIGH_ADDR, 1)[0] << 8) | read_from_memory(
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ADC_CH1_LOW_ADDR, 1
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)[0]
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def print_adc_channels():
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adc_ch0 = read_adc_channel(ADC_CH0_HIGH_ADDR, ADC_CH0_LOW_ADDR)
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adc_ch1 = read_adc_channel(ADC_CH1_HIGH_ADDR, ADC_CH1_LOW_ADDR)
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print(f"Final ADC_CH0: 0x{adc_ch0:04x}")
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print(f"Final ADC_CH1: 0x{adc_ch1:04x}")
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def enable_adc_afe(ch1_x10=False, ch2_x10=False):
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ctrl_value = (ch2_x10 << 1) | ch1_x10
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write_to_memory(ADC_AFE_CTRL_ADDR, ctrl_value)
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afe_ctrl = read_from_memory(ADC_AFE_CTRL_ADDR, 1)[0]
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print(f"ADC_AFE_CTRL: 0x{afe_ctrl:02X}")
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return afe_ctrl
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def modify_bit(original_value, position, bit_value):
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mask = 1 << position
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return (original_value & ~mask) | (bit_value << position)
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def adc_aux_config():
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# MSB to LSB
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# | RANGE | ADDR [2:0] | DIFF |
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# DIFF = 0 => configure as single ended (it is negated in gateware)
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# RANGE = 0 => configure as 0-2.5 Vref
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to_write = 0b00000
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write_to_memory(AUX_ADC_ADDR, to_write)
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def adc_aux_read(port, type, pin):
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# port:
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# 1 - port A
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# 2 - port B
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# type:
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# 0 - single-ended
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# 1 - differential
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# pin:
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# 0b000 - VA1/VB1
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# 0b001 - VA2/VB2
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# 0b010 - VA3/VB3
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# 0b011 - VA4/VB4
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assert type in (0, 1)
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assert port in (1, 2)
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write_buffer = [0, 0]
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read_buffer = [0, 0]
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aux_config_reg = read_from_memory(AUX_ADC_ADDR, 1)[0]
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aux_config = (aux_config_reg & 0b10001) | pin << 1
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write_to_memory(AUX_ADC_ADDR, aux_config)
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def configure_ltc2195():
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spi = spidev.SpiDev()
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try:
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spi.open(1, 3) # AUX ADC 1?
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spi.max_speed_hz = 5000
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spi.mode = 0b00
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spi.open(MAIN_ADC_BUS, MAIN_ADC_DEVICE)
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spi.max_speed_hz = 50000
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spi.mode = 0b00 # CPOL = 0 CPHA = 0
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spi.cshigh = False
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read_buffer = spi.xfer2(write_buffer)
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mu_voltage = read_buffer[0] << 8 | read_buffer[1] >> 2
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print(f"MU_voltage: 0x{mu_voltage:04X}")
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print(f"Read_buffer[0]: 0x{read_buffer[0]:02X}")
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print(f"Read_buffer[1]: 0x{read_buffer[1]:02X}")
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return mu_voltage * 2.5 / 4096
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test_pattern = 0x811F
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main_adc_config(spi, test_pattern)
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verify_adc_registers(spi, {
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0x01: 0x20,
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0x02: 0x15,
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0x03: (test_pattern & 0xFF00) >> 8,
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0x04: test_pattern & 0xFF
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})
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# Performing Word Align
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perform_bitslip()
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find_edge()
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print_adc_channels()
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main_adc_test_mode(spi, False)
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verify_adc_registers(spi, {0x02: 0x11}) # Verify test mode is off
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enable_adc_afe()
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finally:
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spi.close()
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def main():
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main_adc_config(0x811F)
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word_align()
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main_adc_test_mode(False)
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write_to_memory(ADC_AFE_CTRL_ADDR, 0b1100) # {-, -, ch2_X10, ch1_X10}
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print(read_from_memory(ADC_AFE_CTRL_ADDR, 1)[0])
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if __name__ == "__main__":
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main()
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configure_ltc2195()
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