diff --git a/fast-servo/linien_module_pipeline.patch b/fast-servo/linien_module_pipeline.patch
index 4206247..fd84ceb 100644
--- a/fast-servo/linien_module_pipeline.patch
+++ b/fast-servo/linien_module_pipeline.patch
@@ -1,13 +1,12 @@
 diff --git a/gateware/linien_module.py b/gateware/linien_module.py
-index a958896..a64714c 100644
+index 54b6285..c3f8d14 100644
 --- a/gateware/linien_module.py
 +++ b/gateware/linien_module.py
-@@ -233,23 +233,46 @@ class LinienModule(Module, AutoCSR):
+@@ -233,30 +233,52 @@ class LinienModule(Module, AutoCSR):
              self.fast_a.adc.eq(soc.analog.adc_a),
              self.fast_b.adc.eq(soc.analog.adc_b),
          ]
 -
-+        
          # now, we combine the output of the two paths, with a variable factor each.
          mixed = Signal(
              (2 + ((signal_width + 1) + self.logic.chain_a_factor.size), True)
@@ -42,16 +41,26 @@ index a958896..a64714c 100644
 -                    (self.logic.chain_a_factor.storage * self.fast_a.out_i)
 -                    + (self.logic.chain_b_factor.storage * self.fast_b.out_i)
 -                    + (self.logic.combined_offset_signed << (chain_factor_bits + s))
-+                    chain_a_factor_mult_fast_a_out_i
++                    (chain_a_factor_mult_fast_a_out_i
 +                    + chain_b_factor_mult_fast_b_out_i
-+                    + combined_offset_signed_left_shifted
++                    + combined_offset_signed_left_shifted) >> chain_factor_bits
                  ),
              ).Else(
                  mixed.eq(
 -                    (self.fast_a.out_i << chain_factor_bits)
 -                    + (self.logic.combined_offset_signed << (chain_factor_bits + s))
-+                    fast_a_out_i_left_shifted
-+                    + combined_offset_signed_left_shifted
-                 )
+-                )
++                    (fast_a_out_i_left_shifted
++                    + combined_offset_signed_left_shifted) >> chain_factor_bits
++                ),
              )
          ]
+ 
+         mixed_limited = Signal((signal_width, True))
+-        self.comb += [
+-            self.logic.limit_error_signal.x.eq(mixed >> chain_factor_bits),
++        self.sync += [
++            self.logic.limit_error_signal.x.eq(mixed),
+             mixed_limited.eq(self.logic.limit_error_signal.y),
+         ]
+ 
\ No newline at end of file