M-Labs/nix-servo
3
1
Fork 2
Code Issues 1 Pull Requests Packages Projects Releases Wiki Activity

gateware: async fifo with depth of 2 is broken

Browse Source 
- Changing depth to 4 has resolved cdc issue
This commit is contained in:
linuswck 2024-11-15 15:21:09 +08:00
parent 8a40bb4f21
commit 87059eef2b
2 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
fast-servo/linien-gateware/cores/adc.py
View File

@ -135,7 +135,7 @@ class ADC(Module, AutoCSR):
self.s_frame = Signal(4) self.s_frame = Signal(4)
self.s_frame_cdc = Signal(4) self.s_frame_cdc = Signal(4)
self.submodules.cdc_fifo = ClockDomainsRenamer({"write": "dco2d", "read": "sys"})(AsyncFIFO([("data", 36)], 2)) self.submodules.cdc_fifo = ClockDomainsRenamer({"write": "dco2d", "read": "sys"})(AsyncFIFO([("data", 36)], 4))
self.comb += [ self.comb += [
self.cdc_fifo.sink.data.eq(Cat(self.data_out_cdc[0], self.data_out_cdc[1], self.s_frame_cdc)), self.cdc_fifo.sink.data.eq(Cat(self.data_out_cdc[0], self.data_out_cdc[1], self.s_frame_cdc)),
self.cdc_fifo.sink.stb.eq(~ResetSignal("dco2d")), self.cdc_fifo.sink.stb.eq(~ResetSignal("dco2d")),

2
fast-servo/linien-gateware/cores/dac.py
View File

@ -42,7 +42,7 @@ class DAC(Module, AutoCSR):
self.data_in_cdc = [Signal(14, reset_less=True), Signal(14, reset_less=True)] self.data_in_cdc = [Signal(14, reset_less=True), Signal(14, reset_less=True)]
platform.add_period_constraint(dac_pads.dclkio, 10.0) platform.add_period_constraint(dac_pads.dclkio, 10.0)
self.submodules.cdc_fifo = ClockDomainsRenamer({"write": "sys", "read": "dco2d"})(AsyncFIFO([("data", 28)], 2)) self.submodules.cdc_fifo = ClockDomainsRenamer({"write": "sys", "read": "dco2d"})(AsyncFIFO([("data", 28)], 4))
self.comb += [ self.comb += [
self.cdc_fifo.sink.data.eq(Cat(self.data_in[0], self.data_in[1])), self.cdc_fifo.sink.data.eq(Cat(self.data_in[0], self.data_in[1])),
self.cdc_fifo.sink.stb.eq(~ResetSignal("sys")), self.cdc_fifo.sink.stb.eq(~ResetSignal("sys")),