diff --git a/fast-servo/fast-servo.dts b/fast-servo/fast-servo.dts index 87b4644..0bf608c 100644 --- a/fast-servo/fast-servo.dts +++ b/fast-servo/fast-servo.dts @@ -576,7 +576,7 @@ / { cpus { cpu@0 { - operating-points = <500000 1000000 250000 1000000>; + operating-points = <666667 1000000 333334 1000000>; }; }; }; diff --git a/fast-servo/fsbl-support/ps7_init.c b/fast-servo/fsbl-support/ps7_init.c index 46994c9..5045ece 100644 --- a/fast-servo/fsbl-support/ps7_init.c +++ b/fast-servo/fsbl-support/ps7_init.c @@ -25,23 +25,23 @@ unsigned long ps7_pll_init_data_3_0[] = { // .. FINISH: SLCR SETTINGS // .. START: PLL SLCR REGISTERS // .. .. START: ARM PLL INIT - // .. .. PLL_RES = 0xc - // .. .. ==> 0XF8000110[7:4] = 0x0000000CU - // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U // .. .. PLL_CP = 0x2 // .. .. ==> 0XF8000110[11:8] = 0x00000002U // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0x145 - // .. .. ==> 0XF8000110[21:12] = 0x00000145U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U // .. .. - EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001452C0U), + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x1e - // .. .. .. ==> 0XF8000100[18:12] = 0x0000001EU - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001E000U), + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), // .. .. .. FINISH: UPDATE FB_DIV // .. .. .. START: BY PASS PLL // .. .. .. PLL_BYPASS_FORCE = 1 @@ -273,9 +273,9 @@ unsigned long ps7_clock_init_data_3_0[] = { // .. CLKACT = 0x1 // .. ==> 0XF8000140[0:0] = 0x00000001U // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x2 - // .. ==> 0XF8000140[6:4] = 0x00000002U - // .. ==> MASK : 0x00000070U VAL : 0x00000020U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U // .. DIVISOR = 0x8 // .. ==> 0XF8000140[13:8] = 0x00000008U // .. ==> MASK : 0x00003F00U VAL : 0x00000800U @@ -283,7 +283,7 @@ unsigned long ps7_clock_init_data_3_0[] = { // .. ==> 0XF8000140[25:20] = 0x00000001U // .. ==> MASK : 0x03F00000U VAL : 0x00100000U // .. - EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100821U), + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U), // .. CLKACT = 0x1 // .. ==> 0XF800014C[0:0] = 0x00000001U // .. ==> MASK : 0x00000001U VAL : 0x00000001U @@ -4054,23 +4054,23 @@ unsigned long ps7_pll_init_data_2_0[] = { // .. FINISH: SLCR SETTINGS // .. START: PLL SLCR REGISTERS // .. .. START: ARM PLL INIT - // .. .. PLL_RES = 0xc - // .. .. ==> 0XF8000110[7:4] = 0x0000000CU - // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U // .. .. PLL_CP = 0x2 // .. .. ==> 0XF8000110[11:8] = 0x00000002U // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0x145 - // .. .. ==> 0XF8000110[21:12] = 0x00000145U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U // .. .. - EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001452C0U), + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x1e - // .. .. .. ==> 0XF8000100[18:12] = 0x0000001EU - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001E000U), + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), // .. .. .. FINISH: UPDATE FB_DIV // .. .. .. START: BY PASS PLL // .. .. .. PLL_BYPASS_FORCE = 1 @@ -4302,9 +4302,9 @@ unsigned long ps7_clock_init_data_2_0[] = { // .. CLKACT = 0x1 // .. ==> 0XF8000140[0:0] = 0x00000001U // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x2 - // .. ==> 0XF8000140[6:4] = 0x00000002U - // .. ==> MASK : 0x00000070U VAL : 0x00000020U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U // .. DIVISOR = 0x8 // .. ==> 0XF8000140[13:8] = 0x00000008U // .. ==> MASK : 0x00003F00U VAL : 0x00000800U @@ -4312,7 +4312,7 @@ unsigned long ps7_clock_init_data_2_0[] = { // .. ==> 0XF8000140[25:20] = 0x00000001U // .. ==> MASK : 0x03F00000U VAL : 0x00100000U // .. - EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100821U), + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U), // .. CLKACT = 0x1 // .. ==> 0XF800014C[0:0] = 0x00000001U // .. ==> MASK : 0x00000001U VAL : 0x00000001U @@ -8236,23 +8236,23 @@ unsigned long ps7_pll_init_data_1_0[] = { // .. FINISH: SLCR SETTINGS // .. START: PLL SLCR REGISTERS // .. .. START: ARM PLL INIT - // .. .. PLL_RES = 0xc - // .. .. ==> 0XF8000110[7:4] = 0x0000000CU - // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U // .. .. PLL_CP = 0x2 // .. .. ==> 0XF8000110[11:8] = 0x00000002U // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0x145 - // .. .. ==> 0XF8000110[21:12] = 0x00000145U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U // .. .. - EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001452C0U), + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x1e - // .. .. .. ==> 0XF8000100[18:12] = 0x0000001EU - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001E000U), + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), // .. .. .. FINISH: UPDATE FB_DIV // .. .. .. START: BY PASS PLL // .. .. .. PLL_BYPASS_FORCE = 1 @@ -8484,9 +8484,9 @@ unsigned long ps7_clock_init_data_1_0[] = { // .. CLKACT = 0x1 // .. ==> 0XF8000140[0:0] = 0x00000001U // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x2 - // .. ==> 0XF8000140[6:4] = 0x00000002U - // .. ==> MASK : 0x00000070U VAL : 0x00000020U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U // .. DIVISOR = 0x8 // .. ==> 0XF8000140[13:8] = 0x00000008U // .. ==> MASK : 0x00003F00U VAL : 0x00000800U @@ -8494,7 +8494,7 @@ unsigned long ps7_clock_init_data_1_0[] = { // .. ==> 0XF8000140[25:20] = 0x00000001U // .. ==> MASK : 0x03F00000U VAL : 0x00100000U // .. - EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100821U), + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U), // .. CLKACT = 0x1 // .. ==> 0XF800014C[0:0] = 0x00000001U // .. ==> MASK : 0x00000001U VAL : 0x00000001U diff --git a/fast-servo/fsbl-support/ps7_init_gpl.c b/fast-servo/fsbl-support/ps7_init_gpl.c index 1d568af..5ebf982 100644 --- a/fast-servo/fsbl-support/ps7_init_gpl.c +++ b/fast-servo/fsbl-support/ps7_init_gpl.c @@ -38,23 +38,23 @@ unsigned long ps7_pll_init_data_3_0[] = { // .. FINISH: SLCR SETTINGS // .. START: PLL SLCR REGISTERS // .. .. START: ARM PLL INIT - // .. .. PLL_RES = 0xc - // .. .. ==> 0XF8000110[7:4] = 0x0000000CU - // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U // .. .. PLL_CP = 0x2 // .. .. ==> 0XF8000110[11:8] = 0x00000002U // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0x145 - // .. .. ==> 0XF8000110[21:12] = 0x00000145U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U // .. .. - EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001452C0U), + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x1e - // .. .. .. ==> 0XF8000100[18:12] = 0x0000001EU - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001E000U), + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), // .. .. .. FINISH: UPDATE FB_DIV // .. .. .. START: BY PASS PLL // .. .. .. PLL_BYPASS_FORCE = 1 @@ -286,9 +286,9 @@ unsigned long ps7_clock_init_data_3_0[] = { // .. CLKACT = 0x1 // .. ==> 0XF8000140[0:0] = 0x00000001U // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x2 - // .. ==> 0XF8000140[6:4] = 0x00000002U - // .. ==> MASK : 0x00000070U VAL : 0x00000020U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U // .. DIVISOR = 0x8 // .. ==> 0XF8000140[13:8] = 0x00000008U // .. ==> MASK : 0x00003F00U VAL : 0x00000800U @@ -296,7 +296,7 @@ unsigned long ps7_clock_init_data_3_0[] = { // .. ==> 0XF8000140[25:20] = 0x00000001U // .. ==> MASK : 0x03F00000U VAL : 0x00100000U // .. - EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100821U), + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U), // .. CLKACT = 0x1 // .. ==> 0XF800014C[0:0] = 0x00000001U // .. ==> MASK : 0x00000001U VAL : 0x00000001U @@ -4067,23 +4067,23 @@ unsigned long ps7_pll_init_data_2_0[] = { // .. FINISH: SLCR SETTINGS // .. START: PLL SLCR REGISTERS // .. .. START: ARM PLL INIT - // .. .. PLL_RES = 0xc - // .. .. ==> 0XF8000110[7:4] = 0x0000000CU - // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U // .. .. PLL_CP = 0x2 // .. .. ==> 0XF8000110[11:8] = 0x00000002U // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0x145 - // .. .. ==> 0XF8000110[21:12] = 0x00000145U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U // .. .. - EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001452C0U), + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x1e - // .. .. .. ==> 0XF8000100[18:12] = 0x0000001EU - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001E000U), + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), // .. .. .. FINISH: UPDATE FB_DIV // .. .. .. START: BY PASS PLL // .. .. .. PLL_BYPASS_FORCE = 1 @@ -4315,9 +4315,9 @@ unsigned long ps7_clock_init_data_2_0[] = { // .. CLKACT = 0x1 // .. ==> 0XF8000140[0:0] = 0x00000001U // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x2 - // .. ==> 0XF8000140[6:4] = 0x00000002U - // .. ==> MASK : 0x00000070U VAL : 0x00000020U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U // .. DIVISOR = 0x8 // .. ==> 0XF8000140[13:8] = 0x00000008U // .. ==> MASK : 0x00003F00U VAL : 0x00000800U @@ -4325,7 +4325,7 @@ unsigned long ps7_clock_init_data_2_0[] = { // .. ==> 0XF8000140[25:20] = 0x00000001U // .. ==> MASK : 0x03F00000U VAL : 0x00100000U // .. - EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100821U), + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U), // .. CLKACT = 0x1 // .. ==> 0XF800014C[0:0] = 0x00000001U // .. ==> MASK : 0x00000001U VAL : 0x00000001U @@ -8249,23 +8249,23 @@ unsigned long ps7_pll_init_data_1_0[] = { // .. FINISH: SLCR SETTINGS // .. START: PLL SLCR REGISTERS // .. .. START: ARM PLL INIT - // .. .. PLL_RES = 0xc - // .. .. ==> 0XF8000110[7:4] = 0x0000000CU - // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U // .. .. PLL_CP = 0x2 // .. .. ==> 0XF8000110[11:8] = 0x00000002U // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0x145 - // .. .. ==> 0XF8000110[21:12] = 0x00000145U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U // .. .. - EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001452C0U), + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x1e - // .. .. .. ==> 0XF8000100[18:12] = 0x0000001EU - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001E000U), + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), // .. .. .. FINISH: UPDATE FB_DIV // .. .. .. START: BY PASS PLL // .. .. .. PLL_BYPASS_FORCE = 1 @@ -8497,9 +8497,9 @@ unsigned long ps7_clock_init_data_1_0[] = { // .. CLKACT = 0x1 // .. ==> 0XF8000140[0:0] = 0x00000001U // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x2 - // .. ==> 0XF8000140[6:4] = 0x00000002U - // .. ==> MASK : 0x00000070U VAL : 0x00000020U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U // .. DIVISOR = 0x8 // .. ==> 0XF8000140[13:8] = 0x00000008U // .. ==> MASK : 0x00003F00U VAL : 0x00000800U @@ -8507,7 +8507,7 @@ unsigned long ps7_clock_init_data_1_0[] = { // .. ==> 0XF8000140[25:20] = 0x00000001U // .. ==> MASK : 0x03F00000U VAL : 0x00100000U // .. - EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100821U), + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U), // .. CLKACT = 0x1 // .. ==> 0XF800014C[0:0] = 0x00000001U // .. ==> MASK : 0x00000001U VAL : 0x00000001U diff --git a/fast-servo/fsbl.patch b/fast-servo/fsbl.patch index 37ef792..0d25e0e 100644 --- a/fast-servo/fsbl.patch +++ b/fast-servo/fsbl.patch @@ -1,14 +1,8 @@ -diff --git a/lib/sw_apps/zynq_fsbl/misc/fast-servo/ps7_init.h b/lib/sw_apps/zynq_fsbl/misc/fast-servo/ps7_init.h -index 9572636306..2f3816271e 100644 ---- a/lib/sw_apps/zynq_fsbl/misc/fast-servo/ps7_init.h -+++ b/lib/sw_apps/zynq_fsbl/misc/fast-servo/ps7_init.h -@@ -67,20 +67,20 @@ extern unsigned long * ps7_peripherals_init_data; - - /* Freq of all peripherals */ - --#define APU_FREQ 666666687 -+#define APU_FREQ 500000000 - #define DDR_FREQ 533333374 +diff --git a/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init.h b/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init.h +index 9572636..1d79314 100644 +--- a/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init.h ++++ b/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init.h +@@ -72,20 +72,20 @@ extern unsigned long * ps7_peripherals_init_data; #define DCI_FREQ 10158730 #define QSPI_FREQ 200000000 #define SMC_FREQ 10000000 @@ -20,27 +14,25 @@ index 9572636306..2f3816271e 100644 -#define SDIO_FREQ 50000000 -#define UART_FREQ 50000000 -#define SPI_FREQ 10000000 --#define I2C_FREQ 111111115 --#define WDT_FREQ 111111115 +#define SDIO_FREQ 100000000 +#define UART_FREQ 100000000 +#define SPI_FREQ 166666672 -+#define I2C_FREQ 83333336 -+#define WDT_FREQ 83333336 + #define I2C_FREQ 111111115 + #define WDT_FREQ 111111115 #define TTC_FREQ 50000000 #define CAN_FREQ 10000000 #define PCAP_FREQ 200000000 -diff --git a/lib/sw_apps/zynq_fsbl/misc/fast-servo/ps7_init_gpl.h b/lib/sw_apps/zynq_fsbl/misc/fast-servo/ps7_init_gpl.h -index 8962bed427..df2f16adec 100644 ---- a/lib/sw_apps/zynq_fsbl/misc/fast-servo/ps7_init_gpl.h -+++ b/lib/sw_apps/zynq_fsbl/misc/fast-servo/ps7_init_gpl.h -@@ -81,20 +81,20 @@ extern unsigned long * ps7_peripherals_init_data; - - /* Freq of all peripherals */ - --#define APU_FREQ 666666687 -+#define APU_FREQ 500000000 - #define DDR_FREQ 533333374 + #define TPIU_FREQ 200000000 +-#define FPGA0_FREQ 50000000 ++#define FPGA0_FREQ 10000000 + #define FPGA1_FREQ 10000000 + #define FPGA2_FREQ 10000000 + #define FPGA3_FREQ 10000000 +diff --git a/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init_gpl.h b/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init_gpl.h +index 8962bed..562d5b5 100644 +--- a/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init_gpl.h ++++ b/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init_gpl.h +@@ -86,20 +86,20 @@ extern unsigned long * ps7_peripherals_init_data; #define DCI_FREQ 10158730 #define QSPI_FREQ 200000000 #define SMC_FREQ 10000000 @@ -52,33 +44,37 @@ index 8962bed427..df2f16adec 100644 -#define SDIO_FREQ 50000000 -#define UART_FREQ 50000000 -#define SPI_FREQ 10000000 --#define I2C_FREQ 111111115 --#define WDT_FREQ 111111115 +#define SDIO_FREQ 100000000 +#define UART_FREQ 100000000 +#define SPI_FREQ 166666672 -+#define I2C_FREQ 83333336 -+#define WDT_FREQ 83333336 + #define I2C_FREQ 111111115 + #define WDT_FREQ 111111115 #define TTC_FREQ 50000000 #define CAN_FREQ 10000000 #define PCAP_FREQ 200000000 + #define TPIU_FREQ 200000000 +-#define FPGA0_FREQ 50000000 ++#define FPGA0_FREQ 10000000 + #define FPGA1_FREQ 10000000 + #define FPGA2_FREQ 10000000 + #define FPGA3_FREQ 10000000 diff --git a/lib/sw_apps/zynq_fsbl/misc/fast-servo/xparameters.h b/lib/sw_apps/zynq_fsbl/misc/fast-servo/xparameters.h index 997a982ca1..5461fbb477 100644 ---- a/lib/sw_apps/zynq_fsbl/misc/fast-servo/xparameters.h +--- a/lib/sw_apps/zynq_fsbl/misc/fast-servo/xparameters +++ b/lib/sw_apps/zynq_fsbl/misc/fast-servo/xparameters.h @@ -9,21 +9,26 @@ #define XPAR_CPU_ID 0U /* Definitions for peripheral PS7_CORTEXA9_0 */ -#define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687 -+#define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 500000000 ++#define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687 /******************************************************************/ /* Canonical definitions for peripheral PS7_CORTEXA9_0 */ -#define XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687 -+#define XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ 500000000 ++#define XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687 /******************************************************************/ diff --git a/fast-servo/linien-gateware/fast_servo_platform.py b/fast-servo/linien-gateware/fast_servo_platform.py index 45ddd91..888812d 100644 --- a/fast-servo/linien-gateware/fast_servo_platform.py +++ b/fast-servo/linien-gateware/fast_servo_platform.py @@ -273,7 +273,7 @@ ps7_config_board_preset = { # ETHERNET "PCW_ACT_ENET0_PERIPHERAL_FREQMHZ" : "125", - "PCW_ENET0_PERIPHERAL_CLKSRC" : "ARM PLL", + "PCW_ENET0_PERIPHERAL_CLKSRC" : "IO PLL", "PCW_ENET0_PERIPHERAL_ENABLE" : "1", "PCW_ENET0_ENET0_IO" : "MIO 16 .. 27", "PCW_ENET0_GRP_MDIO_ENABLE" : "1",